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-rw-r--r--sim/mips/mips.igen12
1 files changed, 12 insertions, 0 deletions
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 3d4eeb0..fece487 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -55,7 +55,10 @@
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
@@ -978,6 +981,7 @@
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
@@ -1002,6 +1006,7 @@
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
@@ -1111,6 +1116,7 @@
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
@@ -1134,6 +1140,7 @@
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
@@ -2157,6 +2164,7 @@
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2176,6 +2184,7 @@
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2280,6 +2289,7 @@
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2299,6 +2309,7 @@
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2356,6 +2367,7 @@
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))