diff options
Diffstat (limited to 'sim/m32r')
| -rw-r--r-- | sim/m32r/ChangeLog | 14 | ||||
| -rw-r--r-- | sim/m32r/cpu.h | 560 | ||||
| -rw-r--r-- | sim/m32r/cpux.h | 694 | ||||
| -rw-r--r-- | sim/m32r/decodex.c | 345 | ||||
| -rw-r--r-- | sim/m32r/modelx.c | 1240 | ||||
| -rw-r--r-- | sim/m32r/semx-switch.c | 752 |
6 files changed, 1371 insertions, 2234 deletions
diff --git a/sim/m32r/ChangeLog b/sim/m32r/ChangeLog index 530de35..42fd22e 100644 --- a/sim/m32r/ChangeLog +++ b/sim/m32r/ChangeLog @@ -1,3 +1,17 @@ +1999-01-27 Doug Evans <devans@casey.cygnus.com> + + * cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild. +start-sanitize-m32rx + * cpux.h,decodex.c,modelx.c,semx-switch.c: Rebuild. +end-sanitize-m32rx + +1999-01-15 Doug Evans <devans@casey.cygnus.com> + + * decode.h,model.c: Regenerate. +start-sanitize-m32rx + * decodex.h,modelx.c: Regenerate. +end-sanitize-m32rx + 1999-01-14 Doug Evans <devans@casey.cygnus.com> start-sanitize-cygnus diff --git a/sim/m32r/cpu.h b/sim/m32r/cpu.h index 6f4f855..42d2d56 100644 --- a/sim/m32r/cpu.h +++ b/sim/m32r/cpu.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. This file is part of the GNU Simulators. @@ -119,7 +119,7 @@ typedef struct { } MODEL_TEST_DATA; union sem_fields { - struct { /* empty format for unspecified field list */ + struct { /* empty sformat for unspecified field list */ int empty; } fmt_empty; struct { /* e.g. add $dr,$sr */ @@ -189,10 +189,10 @@ union sem_fields { unsigned char in_src2; } fmt_cmpi; struct { /* e.g. div $dr,$sr */ - SI * i_sr; SI * i_dr; - unsigned char in_sr; + SI * i_sr; unsigned char in_dr; + unsigned char in_sr; unsigned char out_dr; } fmt_div; struct { /* e.g. ld $dr,@$sr */ @@ -323,56 +323,56 @@ union sem_fields { unsigned char out_dr; } fmt_slli; struct { /* e.g. st $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_st; struct { /* e.g. st $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_st_d; struct { /* e.g. stb $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_stb; struct { /* e.g. stb $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_stb_d; struct { /* e.g. sth $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_sth; struct { /* e.g. sth $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_sth_d; struct { /* e.g. st $src1,@+$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; unsigned char out_src2; } fmt_st_plus; struct { /* e.g. unlock $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_unlock; /* cti insns, kept separately so addr_cache is in fixed place */ struct { @@ -384,15 +384,15 @@ union sem_fields { IADDR i_disp24; } fmt_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ + IADDR i_disp16; SI * i_src1; SI * i_src2; - IADDR i_disp16; unsigned char in_src1; unsigned char in_src2; } fmt_beq; struct { /* e.g. beqz $src2,$disp16 */ - SI * i_src2; IADDR i_disp16; + SI * i_src2; unsigned char in_src2; } fmt_beqz; struct { /* e.g. bl.s $disp8 */ @@ -457,7 +457,7 @@ union sem_fields { /* The ARGBUF struct. */ struct argbuf { /* These are the baseclass definitions. */ - PCADDR addr; + IADDR addr; const IDESC *idesc; char trace_p; char profile_p; @@ -480,27 +480,27 @@ struct scache { /* Macros to simplify extraction, reading and semantic code. These define and assign the local vars that contain the insn's fields. */ -#define EXTRACT_FMT_EMPTY_VARS \ +#define EXTRACT_IFMT_EMPTY_VARS \ /* Instruction fields. */ \ unsigned int length; -#define EXTRACT_FMT_EMPTY_CODE \ +#define EXTRACT_IFMT_EMPTY_CODE \ length = 0; \ -#define EXTRACT_FMT_ADD_VARS \ +#define EXTRACT_IFMT_ADD_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_ADD_CODE \ +#define EXTRACT_IFMT_ADD_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_ADD3_VARS \ +#define EXTRACT_IFMT_ADD3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -508,7 +508,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_ADD3_CODE \ +#define EXTRACT_IFMT_ADD3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -516,7 +516,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_AND3_VARS \ +#define EXTRACT_IFMT_AND3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -524,7 +524,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_AND3_CODE \ +#define EXTRACT_IFMT_AND3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -532,7 +532,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_OR3_VARS \ +#define EXTRACT_IFMT_OR3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -540,7 +540,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_OR3_CODE \ +#define EXTRACT_IFMT_OR3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -548,33 +548,19 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_ADDI_VARS \ +#define EXTRACT_IFMT_ADDI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ INT f_simm8; \ unsigned int length; -#define EXTRACT_FMT_ADDI_CODE \ +#define EXTRACT_IFMT_ADDI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ -#define EXTRACT_FMT_ADDV_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ADDV_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_ADDV3_VARS \ +#define EXTRACT_IFMT_ADDV3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -582,7 +568,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_ADDV3_CODE \ +#define EXTRACT_IFMT_ADDV3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -590,45 +576,31 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_ADDX_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ADDX_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_BC8_VARS \ +#define EXTRACT_IFMT_BC8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp8; \ unsigned int length; -#define EXTRACT_FMT_BC8_CODE \ +#define EXTRACT_IFMT_BC8_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ -#define EXTRACT_FMT_BC24_VARS \ +#define EXTRACT_IFMT_BC24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp24; \ unsigned int length; -#define EXTRACT_FMT_BC24_CODE \ +#define EXTRACT_IFMT_BC24_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BEQ_VARS \ +#define EXTRACT_IFMT_BEQ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -636,7 +608,7 @@ struct scache { UINT f_r2; \ SI f_disp16; \ unsigned int length; -#define EXTRACT_FMT_BEQ_CODE \ +#define EXTRACT_IFMT_BEQ_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -644,7 +616,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BEQZ_VARS \ +#define EXTRACT_IFMT_BEQZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -652,7 +624,7 @@ struct scache { UINT f_r2; \ SI f_disp16; \ unsigned int length; -#define EXTRACT_FMT_BEQZ_CODE \ +#define EXTRACT_IFMT_BEQZ_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -660,69 +632,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BL8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp8; \ - unsigned int length; -#define EXTRACT_FMT_BL8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ - -#define EXTRACT_FMT_BL24_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp24; \ - unsigned int length; -#define EXTRACT_FMT_BL24_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ - -#define EXTRACT_FMT_BRA8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp8; \ - unsigned int length; -#define EXTRACT_FMT_BRA8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ - -#define EXTRACT_FMT_BRA24_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp24; \ - unsigned int length; -#define EXTRACT_FMT_BRA24_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ - -#define EXTRACT_FMT_CMP_VARS \ +#define EXTRACT_IFMT_CMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_CMP_CODE \ +#define EXTRACT_IFMT_CMP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_CMPI_VARS \ +#define EXTRACT_IFMT_CMPI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -730,7 +654,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_CMPI_CODE \ +#define EXTRACT_IFMT_CMPI_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -738,125 +662,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_DIV_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_DIV_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_JL_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_JL_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_JMP_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_JMP_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LD_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LD_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LD_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_LD_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_LDB_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LDB_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LDB_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_LDB_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_LDH_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LDH_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LDH_D_VARS \ +#define EXTRACT_IFMT_DIV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -864,7 +670,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_LDH_D_CODE \ +#define EXTRACT_IFMT_DIV_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -872,45 +678,33 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_LD_PLUS_VARS \ +#define EXTRACT_IFMT_JL_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_LD_PLUS_CODE \ +#define EXTRACT_IFMT_JL_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_LD24_VARS \ +#define EXTRACT_IFMT_LD24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_uimm24; \ unsigned int length; -#define EXTRACT_FMT_LD24_CODE \ +#define EXTRACT_IFMT_LD24_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \ -#define EXTRACT_FMT_LDI8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - INT f_simm8; \ - unsigned int length; -#define EXTRACT_FMT_LDI8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ - -#define EXTRACT_FMT_LDI16_VARS \ +#define EXTRACT_IFMT_LDI16_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -918,7 +712,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_LDI16_CODE \ +#define EXTRACT_IFMT_LDI16_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -926,161 +720,77 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_LOCK_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LOCK_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MACHI_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MACHI_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MULHI_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MULHI_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MV_VARS \ +#define EXTRACT_IFMT_MVFACHI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MV_CODE \ +#define EXTRACT_IFMT_MVFACHI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MVFACHI_VARS \ +#define EXTRACT_IFMT_MVFC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVFACHI_CODE \ +#define EXTRACT_IFMT_MVFC_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MVFC_VARS \ +#define EXTRACT_IFMT_MVTACHI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVFC_CODE \ +#define EXTRACT_IFMT_MVTACHI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MVTACHI_VARS \ +#define EXTRACT_IFMT_MVTC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVTACHI_CODE \ +#define EXTRACT_IFMT_MVTC_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MVTC_VARS \ +#define EXTRACT_IFMT_NOP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVTC_CODE \ +#define EXTRACT_IFMT_NOP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_NOP_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_NOP_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_RAC_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_RAC_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_RTE_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_RTE_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_SETH_VARS \ +#define EXTRACT_IFMT_SETH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1088,7 +798,7 @@ struct scache { UINT f_r2; \ UINT f_hi16; \ unsigned int length; -#define EXTRACT_FMT_SETH_CODE \ +#define EXTRACT_IFMT_SETH_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1096,51 +806,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_SLL3_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_SLL3_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_SLLI_VARS \ +#define EXTRACT_IFMT_SLLI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_shift_op2; \ UINT f_uimm5; \ unsigned int length; -#define EXTRACT_FMT_SLLI_CODE \ +#define EXTRACT_IFMT_SLLI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \ f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \ -#define EXTRACT_FMT_ST_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ST_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_ST_D_VARS \ +#define EXTRACT_IFMT_ST_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1148,7 +828,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_ST_D_CODE \ +#define EXTRACT_IFMT_ST_D_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1156,112 +836,24 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_STB_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_STB_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_STB_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_STB_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_STH_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_STH_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_STH_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_STH_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_ST_PLUS_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ST_PLUS_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_TRAP_VARS \ +#define EXTRACT_IFMT_TRAP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_uimm4; \ unsigned int length; -#define EXTRACT_FMT_TRAP_CODE \ +#define EXTRACT_IFMT_TRAP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_UNLOCK_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_UNLOCK_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - /* Collection of various things for the trace handler to use. */ typedef struct trace_record { - PCADDR pc; + IADDR pc; /* FIXME:wip */ } TRACE_RECORD; diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h index 6323b18..c8894df 100644 --- a/sim/m32r/cpux.h +++ b/sim/m32r/cpux.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. This file is part of the GNU Simulators. @@ -115,7 +115,7 @@ typedef struct { } MODEL_M32RX_DATA; union sem_fields { - struct { /* empty format for unspecified field list */ + struct { /* empty sformat for unspecified field list */ int empty; } fmt_empty; struct { /* e.g. add $dr,$sr */ @@ -189,10 +189,10 @@ union sem_fields { unsigned char in_src2; } fmt_cmpz; struct { /* e.g. div $dr,$sr */ - SI * i_sr; SI * i_dr; - unsigned char in_sr; + SI * i_sr; unsigned char in_dr; + unsigned char in_sr; unsigned char out_dr; } fmt_div; struct { /* e.g. ld $dr,@$sr */ @@ -329,56 +329,56 @@ union sem_fields { unsigned char out_dr; } fmt_slli; struct { /* e.g. st $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_st; struct { /* e.g. st $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_st_d; struct { /* e.g. stb $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_stb; struct { /* e.g. stb $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_stb_d; struct { /* e.g. sth $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_sth; struct { /* e.g. sth $src1,@($slo16,$src2) */ INT f_simm16; - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_sth_d; struct { /* e.g. st $src1,@+$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; unsigned char out_src2; } fmt_st_plus; struct { /* e.g. unlock $src1,@$src2 */ - SI * i_src2; SI * i_src1; - unsigned char in_src2; + SI * i_src2; unsigned char in_src1; + unsigned char in_src2; } fmt_unlock; struct { /* e.g. satb $dr,$sr */ SI * i_sr; @@ -423,15 +423,15 @@ union sem_fields { IADDR i_disp24; } fmt_bc24; struct { /* e.g. beq $src1,$src2,$disp16 */ + IADDR i_disp16; SI * i_src1; SI * i_src2; - IADDR i_disp16; unsigned char in_src1; unsigned char in_src2; } fmt_beq; struct { /* e.g. beqz $src2,$disp16 */ - SI * i_src2; IADDR i_disp16; + SI * i_src2; unsigned char in_src2; } fmt_beqz; struct { /* e.g. bl.s $disp8 */ @@ -511,7 +511,7 @@ union sem_fields { /* The ARGBUF struct. */ struct argbuf { /* These are the baseclass definitions. */ - PCADDR addr; + IADDR addr; const IDESC *idesc; char trace_p; char profile_p; @@ -534,27 +534,27 @@ struct scache { /* Macros to simplify extraction, reading and semantic code. These define and assign the local vars that contain the insn's fields. */ -#define EXTRACT_FMT_EMPTY_VARS \ +#define EXTRACT_IFMT_EMPTY_VARS \ /* Instruction fields. */ \ unsigned int length; -#define EXTRACT_FMT_EMPTY_CODE \ +#define EXTRACT_IFMT_EMPTY_CODE \ length = 0; \ -#define EXTRACT_FMT_ADD_VARS \ +#define EXTRACT_IFMT_ADD_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_ADD_CODE \ +#define EXTRACT_IFMT_ADD_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_ADD3_VARS \ +#define EXTRACT_IFMT_ADD3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -562,7 +562,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_ADD3_CODE \ +#define EXTRACT_IFMT_ADD3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -570,7 +570,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_AND3_VARS \ +#define EXTRACT_IFMT_AND3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -578,7 +578,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_AND3_CODE \ +#define EXTRACT_IFMT_AND3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -586,7 +586,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_OR3_VARS \ +#define EXTRACT_IFMT_OR3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -594,7 +594,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_OR3_CODE \ +#define EXTRACT_IFMT_OR3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -602,33 +602,19 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_ADDI_VARS \ +#define EXTRACT_IFMT_ADDI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ INT f_simm8; \ unsigned int length; -#define EXTRACT_FMT_ADDI_CODE \ +#define EXTRACT_IFMT_ADDI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ -#define EXTRACT_FMT_ADDV_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ADDV_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_ADDV3_VARS \ +#define EXTRACT_IFMT_ADDV3_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -636,7 +622,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_ADDV3_CODE \ +#define EXTRACT_IFMT_ADDV3_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -644,45 +630,31 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_ADDX_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ADDX_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_BC8_VARS \ +#define EXTRACT_IFMT_BC8_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp8; \ unsigned int length; -#define EXTRACT_FMT_BC8_CODE \ +#define EXTRACT_IFMT_BC8_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ -#define EXTRACT_FMT_BC24_VARS \ +#define EXTRACT_IFMT_BC24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ SI f_disp24; \ unsigned int length; -#define EXTRACT_FMT_BC24_CODE \ +#define EXTRACT_IFMT_BC24_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BEQ_VARS \ +#define EXTRACT_IFMT_BEQ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -690,7 +662,7 @@ struct scache { UINT f_r2; \ SI f_disp16; \ unsigned int length; -#define EXTRACT_FMT_BEQ_CODE \ +#define EXTRACT_IFMT_BEQ_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -698,7 +670,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BEQZ_VARS \ +#define EXTRACT_IFMT_BEQZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -706,7 +678,7 @@ struct scache { UINT f_r2; \ SI f_disp16; \ unsigned int length; -#define EXTRACT_FMT_BEQZ_CODE \ +#define EXTRACT_IFMT_BEQZ_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -714,93 +686,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \ -#define EXTRACT_FMT_BL8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp8; \ - unsigned int length; -#define EXTRACT_FMT_BL8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ - -#define EXTRACT_FMT_BL24_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp24; \ - unsigned int length; -#define EXTRACT_FMT_BL24_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ - -#define EXTRACT_FMT_BCL8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp8; \ - unsigned int length; -#define EXTRACT_FMT_BCL8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ - -#define EXTRACT_FMT_BCL24_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp24; \ - unsigned int length; -#define EXTRACT_FMT_BCL24_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ - -#define EXTRACT_FMT_BRA8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp8; \ - unsigned int length; -#define EXTRACT_FMT_BRA8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \ - -#define EXTRACT_FMT_BRA24_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - SI f_disp24; \ - unsigned int length; -#define EXTRACT_FMT_BRA24_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \ - -#define EXTRACT_FMT_CMP_VARS \ +#define EXTRACT_IFMT_CMP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_CMP_CODE \ +#define EXTRACT_IFMT_CMP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_CMPI_VARS \ +#define EXTRACT_IFMT_CMPI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -808,7 +708,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_CMPI_CODE \ +#define EXTRACT_IFMT_CMPI_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -816,21 +716,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_CMPZ_VARS \ +#define EXTRACT_IFMT_CMPZ_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_CMPZ_CODE \ +#define EXTRACT_IFMT_CMPZ_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_DIV_VARS \ +#define EXTRACT_IFMT_DIV_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -838,7 +738,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_DIV_CODE \ +#define EXTRACT_IFMT_DIV_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -846,177 +746,33 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_JC_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_JC_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_JL_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_JL_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_JMP_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_JMP_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LD_VARS \ +#define EXTRACT_IFMT_JC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_LD_CODE \ +#define EXTRACT_IFMT_JC_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_LD_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_LD_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_LDB_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LDB_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LDB_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_LDB_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_LDH_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LDH_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LDH_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_LDH_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_LD_PLUS_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LD_PLUS_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_LD24_VARS \ +#define EXTRACT_IFMT_LD24_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_uimm24; \ unsigned int length; -#define EXTRACT_FMT_LD24_CODE \ +#define EXTRACT_IFMT_LD24_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \ -#define EXTRACT_FMT_LDI8_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - INT f_simm8; \ - unsigned int length; -#define EXTRACT_FMT_LDI8_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \ - -#define EXTRACT_FMT_LDI16_VARS \ +#define EXTRACT_IFMT_LDI16_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1024,7 +780,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_LDI16_CODE \ +#define EXTRACT_IFMT_LDI16_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1032,21 +788,7 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_LOCK_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_LOCK_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MACHI_A_VARS \ +#define EXTRACT_IFMT_MACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1054,7 +796,7 @@ struct scache { UINT f_op23; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MACHI_A_CODE \ +#define EXTRACT_IFMT_MACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ @@ -1062,37 +804,7 @@ struct scache { f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MULHI_A_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_acc; \ - UINT f_op23; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MULHI_A_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_acc = EXTRACT_UINT (insn, 16, 8, 1); \ - f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MV_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MV_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MVFACHI_A_VARS \ +#define EXTRACT_IFMT_MVFACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1100,7 +812,7 @@ struct scache { UINT f_accs; \ UINT f_op3; \ unsigned int length; -#define EXTRACT_FMT_MVFACHI_A_CODE \ +#define EXTRACT_IFMT_MVFACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ @@ -1108,21 +820,21 @@ struct scache { f_accs = EXTRACT_UINT (insn, 16, 12, 2); \ f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \ -#define EXTRACT_FMT_MVFC_VARS \ +#define EXTRACT_IFMT_MVFC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVFC_CODE \ +#define EXTRACT_IFMT_MVFC_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_MVTACHI_A_VARS \ +#define EXTRACT_IFMT_MVTACHI_A_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1130,7 +842,7 @@ struct scache { UINT f_accs; \ UINT f_op3; \ unsigned int length; -#define EXTRACT_FMT_MVTACHI_A_CODE \ +#define EXTRACT_IFMT_MVTACHI_A_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ @@ -1138,35 +850,35 @@ struct scache { f_accs = EXTRACT_UINT (insn, 16, 12, 2); \ f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \ -#define EXTRACT_FMT_MVTC_VARS \ +#define EXTRACT_IFMT_MVTC_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_MVTC_CODE \ +#define EXTRACT_IFMT_MVTC_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_NOP_VARS \ +#define EXTRACT_IFMT_NOP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_r2; \ unsigned int length; -#define EXTRACT_FMT_NOP_CODE \ +#define EXTRACT_IFMT_NOP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_RAC_DSI_VARS \ +#define EXTRACT_IFMT_RAC_DSI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_accd; \ @@ -1176,7 +888,7 @@ struct scache { UINT f_bit14; \ SI f_imm1; \ unsigned int length; -#define EXTRACT_FMT_RAC_DSI_CODE \ +#define EXTRACT_IFMT_RAC_DSI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_accd = EXTRACT_UINT (insn, 16, 4, 2); \ @@ -1186,21 +898,7 @@ struct scache { f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \ f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \ -#define EXTRACT_FMT_RTE_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_RTE_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_SETH_VARS \ +#define EXTRACT_IFMT_SETH_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1208,7 +906,7 @@ struct scache { UINT f_r2; \ UINT f_hi16; \ unsigned int length; -#define EXTRACT_FMT_SETH_CODE \ +#define EXTRACT_IFMT_SETH_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1216,111 +914,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_SLL3_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_SLL3_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_SLLI_VARS \ +#define EXTRACT_IFMT_SLLI_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_shift_op2; \ UINT f_uimm5; \ unsigned int length; -#define EXTRACT_FMT_SLLI_CODE \ +#define EXTRACT_IFMT_SLLI_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \ f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \ -#define EXTRACT_FMT_ST_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ST_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_ST_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_ST_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_STB_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_STB_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_STB_D_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - INT f_simm16; \ - unsigned int length; -#define EXTRACT_FMT_STB_D_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_STH_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_STH_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_STH_D_VARS \ +#define EXTRACT_IFMT_ST_D_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1328,7 +936,7 @@ struct scache { UINT f_r2; \ INT f_simm16; \ unsigned int length; -#define EXTRACT_FMT_STH_D_CODE \ +#define EXTRACT_IFMT_ST_D_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1336,49 +944,21 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_ST_PLUS_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_ST_PLUS_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_TRAP_VARS \ +#define EXTRACT_IFMT_TRAP_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ UINT f_op2; \ UINT f_uimm4; \ unsigned int length; -#define EXTRACT_FMT_TRAP_CODE \ +#define EXTRACT_IFMT_TRAP_CODE \ length = 2; \ f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \ -#define EXTRACT_FMT_UNLOCK_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_UNLOCK_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_SATB_VARS \ +#define EXTRACT_IFMT_SATB_VARS \ /* Instruction fields. */ \ UINT f_op1; \ UINT f_r1; \ @@ -1386,7 +966,7 @@ struct scache { UINT f_r2; \ UINT f_uimm16; \ unsigned int length; -#define EXTRACT_FMT_SATB_CODE \ +#define EXTRACT_IFMT_SATB_CODE \ length = 4; \ f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ @@ -1394,97 +974,11 @@ struct scache { f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ -#define EXTRACT_FMT_SAT_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - UINT f_uimm16; \ - unsigned int length; -#define EXTRACT_FMT_SAT_CODE \ - length = 4; \ - f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \ - f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \ - -#define EXTRACT_FMT_SADD_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_SADD_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MACWU1_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MACWU1_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MSBLO_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MSBLO_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_MULWU1_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_MULWU1_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - -#define EXTRACT_FMT_SC_VARS \ - /* Instruction fields. */ \ - UINT f_op1; \ - UINT f_r1; \ - UINT f_op2; \ - UINT f_r2; \ - unsigned int length; -#define EXTRACT_FMT_SC_CODE \ - length = 2; \ - f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \ - f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \ - f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \ - f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \ - /* Queued output values of an instruction. */ struct parexec { union { - struct { /* empty format for unspecified field list */ + struct { /* empty sformat for unspecified field list */ int empty; } fmt_empty; struct { /* e.g. add $dr,$sr */ @@ -1503,16 +997,16 @@ struct parexec { SI dr; } fmt_addi; struct { /* e.g. addv $dr,$sr */ - SI dr; BI condbit; + SI dr; } fmt_addv; struct { /* e.g. addv3 $dr,$sr,$simm16 */ - SI dr; BI condbit; + SI dr; } fmt_addv3; struct { /* e.g. addx $dr,$sr */ - SI dr; BI condbit; + SI dr; } fmt_addx; struct { /* e.g. bc.s $disp8 */ USI pc; @@ -1602,8 +1096,8 @@ struct parexec { SI dr; } fmt_ldi16; struct { /* e.g. lock $dr,@$sr */ - BI h_lock_0; SI dr; + BI h_lock_0; } fmt_lock; struct { /* e.g. machi $src1,$src2,$acc */ DI acc; @@ -1633,10 +1127,10 @@ struct parexec { DI accd; } fmt_rac_dsi; struct { /* e.g. rte */ - USI pc; + UQI h_bpsw_0; USI h_cr_6; UQI h_psw_0; - UQI h_bpsw_0; + USI pc; } fmt_rte; struct { /* e.g. seth $dr,$hash$hi16 */ SI dr; @@ -1677,17 +1171,17 @@ struct parexec { SI src2; } fmt_st_plus; struct { /* e.g. trap $uimm4 */ - USI h_cr_14; - USI h_cr_6; UQI h_bbpsw_0; UQI h_bpsw_0; + USI h_cr_14; + USI h_cr_6; UQI h_psw_0; SI pc; } fmt_trap; struct { /* e.g. unlock $src1,@$src2 */ + BI h_lock_0; SI h_memory_src2; USI h_memory_src2_idx; - BI h_lock_0; } fmt_unlock; struct { /* e.g. satb $dr,$sr */ SI dr; @@ -1718,7 +1212,7 @@ struct parexec { /* Collection of various things for the trace handler to use. */ typedef struct trace_record { - PCADDR pc; + IADDR pc; /* FIXME:wip */ } TRACE_RECORD; diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c index d1cd21f..bc61f5d 100644 --- a/sim/m32r/decodex.c +++ b/sim/m32r/decodex.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. This file is part of the GNU Simulators. @@ -302,8 +302,8 @@ m32rxf_init_idesc_table (SIM_CPU *cpu) CPU_IDESC (cpu) = table; } -/* Enum declaration for all instruction formats. */ -typedef enum ifmt { +/* Enum declaration for all instruction semantic formats. */ +typedef enum sfmt { FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3 , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3 , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ @@ -321,23 +321,23 @@ typedef enum ifmt { , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK, FMT_SATB , FMT_SAT, FMT_SADD, FMT_MACWU1, FMT_MSBLO , FMT_MULWU1, FMT_SC -} IFMT; +} SFMT; /* The decoder uses this to record insns and direct extraction handling. */ typedef struct { const IDESC *idesc; #ifdef __GNUC__ - void *ifmt; + void *sfmt; #else - enum ifmt ifmt; + enum sfmt sfmt; #endif } DECODE_DESC; /* Macro to go from decode phase to extraction phase. */ #ifdef __GNUC__ -#define GOTO_EXTRACT(id) goto *(id)->ifmt +#define GOTO_EXTRACT(id) goto *(id)->sfmt #else #define GOTO_EXTRACT(id) goto extract #endif @@ -352,7 +352,7 @@ typedef struct { /* Given an instruction, return a pointer to its IDESC entry. */ const IDESC * -m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, +m32rxf_decode (SIM_CPU *current_cpu, IADDR pc, CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn, ARGBUF *abuf) { @@ -370,6 +370,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, #endif CGEN_INSN_INT insn = base_insn; static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) }; + { #ifdef __GNUC__ static const void *labels_0[256] = { @@ -843,7 +844,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, extract: { #ifndef __GNUC__ - switch (idecode->ifmt) + switch (idecode->sfmt) #endif { @@ -851,9 +852,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_empty.f - EXTRACT_FMT_EMPTY_VARS /* */ + EXTRACT_IFMT_EMPTY_VARS /* */ - EXTRACT_FMT_EMPTY_CODE + EXTRACT_IFMT_EMPTY_CODE /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0)); @@ -866,9 +867,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_add.f - EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_ADD_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; @@ -892,9 +893,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_add3.f - EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_ADD3_CODE + EXTRACT_IFMT_ADD3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -918,9 +919,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_and3.f - EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_AND3_CODE + EXTRACT_IFMT_AND3_CODE /* Record the fields for the semantic handler. */ FLD (f_uimm16) = f_uimm16; @@ -944,9 +945,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_or3.f - EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_OR3_CODE + EXTRACT_IFMT_OR3_CODE /* Record the fields for the semantic handler. */ FLD (f_uimm16) = f_uimm16; @@ -970,9 +971,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addi.f - EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ + EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ - EXTRACT_FMT_ADDI_CODE + EXTRACT_IFMT_ADDI_CODE /* Record the fields for the semantic handler. */ FLD (f_simm8) = f_simm8; @@ -995,9 +996,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addv.f - EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_ADDV_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; @@ -1021,9 +1022,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addv3.f - EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_ADDV3_CODE + EXTRACT_IFMT_ADDV3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1047,9 +1048,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_addx.f - EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_ADDX_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_dr) = & CPU (h_gr)[f_r1]; @@ -1073,9 +1074,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f - EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ + EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ - EXTRACT_FMT_BC8_CODE + EXTRACT_IFMT_BC8_CODE /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; @@ -1096,9 +1097,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f - EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ + EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ - EXTRACT_FMT_BC24_CODE + EXTRACT_IFMT_BC24_CODE /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; @@ -1119,16 +1120,16 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beq.f - EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ + EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ - EXTRACT_FMT_BEQ_CODE + EXTRACT_IFMT_BEQ_CODE /* Record the fields for the semantic handler. */ + FLD (i_disp16) = f_disp16; FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src2) = & CPU (h_gr)[f_r2]; - FLD (i_disp16) = f_disp16; SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1146,15 +1147,15 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f - EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ + EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */ - EXTRACT_FMT_BEQZ_CODE + EXTRACT_IFMT_BEQZ_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_disp16) = f_disp16; + FLD (i_src2) = & CPU (h_gr)[f_r2]; SEM_BRANCH_INIT_EXTRACT (abuf); - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ @@ -1171,9 +1172,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f - EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */ + EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ - EXTRACT_FMT_BL8_CODE + EXTRACT_IFMT_BC8_CODE /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; @@ -1195,9 +1196,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f - EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */ + EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ - EXTRACT_FMT_BL24_CODE + EXTRACT_IFMT_BC24_CODE /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; @@ -1219,9 +1220,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f - EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */ + EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ - EXTRACT_FMT_BCL8_CODE + EXTRACT_IFMT_BC8_CODE /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; @@ -1243,9 +1244,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f - EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */ + EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ - EXTRACT_FMT_BCL24_CODE + EXTRACT_IFMT_BC24_CODE /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; @@ -1267,9 +1268,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f - EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */ + EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */ - EXTRACT_FMT_BRA8_CODE + EXTRACT_IFMT_BC8_CODE /* Record the fields for the semantic handler. */ FLD (i_disp8) = f_disp8; @@ -1290,9 +1291,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f - EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */ + EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */ - EXTRACT_FMT_BRA24_CODE + EXTRACT_IFMT_BC24_CODE /* Record the fields for the semantic handler. */ FLD (i_disp24) = f_disp24; @@ -1313,9 +1314,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_cmp.f - EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_CMP_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; @@ -1338,9 +1339,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_cmpi.f - EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_CMPI_CODE + EXTRACT_IFMT_CMPI_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1362,9 +1363,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_cmpz.f - EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_CMPZ_CODE + EXTRACT_IFMT_CMPZ_CODE /* Record the fields for the semantic handler. */ FLD (i_src2) = & CPU (h_gr)[f_r2]; @@ -1385,21 +1386,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_div.f - EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_DIV_CODE + EXTRACT_IFMT_DIV_CODE /* Record the fields for the semantic handler. */ - FLD (i_sr) = & CPU (h_gr)[f_r2]; FLD (i_dr) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_sr) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_sr) = f_r2; FLD (in_dr) = f_r1; + FLD (in_sr) = f_r2; FLD (out_dr) = f_r1; } #endif @@ -1411,9 +1412,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jc.f - EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_JC_CODE + EXTRACT_IFMT_JC_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1435,9 +1436,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jl.f - EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_JL_CODE + EXTRACT_IFMT_JC_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1460,9 +1461,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f - EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_JMP_CODE + EXTRACT_IFMT_JC_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1484,9 +1485,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld.f - EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_LD_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1509,9 +1510,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld_d.f - EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_LD_D_CODE + EXTRACT_IFMT_ADD3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1535,9 +1536,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldb.f - EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_LDB_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1560,9 +1561,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldb_d.f - EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_LDB_D_CODE + EXTRACT_IFMT_ADD3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1586,9 +1587,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldh.f - EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_LDH_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1611,9 +1612,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldh_d.f - EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_LDH_D_CODE + EXTRACT_IFMT_ADD3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1637,9 +1638,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld_plus.f - EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_LD_PLUS_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1663,9 +1664,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ld24.f - EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */ + EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */ - EXTRACT_FMT_LD24_CODE + EXTRACT_IFMT_LD24_CODE /* Record the fields for the semantic handler. */ FLD (i_uimm24) = f_uimm24; @@ -1687,9 +1688,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldi8.f - EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */ + EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */ - EXTRACT_FMT_LDI8_CODE + EXTRACT_IFMT_ADDI_CODE /* Record the fields for the semantic handler. */ FLD (f_simm8) = f_simm8; @@ -1711,9 +1712,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_ldi16.f - EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_LDI16_CODE + EXTRACT_IFMT_LDI16_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -1735,9 +1736,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_lock.f - EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_LOCK_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1760,9 +1761,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_machi_a.f - EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ + EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ - EXTRACT_FMT_MACHI_A_CODE + EXTRACT_IFMT_MACHI_A_CODE /* Record the fields for the semantic handler. */ FLD (f_acc) = f_acc; @@ -1786,9 +1787,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mulhi_a.f - EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ + EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */ - EXTRACT_FMT_MULHI_A_CODE + EXTRACT_IFMT_MACHI_A_CODE /* Record the fields for the semantic handler. */ FLD (f_acc) = f_acc; @@ -1812,9 +1813,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mv.f - EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MV_CODE + EXTRACT_IFMT_ADD_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -1837,9 +1838,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvfachi_a.f - EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ + EXTRACT_IFMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ - EXTRACT_FMT_MVFACHI_A_CODE + EXTRACT_IFMT_MVFACHI_A_CODE /* Record the fields for the semantic handler. */ FLD (f_accs) = f_accs; @@ -1861,9 +1862,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvfc.f - EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MVFC_CODE + EXTRACT_IFMT_MVFC_CODE /* Record the fields for the semantic handler. */ FLD (f_r2) = f_r2; @@ -1885,9 +1886,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvtachi_a.f - EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ + EXTRACT_IFMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */ - EXTRACT_FMT_MVTACHI_A_CODE + EXTRACT_IFMT_MVTACHI_A_CODE /* Record the fields for the semantic handler. */ FLD (f_accs) = f_accs; @@ -1909,9 +1910,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mvtc.f - EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MVTC_CODE + EXTRACT_IFMT_MVTC_CODE /* Record the fields for the semantic handler. */ FLD (f_r1) = f_r1; @@ -1933,9 +1934,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_nop.f - EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_NOP_CODE + EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0)); @@ -1948,9 +1949,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_rac_dsi.f - EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ + EXTRACT_IFMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */ - EXTRACT_FMT_RAC_DSI_CODE + EXTRACT_IFMT_RAC_DSI_CODE /* Record the fields for the semantic handler. */ FLD (f_accs) = f_accs; @@ -1966,9 +1967,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_rte.f - EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_RTE_CODE + EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ SEM_BRANCH_INIT_EXTRACT (abuf); @@ -1988,9 +1989,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_seth.f - EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ + EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */ - EXTRACT_FMT_SETH_CODE + EXTRACT_IFMT_SETH_CODE /* Record the fields for the semantic handler. */ FLD (f_hi16) = f_hi16; @@ -2012,9 +2013,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sll3.f - EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_SLL3_CODE + EXTRACT_IFMT_ADDV3_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; @@ -2038,9 +2039,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_slli.f - EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ + EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */ - EXTRACT_FMT_SLLI_CODE + EXTRACT_IFMT_SLLI_CODE /* Record the fields for the semantic handler. */ FLD (f_uimm5) = f_uimm5; @@ -2063,21 +2064,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st.f - EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_ST_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2088,22 +2089,22 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st_d.f - EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_ST_D_CODE + EXTRACT_IFMT_ST_D_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2114,21 +2115,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_stb.f - EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_STB_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2139,22 +2140,22 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_stb_d.f - EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_STB_D_CODE + EXTRACT_IFMT_ST_D_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2165,21 +2166,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sth.f - EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_STH_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2190,22 +2191,22 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sth_d.f - EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ + EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */ - EXTRACT_FMT_STH_D_CODE + EXTRACT_IFMT_ST_D_CODE /* Record the fields for the semantic handler. */ FLD (f_simm16) = f_simm16; - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2216,21 +2217,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_st_plus.f - EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_ST_PLUS_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; FLD (out_src2) = f_r2; } #endif @@ -2242,9 +2243,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_trap.f - EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ + EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */ - EXTRACT_FMT_TRAP_CODE + EXTRACT_IFMT_TRAP_CODE /* Record the fields for the semantic handler. */ FLD (f_uimm4) = f_uimm4; @@ -2265,21 +2266,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_unlock.f - EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_UNLOCK_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ - FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src1) = & CPU (h_gr)[f_r1]; - TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0)); + FLD (i_src2) = & CPU (h_gr)[f_r2]; + TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); #if WITH_PROFILE_MODEL_P /* Record the fields for profiling. */ if (PROFILE_MODEL_P (current_cpu)) { - FLD (in_src2) = f_r2; FLD (in_src1) = f_r1; + FLD (in_src2) = f_r2; } #endif #undef FLD @@ -2290,9 +2291,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_satb.f - EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_SATB_CODE + EXTRACT_IFMT_SATB_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -2315,9 +2316,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sat.f - EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ + EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */ - EXTRACT_FMT_SAT_CODE + EXTRACT_IFMT_SATB_CODE /* Record the fields for the semantic handler. */ FLD (i_sr) = & CPU (h_gr)[f_r2]; @@ -2340,9 +2341,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_sadd.f - EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_SADD_CODE + EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sadd", (char *) 0)); @@ -2355,9 +2356,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_macwu1.f - EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MACWU1_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; @@ -2380,9 +2381,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_msblo.f - EXTRACT_FMT_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MSBLO_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; @@ -2405,9 +2406,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.fmt_mulwu1.f - EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_MULWU1_CODE + EXTRACT_IFMT_CMP_CODE /* Record the fields for the semantic handler. */ FLD (i_src1) = & CPU (h_gr)[f_r1]; @@ -2430,9 +2431,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc, { CGEN_INSN_INT insn = entire_insn; #define FLD(f) abuf->fields.cti.fields.fmt_sc.f - EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */ + EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */ - EXTRACT_FMT_SC_CODE + EXTRACT_IFMT_NOP_CODE /* Record the fields for the semantic handler. */ SEM_BRANCH_INIT_EXTRACT (abuf); diff --git a/sim/m32r/modelx.c b/sim/m32r/modelx.c index 5eb3601..7ff4ad1 100644 --- a/sim/m32r/modelx.c +++ b/sim/m32r/modelx.c @@ -44,14 +44,16 @@ model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -67,14 +69,14 @@ model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -90,14 +92,16 @@ model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -113,14 +117,14 @@ model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -136,14 +140,16 @@ model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -159,14 +165,14 @@ model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -182,14 +188,16 @@ model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -205,14 +213,14 @@ model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -228,14 +236,14 @@ model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); - sr = FLD (in_dr); - referenced |= 1 << 0; + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -251,14 +259,16 @@ model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -274,14 +284,14 @@ model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -297,14 +307,16 @@ model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -320,9 +332,9 @@ model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -338,9 +350,9 @@ model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -356,20 +368,20 @@ model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 3)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -385,18 +397,18 @@ model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -412,18 +424,18 @@ model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -439,18 +451,18 @@ model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -466,18 +478,18 @@ model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -493,18 +505,18 @@ model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -520,18 +532,18 @@ model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -547,9 +559,9 @@ model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -565,9 +577,9 @@ model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -583,9 +595,9 @@ model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 4)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -601,9 +613,9 @@ model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 4)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -619,9 +631,9 @@ model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -637,9 +649,9 @@ model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -655,20 +667,20 @@ model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 3)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -684,9 +696,9 @@ model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -702,9 +714,9 @@ model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -720,9 +732,9 @@ model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 4)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -738,9 +750,9 @@ model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; + INT in_sr = -1; if (insn_referenced & (1 << 4)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -756,13 +768,13 @@ model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -778,11 +790,11 @@ model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -798,13 +810,13 @@ model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -820,11 +832,11 @@ model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -840,13 +852,13 @@ model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -862,11 +874,11 @@ model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -882,14 +894,16 @@ model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; if (insn_referenced & (1 << 2)) referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -905,14 +919,16 @@ model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; if (insn_referenced & (1 << 2)) referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -928,14 +944,16 @@ model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; if (insn_referenced & (1 << 2)) referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -951,14 +969,16 @@ model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; if (insn_referenced & (1 << 2)) referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -974,14 +994,16 @@ model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + if (insn_referenced & (1 << 0)) referenced |= 1 << 1; if (insn_referenced & (1 << 2)) referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -997,11 +1019,11 @@ model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - sr = FLD (in_sr); + INT in_sr = -1; + in_sr = FLD (in_sr); if (insn_referenced & (1 << 1)) referenced |= 1 << 0; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -1017,11 +1039,11 @@ model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - sr = FLD (in_sr); + INT in_sr = -1; + in_sr = FLD (in_sr); if (insn_referenced & (1 << 1)) referenced |= 1 << 0; if (insn_referenced & (1 << 2)) referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -1037,11 +1059,11 @@ model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - sr = FLD (in_sr); + INT in_sr = -1; + in_sr = FLD (in_sr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -1057,11 +1079,11 @@ model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - sr = FLD (in_sr); + INT in_sr = -1; + in_sr = FLD (in_sr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, sr); + cycles += m32rxf_model_m32rx_u_cti (current_cpu, idesc, 0, referenced, in_sr); } return cycles; #undef FLD @@ -1077,13 +1099,13 @@ model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1099,13 +1121,13 @@ model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1121,13 +1143,13 @@ model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1143,13 +1165,13 @@ model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1165,13 +1187,13 @@ model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1187,13 +1209,13 @@ model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1209,13 +1231,13 @@ model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1231,13 +1253,13 @@ model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1253,13 +1275,13 @@ model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1275,13 +1297,13 @@ model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1297,25 +1319,25 @@ model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_sr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_sr); + out_dr = FLD (out_sr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1331,12 +1353,12 @@ model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1352,12 +1374,12 @@ model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1373,12 +1395,12 @@ model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1394,13 +1416,13 @@ model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = 0; + INT out_dr = 0; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -1416,13 +1438,13 @@ model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1438,13 +1460,13 @@ model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1460,13 +1482,13 @@ model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1482,13 +1504,13 @@ model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1504,14 +1526,16 @@ model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1527,13 +1551,13 @@ model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1549,13 +1573,13 @@ model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1571,13 +1595,13 @@ model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1593,13 +1617,13 @@ model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1615,14 +1639,14 @@ model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1638,12 +1662,12 @@ model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1659,12 +1683,12 @@ model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1680,12 +1704,12 @@ model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1701,12 +1725,12 @@ model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1722,12 +1746,11 @@ model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_src1); - referenced |= 1 << 0; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_src1); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1743,12 +1766,11 @@ model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_src1); - referenced |= 1 << 0; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_src1); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1764,12 +1786,12 @@ model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); referenced |= 1 << 0; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1785,14 +1807,14 @@ model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1808,10 +1830,10 @@ model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1827,14 +1849,14 @@ model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1850,9 +1872,9 @@ model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1868,9 +1890,9 @@ model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -1886,10 +1908,10 @@ model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1905,12 +1927,12 @@ model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + out_dr = FLD (out_dr); referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1926,14 +1948,16 @@ model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1949,14 +1973,14 @@ model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1972,12 +1996,14 @@ model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -1993,14 +2019,16 @@ model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2016,14 +2044,14 @@ model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2039,12 +2067,14 @@ model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2060,14 +2090,16 @@ model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2083,14 +2115,14 @@ model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2106,12 +2138,14 @@ model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2127,13 +2161,13 @@ model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2149,13 +2183,13 @@ model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2171,13 +2205,13 @@ model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2193,13 +2227,13 @@ model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2215,13 +2249,13 @@ model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2237,13 +2271,13 @@ model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2259,25 +2293,23 @@ model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_src2); - sr = FLD (in_src2); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2293,25 +2325,23 @@ model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = 0; - INT src2 = 0; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = 0; + INT in_src2 = 0; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); } { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - dr = FLD (out_src2); - sr = FLD (in_src2); - referenced |= 1 << 0; - referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_dr = FLD (in_src2); + out_dr = FLD (out_src2); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2327,14 +2357,16 @@ model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2350,14 +2382,16 @@ model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2373,14 +2407,16 @@ model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + in_dr = FLD (in_dr); + out_dr = FLD (out_dr); referenced |= 1 << 0; + referenced |= 1 << 1; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2396,10 +2432,10 @@ model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2415,9 +2451,9 @@ model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = 0; - INT dr = 0; - cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, sr, dr); + INT in_sr = 0; + INT out_dr = 0; + cycles += m32rxf_model_m32rx_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); } return cycles; #undef FLD @@ -2433,14 +2469,14 @@ model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2456,14 +2492,14 @@ model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2479,14 +2515,14 @@ model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - sr = FLD (in_sr); - dr = FLD (out_dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + in_sr = FLD (in_sr); + out_dr = FLD (out_dr); if (insn_referenced & (1 << 1)) referenced |= 1 << 0; referenced |= 1 << 2; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2502,11 +2538,11 @@ model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src2 = FLD (in_src2); referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2522,9 +2558,9 @@ model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + INT in_src1 = -1; + INT in_src2 = -1; + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2540,13 +2576,13 @@ model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2562,13 +2598,13 @@ model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2584,13 +2620,13 @@ model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2606,13 +2642,13 @@ model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT src1 = -1; - INT src2 = -1; - src1 = FLD (in_src1); - src2 = FLD (in_src2); + INT in_src1 = -1; + INT in_src2 = -1; + in_src1 = FLD (in_src1); + in_src2 = FLD (in_src2); referenced |= 1 << 0; referenced |= 1 << 1; - cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, src1, src2); + cycles += m32rxf_model_m32rx_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); } return cycles; #undef FLD @@ -2628,10 +2664,10 @@ model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD @@ -2647,10 +2683,10 @@ model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg) { int referenced = 0; int UNUSED insn_referenced = abuf->written; - INT sr = -1; - INT sr2 = -1; - INT dr = -1; - cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, sr, sr2, dr); + INT in_sr = -1; + INT in_dr = -1; + INT out_dr = -1; + cycles += m32rxf_model_m32rx_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); } return cycles; #undef FLD diff --git a/sim/m32r/semx-switch.c b/sim/m32r/semx-switch.c index 3299f6d..ef3c490 100644 --- a/sim/m32r/semx-switch.c +++ b/sim/m32r/semx-switch.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. This file is part of the GNU Simulators. @@ -370,7 +370,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -393,7 +393,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -412,7 +412,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -431,7 +431,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -459,7 +459,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -481,7 +481,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_empty.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); { @@ -506,7 +506,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -525,7 +525,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -544,7 +544,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -563,7 +563,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_and3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -582,7 +582,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -601,7 +601,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_or3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -620,7 +620,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -639,7 +639,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_and3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -658,7 +658,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -677,7 +677,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -706,7 +706,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addv3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); do { @@ -735,7 +735,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addx.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -764,7 +764,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -789,7 +789,7 @@ if (CPU (h_cond)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -814,7 +814,7 @@ if (CPU (h_cond)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beq.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -839,7 +839,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -864,7 +864,7 @@ if (EQSI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -889,7 +889,7 @@ if (GESI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -914,7 +914,7 @@ if (GTSI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -939,7 +939,7 @@ if (LESI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -964,7 +964,7 @@ if (LTSI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -989,7 +989,7 @@ if (NESI (* FLD (i_src2), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1017,7 +1017,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1045,7 +1045,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1078,7 +1078,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1111,7 +1111,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1136,7 +1136,7 @@ if (NOTBI (CPU (h_cond))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1161,7 +1161,7 @@ if (NOTBI (CPU (h_cond))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_beq.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1186,7 +1186,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1207,7 +1207,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1228,7 +1228,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1261,7 +1261,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 4); @@ -1294,7 +1294,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1313,7 +1313,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmpi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1332,7 +1332,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1351,7 +1351,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmpi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1370,7 +1370,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1389,7 +1389,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmpz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1408,7 +1408,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_div.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); if (NESI (* FLD (i_sr), 0)) { @@ -1431,7 +1431,7 @@ if (NESI (* FLD (i_sr), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_div.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); if (NESI (* FLD (i_sr), 0)) { @@ -1454,7 +1454,7 @@ if (NESI (* FLD (i_sr), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_div.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); if (NESI (* FLD (i_sr), 0)) { @@ -1477,7 +1477,7 @@ if (NESI (* FLD (i_sr), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_div.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); if (NESI (* FLD (i_sr), 0)) { @@ -1500,7 +1500,7 @@ if (NESI (* FLD (i_sr), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_div.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); if (NESI (* FLD (i_sr), 0)) { @@ -1523,7 +1523,7 @@ if (NESI (* FLD (i_sr), 0)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_jc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1548,7 +1548,7 @@ if (CPU (h_cond)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_jc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1573,7 +1573,7 @@ if (NOTBI (CPU (h_cond))) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_jl.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1604,7 +1604,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -1625,7 +1625,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ld.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1644,7 +1644,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ld_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1663,7 +1663,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1682,7 +1682,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldb_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1701,7 +1701,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldh.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1720,7 +1720,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldh_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1739,7 +1739,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1758,7 +1758,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldb_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1777,7 +1777,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldh.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1796,7 +1796,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldh_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1815,7 +1815,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ld_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -1844,7 +1844,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ld24.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1863,7 +1863,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldi8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -1882,7 +1882,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_ldi16.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -1901,7 +1901,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_lock.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -1927,12 +1927,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -1946,12 +1946,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -1965,12 +1965,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -1984,12 +1984,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -2003,7 +2003,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2022,12 +2022,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { DI opval = SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))), 16), 16); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -2041,12 +2041,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { DI opval = SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 16), 16); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -2060,12 +2060,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16)))); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -2079,12 +2079,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { DI opval = MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), opval); + SET_H_ACCUMS (FLD (f_acc), opval); TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -2098,7 +2098,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2117,11 +2117,11 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 32)); + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -2136,11 +2136,11 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (m32rxf_h_accums_get (current_cpu, FLD (f_accs))); + SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -2155,11 +2155,11 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 16)); + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -2174,11 +2174,11 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvfc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = m32rxf_h_cr_get (current_cpu, FLD (f_r2)); + SI opval = GET_H_CR (FLD (f_r2)); * FLD (i_dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -2193,12 +2193,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvtachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); - m32rxf_h_accums_set (current_cpu, FLD (f_accs), opval); + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); + SET_H_ACCUMS (FLD (f_accs), opval); TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval); } @@ -2212,12 +2212,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvtachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); - m32rxf_h_accums_set (current_cpu, FLD (f_accs), opval); + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); + SET_H_ACCUMS (FLD (f_accs), opval); TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval); } @@ -2231,12 +2231,12 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mvtc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { USI opval = * FLD (i_sr); - m32rxf_h_cr_set (current_cpu, FLD (f_r1), opval); + SET_H_CR (FLD (f_r1), opval); TRACE_RESULT (current_cpu, abuf, "dcr", 'x', opval); } @@ -2250,7 +2250,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2269,7 +2269,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_nop.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); @@ -2284,7 +2284,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2303,16 +2303,16 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_rac_dsi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { DI tmp_tmp1; - tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); { DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); - m32rxf_h_accums_set (current_cpu, FLD (f_accd), opval); + SET_H_ACCUMS (FLD (f_accd), opval); TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval); } } while (0); @@ -2327,16 +2327,16 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_rac_dsi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { DI tmp_tmp1; - tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); { DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); - m32rxf_h_accums_set (current_cpu, FLD (f_accd), opval); + SET_H_ACCUMS (FLD (f_accd), opval); TRACE_RESULT (current_cpu, abuf, "accd", 'D', opval); } } while (0); @@ -2351,24 +2351,24 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_rte.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { { - USI opval = ANDSI (m32rxf_h_cr_get (current_cpu, ((UINT) 6)), -4); + USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } { - USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 14)); - m32rxf_h_cr_set (current_cpu, ((UINT) 6), opval); + USI opval = GET_H_CR (((UINT) 14)); + SET_H_CR (((UINT) 6), opval); TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval); } { UQI opval = CPU (h_bpsw); - m32rxf_h_psw_set (current_cpu, opval); + SET_H_PSW (opval); TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); } { @@ -2389,7 +2389,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_seth.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2408,7 +2408,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2427,7 +2427,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sll3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2446,7 +2446,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2465,7 +2465,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2484,7 +2484,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sll3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2503,7 +2503,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2522,7 +2522,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2541,7 +2541,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sll3.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2560,7 +2560,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2579,7 +2579,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_st.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2598,7 +2598,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_st_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2617,7 +2617,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_stb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2636,7 +2636,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_stb_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2655,7 +2655,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sth.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2674,7 +2674,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sth_d.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2693,7 +2693,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_st_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -2721,7 +2721,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_st_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -2749,7 +2749,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2768,7 +2768,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -2797,7 +2797,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_addx.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -2826,19 +2826,19 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_trap.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { { - USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 6)); - m32rxf_h_cr_set (current_cpu, ((UINT) 14), opval); + USI opval = GET_H_CR (((UINT) 6)); + SET_H_CR (((UINT) 14), opval); TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval); } { USI opval = ADDSI (pc, 4); - m32rxf_h_cr_set (current_cpu, ((UINT) 6), opval); + SET_H_CR (((UINT) 6), opval); TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval); } { @@ -2847,13 +2847,13 @@ do { TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval); } { - UQI opval = m32rxf_h_psw_get (current_cpu); + UQI opval = GET_H_PSW (); CPU (h_bpsw) = opval; TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); } { - UQI opval = ANDQI (m32rxf_h_psw_get (current_cpu), 128); - m32rxf_h_psw_set (current_cpu, opval); + UQI opval = ANDQI (GET_H_PSW (), 128); + SET_H_PSW (opval); TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); } { @@ -2874,7 +2874,7 @@ do { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_unlock.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -2882,7 +2882,7 @@ if (CPU (h_lock)) { { SI opval = * FLD (i_src1); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval); - written |= (1 << 3); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } @@ -2904,7 +2904,7 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_satb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2923,7 +2923,7 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_satb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2942,7 +2942,7 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sat.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { @@ -2961,7 +2961,7 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_cmpz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -2980,12 +2980,12 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_sadd.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (SRADI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), 16), m32rxf_h_accums_get (current_cpu, ((UINT) 0))); - m32rxf_h_accums_set (current_cpu, ((UINT) 0), opval); + DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); + SET_H_ACCUMS (((UINT) 0), opval); TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval); } @@ -2999,12 +2999,12 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_macwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); + SET_H_ACCUMS (((UINT) 1), opval); TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval); } @@ -3018,12 +3018,12 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_msblo.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (SUBDI (m32rxf_h_accum_get (current_cpu), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); - m32rxf_h_accum_set (current_cpu, opval); + DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); + SET_H_ACCUM (opval); TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } @@ -3037,12 +3037,12 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_mulwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { DI opval = SRADI (SLLDI (MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535))), 16), 16); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval); + SET_H_ACCUMS (((UINT) 1), opval); TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval); } @@ -3056,12 +3056,12 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.fmt_macwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), opval); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); + SET_H_ACCUMS (((UINT) 1), opval); TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval); } @@ -3075,7 +3075,7 @@ if (CPU (h_lock)) { ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_sc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3094,7 +3094,7 @@ SEM_SKIP_INSN (current_cpu, 1); ARGBUF *abuf = SEM_ARGBUF (sem_arg); #define FLD(f) abuf->fields.cti.fields.fmt_sc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 2); @@ -3114,7 +3114,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3135,7 +3135,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -3152,7 +3152,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3173,7 +3173,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -3190,7 +3190,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3211,7 +3211,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -3228,7 +3228,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3249,7 +3249,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -3266,7 +3266,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_addi.f #define OPRND(f) par_exec->operands.fmt_addi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3287,7 +3287,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_addi.f #define OPRND(f) par_exec->operands.fmt_addi.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -3304,7 +3304,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.fmt_addv.f #define OPRND(f) par_exec->operands.fmt_addv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -3335,11 +3335,11 @@ do { #define FLD(f) abuf->fields.fmt_addv.f #define OPRND(f) par_exec->operands.fmt_addv.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - * FLD (i_dr) = OPRND (dr); CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); #undef OPRND #undef FLD @@ -3353,7 +3353,7 @@ do { #define FLD(f) abuf->fields.fmt_addx.f #define OPRND(f) par_exec->operands.fmt_addx.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -3384,11 +3384,11 @@ do { #define FLD(f) abuf->fields.fmt_addx.f #define OPRND(f) par_exec->operands.fmt_addx.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - * FLD (i_dr) = OPRND (dr); CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); #undef OPRND #undef FLD @@ -3402,7 +3402,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f #define OPRND(f) par_exec->operands.fmt_bc8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (CPU (h_cond)) { @@ -3427,7 +3427,7 @@ if (CPU (h_cond)) { #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f #define OPRND(f) par_exec->operands.fmt_bc8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3449,7 +3449,7 @@ if (CPU (h_cond)) { #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f #define OPRND(f) par_exec->operands.fmt_bl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -3477,7 +3477,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f #define OPRND(f) par_exec->operands.fmt_bl8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3497,7 +3497,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f #define OPRND(f) par_exec->operands.fmt_bcl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (CPU (h_cond)) { @@ -3530,7 +3530,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f #define OPRND(f) par_exec->operands.fmt_bcl8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3556,7 +3556,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f #define OPRND(f) par_exec->operands.fmt_bc8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (CPU (h_cond))) { @@ -3581,7 +3581,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f #define OPRND(f) par_exec->operands.fmt_bc8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3603,7 +3603,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f #define OPRND(f) par_exec->operands.fmt_bra8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3624,7 +3624,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f #define OPRND(f) par_exec->operands.fmt_bra8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3643,7 +3643,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f #define OPRND(f) par_exec->operands.fmt_bcl8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (CPU (h_cond))) { @@ -3676,7 +3676,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f #define OPRND(f) par_exec->operands.fmt_bcl8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3702,7 +3702,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3723,7 +3723,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); CPU (h_cond) = OPRND (condbit); @@ -3740,7 +3740,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3761,7 +3761,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); CPU (h_cond) = OPRND (condbit); @@ -3778,7 +3778,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3799,7 +3799,7 @@ do { #define FLD(f) abuf->fields.fmt_cmp.f #define OPRND(f) par_exec->operands.fmt_cmp.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); CPU (h_cond) = OPRND (condbit); @@ -3816,7 +3816,7 @@ do { #define FLD(f) abuf->fields.fmt_cmpz.f #define OPRND(f) par_exec->operands.fmt_cmpz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -3837,7 +3837,7 @@ do { #define FLD(f) abuf->fields.fmt_cmpz.f #define OPRND(f) par_exec->operands.fmt_cmpz.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); CPU (h_cond) = OPRND (condbit); @@ -3854,7 +3854,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_jc.f #define OPRND(f) par_exec->operands.fmt_jc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (CPU (h_cond)) { @@ -3879,7 +3879,7 @@ if (CPU (h_cond)) { #define FLD(f) abuf->fields.cti.fields.fmt_jc.f #define OPRND(f) par_exec->operands.fmt_jc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3901,7 +3901,7 @@ if (CPU (h_cond)) { #define FLD(f) abuf->fields.cti.fields.fmt_jc.f #define OPRND(f) par_exec->operands.fmt_jc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (CPU (h_cond))) { @@ -3926,7 +3926,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_jc.f #define OPRND(f) par_exec->operands.fmt_jc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3948,7 +3948,7 @@ if (NOTBI (CPU (h_cond))) { #define FLD(f) abuf->fields.cti.fields.fmt_jl.f #define OPRND(f) par_exec->operands.fmt_jl.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -3979,7 +3979,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_jl.f #define OPRND(f) par_exec->operands.fmt_jl.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -3999,7 +3999,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f #define OPRND(f) par_exec->operands.fmt_jmp.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4020,7 +4020,7 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f #define OPRND(f) par_exec->operands.fmt_jmp.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -4039,7 +4039,7 @@ do { #define FLD(f) abuf->fields.fmt_ld.f #define OPRND(f) par_exec->operands.fmt_ld.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4060,7 +4060,7 @@ do { #define FLD(f) abuf->fields.fmt_ld.f #define OPRND(f) par_exec->operands.fmt_ld.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4077,7 +4077,7 @@ do { #define FLD(f) abuf->fields.fmt_ldb.f #define OPRND(f) par_exec->operands.fmt_ldb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4098,7 +4098,7 @@ do { #define FLD(f) abuf->fields.fmt_ldb.f #define OPRND(f) par_exec->operands.fmt_ldb.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4115,7 +4115,7 @@ do { #define FLD(f) abuf->fields.fmt_ldh.f #define OPRND(f) par_exec->operands.fmt_ldh.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4136,7 +4136,7 @@ do { #define FLD(f) abuf->fields.fmt_ldh.f #define OPRND(f) par_exec->operands.fmt_ldh.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4153,7 +4153,7 @@ do { #define FLD(f) abuf->fields.fmt_ldb.f #define OPRND(f) par_exec->operands.fmt_ldb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4174,7 +4174,7 @@ do { #define FLD(f) abuf->fields.fmt_ldb.f #define OPRND(f) par_exec->operands.fmt_ldb.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4191,7 +4191,7 @@ do { #define FLD(f) abuf->fields.fmt_ldh.f #define OPRND(f) par_exec->operands.fmt_ldh.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4212,7 +4212,7 @@ do { #define FLD(f) abuf->fields.fmt_ldh.f #define OPRND(f) par_exec->operands.fmt_ldh.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4229,7 +4229,7 @@ do { #define FLD(f) abuf->fields.fmt_ld_plus.f #define OPRND(f) par_exec->operands.fmt_ld_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -4260,7 +4260,7 @@ do { #define FLD(f) abuf->fields.fmt_ld_plus.f #define OPRND(f) par_exec->operands.fmt_ld_plus.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4278,7 +4278,7 @@ do { #define FLD(f) abuf->fields.fmt_ldi8.f #define OPRND(f) par_exec->operands.fmt_ldi8.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4299,7 +4299,7 @@ do { #define FLD(f) abuf->fields.fmt_ldi8.f #define OPRND(f) par_exec->operands.fmt_ldi8.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4316,7 +4316,7 @@ do { #define FLD(f) abuf->fields.fmt_lock.f #define OPRND(f) par_exec->operands.fmt_lock.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -4344,11 +4344,11 @@ do { #define FLD(f) abuf->fields.fmt_lock.f #define OPRND(f) par_exec->operands.fmt_lock.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - CPU (h_lock) = OPRND (h_lock_0); * FLD (i_dr) = OPRND (dr); + CPU (h_lock) = OPRND (h_lock_0); #undef OPRND #undef FLD @@ -4362,11 +4362,11 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (ANDSI (* FLD (i_src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))), 8), 8); OPRND (acc) = opval; TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -4383,10 +4383,10 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4400,11 +4400,11 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (SLLSI (* FLD (i_src1), 16)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))), 8), 8); OPRND (acc) = opval; TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -4421,10 +4421,10 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4438,11 +4438,11 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (SRASI (* FLD (i_src2), 16))))); OPRND (acc) = opval; TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -4459,10 +4459,10 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4476,11 +4476,11 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (m32rxf_h_accums_get (current_cpu, FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); + DI opval = ADDDI (GET_H_ACCUMS (FLD (f_acc)), MULDI (EXTSIDI (* FLD (i_src1)), EXTHIDI (TRUNCSIHI (* FLD (i_src2))))); OPRND (acc) = opval; TRACE_RESULT (current_cpu, abuf, "acc", 'D', opval); } @@ -4497,10 +4497,10 @@ do { #define FLD(f) abuf->fields.fmt_machi_a.f #define OPRND(f) par_exec->operands.fmt_machi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4514,7 +4514,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4535,7 +4535,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4552,7 +4552,7 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4573,10 +4573,10 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4590,7 +4590,7 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4611,10 +4611,10 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4628,7 +4628,7 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4649,10 +4649,10 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4666,7 +4666,7 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4687,10 +4687,10 @@ do { #define FLD(f) abuf->fields.fmt_mulhi_a.f #define OPRND(f) par_exec->operands.fmt_mulhi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_acc), OPRND (acc)); + SET_H_ACCUMS (FLD (f_acc), OPRND (acc)); #undef OPRND #undef FLD @@ -4704,7 +4704,7 @@ do { #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4725,7 +4725,7 @@ do { #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4742,11 +4742,11 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 32)); + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 32)); OPRND (dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -4763,7 +4763,7 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4780,11 +4780,11 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (m32rxf_h_accums_get (current_cpu, FLD (f_accs))); + SI opval = TRUNCDISI (GET_H_ACCUMS (FLD (f_accs))); OPRND (dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -4801,7 +4801,7 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4818,11 +4818,11 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = TRUNCDISI (SRADI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), 16)); + SI opval = TRUNCDISI (SRADI (GET_H_ACCUMS (FLD (f_accs)), 16)); OPRND (dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -4839,7 +4839,7 @@ do { #define FLD(f) abuf->fields.fmt_mvfachi_a.f #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4856,11 +4856,11 @@ do { #define FLD(f) abuf->fields.fmt_mvfc.f #define OPRND(f) par_exec->operands.fmt_mvfc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - SI opval = m32rxf_h_cr_get (current_cpu, FLD (f_r2)); + SI opval = GET_H_CR (FLD (f_r2)); OPRND (dr) = opval; TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); } @@ -4877,7 +4877,7 @@ do { #define FLD(f) abuf->fields.fmt_mvfc.f #define OPRND(f) par_exec->operands.fmt_mvfc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -4894,11 +4894,11 @@ do { #define FLD(f) abuf->fields.fmt_mvtachi_a.f #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (* FLD (i_src1)), 32)); OPRND (accs) = opval; TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval); } @@ -4915,10 +4915,10 @@ do { #define FLD(f) abuf->fields.fmt_mvtachi_a.f #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_accs), OPRND (accs)); + SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); #undef OPRND #undef FLD @@ -4932,11 +4932,11 @@ do { #define FLD(f) abuf->fields.fmt_mvtachi_a.f #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ORDI (ANDDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); + DI opval = ORDI (ANDDI (GET_H_ACCUMS (FLD (f_accs)), MAKEDI (0xffffffff, 0)), ZEXTSIDI (* FLD (i_src1))); OPRND (accs) = opval; TRACE_RESULT (current_cpu, abuf, "accs", 'D', opval); } @@ -4953,10 +4953,10 @@ do { #define FLD(f) abuf->fields.fmt_mvtachi_a.f #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_accs), OPRND (accs)); + SET_H_ACCUMS (FLD (f_accs), OPRND (accs)); #undef OPRND #undef FLD @@ -4970,7 +4970,7 @@ do { #define FLD(f) abuf->fields.fmt_mvtc.f #define OPRND(f) par_exec->operands.fmt_mvtc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -4991,10 +4991,10 @@ do { #define FLD(f) abuf->fields.fmt_mvtc.f #define OPRND(f) par_exec->operands.fmt_mvtc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_cr_set (current_cpu, FLD (f_r1), OPRND (dcr)); + SET_H_CR (FLD (f_r1), OPRND (dcr)); #undef OPRND #undef FLD @@ -5008,7 +5008,7 @@ do { #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5029,7 +5029,7 @@ do { #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5046,7 +5046,7 @@ do { #define FLD(f) abuf->fields.fmt_nop.f #define OPRND(f) par_exec->operands.fmt_nop.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); @@ -5063,7 +5063,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); #define FLD(f) abuf->fields.fmt_nop.f #define OPRND(f) par_exec->operands.fmt_nop.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -5079,7 +5079,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5100,7 +5100,7 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); #define FLD(f) abuf->fields.fmt_mv.f #define OPRND(f) par_exec->operands.fmt_mv.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5117,12 +5117,12 @@ PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr); #define FLD(f) abuf->fields.fmt_rac_dsi.f #define OPRND(f) par_exec->operands.fmt_rac_dsi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { DI tmp_tmp1; - tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768)); { DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))); @@ -5143,10 +5143,10 @@ do { #define FLD(f) abuf->fields.fmt_rac_dsi.f #define OPRND(f) par_exec->operands.fmt_rac_dsi.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_accd), OPRND (accd)); + SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); #undef OPRND #undef FLD @@ -5160,12 +5160,12 @@ do { #define FLD(f) abuf->fields.fmt_rac_dsi.f #define OPRND(f) par_exec->operands.fmt_rac_dsi.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { DI tmp_tmp1; - tmp_tmp1 = SLLDI (m32rxf_h_accums_get (current_cpu, FLD (f_accs)), FLD (f_imm1)); + tmp_tmp1 = SLLDI (GET_H_ACCUMS (FLD (f_accs)), FLD (f_imm1)); tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000)); { DI opval = (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))); @@ -5186,10 +5186,10 @@ do { #define FLD(f) abuf->fields.fmt_rac_dsi.f #define OPRND(f) par_exec->operands.fmt_rac_dsi.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, FLD (f_accd), OPRND (accd)); + SET_H_ACCUMS (FLD (f_accd), OPRND (accd)); #undef OPRND #undef FLD @@ -5203,17 +5203,17 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_rte.f #define OPRND(f) par_exec->operands.fmt_rte.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { { - USI opval = ANDSI (m32rxf_h_cr_get (current_cpu, ((UINT) 6)), -4); + USI opval = ANDSI (GET_H_CR (((UINT) 6)), -4); OPRND (pc) = opval; TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); } { - USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 14)); + USI opval = GET_H_CR (((UINT) 14)); OPRND (h_cr_6) = opval; TRACE_RESULT (current_cpu, abuf, "cr-6", 'x', opval); } @@ -5241,14 +5241,14 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_rte.f #define OPRND(f) par_exec->operands.fmt_rte.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); - m32rxf_h_cr_set (current_cpu, ((UINT) 6), OPRND (h_cr_6)); - m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0)); CPU (h_bpsw) = OPRND (h_bpsw_0); + SET_H_CR (((UINT) 6), OPRND (h_cr_6)); + SET_H_PSW (OPRND (h_psw_0)); + SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_FINI (vpc); #undef OPRND @@ -5263,7 +5263,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5284,7 +5284,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5301,7 +5301,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5322,7 +5322,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5339,7 +5339,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5360,7 +5360,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5377,7 +5377,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5398,7 +5398,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5415,7 +5415,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5436,7 +5436,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5453,7 +5453,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5474,7 +5474,7 @@ do { #define FLD(f) abuf->fields.fmt_slli.f #define OPRND(f) par_exec->operands.fmt_slli.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5491,7 +5491,7 @@ do { #define FLD(f) abuf->fields.fmt_st.f #define OPRND(f) par_exec->operands.fmt_st.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5513,7 +5513,7 @@ do { #define FLD(f) abuf->fields.fmt_st.f #define OPRND(f) par_exec->operands.fmt_st.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); @@ -5530,7 +5530,7 @@ do { #define FLD(f) abuf->fields.fmt_stb.f #define OPRND(f) par_exec->operands.fmt_stb.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5552,7 +5552,7 @@ do { #define FLD(f) abuf->fields.fmt_stb.f #define OPRND(f) par_exec->operands.fmt_stb.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SETMEMQI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); @@ -5569,7 +5569,7 @@ do { #define FLD(f) abuf->fields.fmt_sth.f #define OPRND(f) par_exec->operands.fmt_sth.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5591,7 +5591,7 @@ do { #define FLD(f) abuf->fields.fmt_sth.f #define OPRND(f) par_exec->operands.fmt_sth.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SETMEMHI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); @@ -5608,7 +5608,7 @@ do { #define FLD(f) abuf->fields.fmt_st_plus.f #define OPRND(f) par_exec->operands.fmt_st_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -5639,7 +5639,7 @@ do { #define FLD(f) abuf->fields.fmt_st_plus.f #define OPRND(f) par_exec->operands.fmt_st_plus.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2)); @@ -5657,7 +5657,7 @@ do { #define FLD(f) abuf->fields.fmt_st_plus.f #define OPRND(f) par_exec->operands.fmt_st_plus.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -5688,7 +5688,7 @@ do { #define FLD(f) abuf->fields.fmt_st_plus.f #define OPRND(f) par_exec->operands.fmt_st_plus.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2)); @@ -5706,7 +5706,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5727,7 +5727,7 @@ do { #define FLD(f) abuf->fields.fmt_add.f #define OPRND(f) par_exec->operands.fmt_add.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); * FLD (i_dr) = OPRND (dr); @@ -5744,7 +5744,7 @@ do { #define FLD(f) abuf->fields.fmt_addv.f #define OPRND(f) par_exec->operands.fmt_addv.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -5775,11 +5775,11 @@ do { #define FLD(f) abuf->fields.fmt_addv.f #define OPRND(f) par_exec->operands.fmt_addv.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - * FLD (i_dr) = OPRND (dr); CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); #undef OPRND #undef FLD @@ -5793,7 +5793,7 @@ do { #define FLD(f) abuf->fields.fmt_addx.f #define OPRND(f) par_exec->operands.fmt_addx.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -5824,11 +5824,11 @@ do { #define FLD(f) abuf->fields.fmt_addx.f #define OPRND(f) par_exec->operands.fmt_addx.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - * FLD (i_dr) = OPRND (dr); CPU (h_cond) = OPRND (condbit); + * FLD (i_dr) = OPRND (dr); #undef OPRND #undef FLD @@ -5842,12 +5842,12 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_trap.f #define OPRND(f) par_exec->operands.fmt_trap.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { { - USI opval = m32rxf_h_cr_get (current_cpu, ((UINT) 6)); + USI opval = GET_H_CR (((UINT) 6)); OPRND (h_cr_14) = opval; TRACE_RESULT (current_cpu, abuf, "cr-14", 'x', opval); } @@ -5862,12 +5862,12 @@ do { TRACE_RESULT (current_cpu, abuf, "bbpsw-0", 'x', opval); } { - UQI opval = m32rxf_h_psw_get (current_cpu); + UQI opval = GET_H_PSW (); OPRND (h_bpsw_0) = opval; TRACE_RESULT (current_cpu, abuf, "bpsw-0", 'x', opval); } { - UQI opval = ANDQI (m32rxf_h_psw_get (current_cpu), 128); + UQI opval = ANDQI (GET_H_PSW (), 128); OPRND (h_psw_0) = opval; TRACE_RESULT (current_cpu, abuf, "psw-0", 'x', opval); } @@ -5890,15 +5890,15 @@ do { #define FLD(f) abuf->fields.cti.fields.fmt_trap.f #define OPRND(f) par_exec->operands.fmt_trap.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_cr_set (current_cpu, ((UINT) 14), OPRND (h_cr_14)); - m32rxf_h_cr_set (current_cpu, ((UINT) 6), OPRND (h_cr_6)); CPU (h_bbpsw) = OPRND (h_bbpsw_0); CPU (h_bpsw) = OPRND (h_bpsw_0); - m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0)); + SET_H_CR (((UINT) 14), OPRND (h_cr_14)); + SET_H_CR (((UINT) 6), OPRND (h_cr_6)); + SET_H_PSW (OPRND (h_psw_0)); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_FINI (vpc); @@ -5914,7 +5914,7 @@ do { #define FLD(f) abuf->fields.fmt_unlock.f #define OPRND(f) par_exec->operands.fmt_unlock.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); do { @@ -5923,7 +5923,7 @@ if (CPU (h_lock)) { SI opval = * FLD (i_src1); OPRND (h_memory_src2_idx) = * FLD (i_src2); OPRND (h_memory_src2) = opval; - written |= (1 << 3); + written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } @@ -5947,14 +5947,14 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_unlock.f #define OPRND(f) par_exec->operands.fmt_unlock.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - if (written & (1 << 3)) + CPU (h_lock) = OPRND (h_lock_0); + if (written & (1 << 4)) { SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); } - CPU (h_lock) = OPRND (h_lock_0); #undef OPRND #undef FLD @@ -5968,7 +5968,7 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_cmpz.f #define OPRND(f) par_exec->operands.fmt_cmpz.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -5989,7 +5989,7 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_cmpz.f #define OPRND(f) par_exec->operands.fmt_cmpz.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); CPU (h_cond) = OPRND (condbit); @@ -6006,11 +6006,11 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_sadd.f #define OPRND(f) par_exec->operands.fmt_sadd.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = ADDDI (SRADI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), 16), m32rxf_h_accums_get (current_cpu, ((UINT) 0))); + DI opval = ADDDI (SRADI (GET_H_ACCUMS (((UINT) 1)), 16), GET_H_ACCUMS (((UINT) 0))); OPRND (h_accums_0) = opval; TRACE_RESULT (current_cpu, abuf, "accums-0", 'D', opval); } @@ -6027,10 +6027,10 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_sadd.f #define OPRND(f) par_exec->operands.fmt_sadd.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, ((UINT) 0), OPRND (h_accums_0)); + SET_H_ACCUMS (((UINT) 0), OPRND (h_accums_0)); #undef OPRND #undef FLD @@ -6044,11 +6044,11 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_macwu1.f #define OPRND(f) par_exec->operands.fmt_macwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), MULDI (EXTSIDI (* FLD (i_src1)), EXTSIDI (ANDSI (* FLD (i_src2), 65535)))), 8), 8); OPRND (h_accums_1) = opval; TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval); } @@ -6065,10 +6065,10 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_macwu1.f #define OPRND(f) par_exec->operands.fmt_macwu1.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1)); + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1)); #undef OPRND #undef FLD @@ -6082,11 +6082,11 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_msblo.f #define OPRND(f) par_exec->operands.fmt_msblo.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (SUBDI (m32rxf_h_accum_get (current_cpu), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); + DI opval = SRADI (SLLDI (SUBDI (GET_H_ACCUM (), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (* FLD (i_src1))), EXTHIDI (TRUNCSIHI (* FLD (i_src2)))), 32), 16)), 8), 8); OPRND (accum) = opval; TRACE_RESULT (current_cpu, abuf, "accum", 'D', opval); } @@ -6103,10 +6103,10 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_msblo.f #define OPRND(f) par_exec->operands.fmt_msblo.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accum_set (current_cpu, OPRND (accum)); + SET_H_ACCUM (OPRND (accum)); #undef OPRND #undef FLD @@ -6120,7 +6120,7 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_mulwu1.f #define OPRND(f) par_exec->operands.fmt_mulwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { @@ -6141,10 +6141,10 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_mulwu1.f #define OPRND(f) par_exec->operands.fmt_mulwu1.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1)); + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1)); #undef OPRND #undef FLD @@ -6158,11 +6158,11 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_macwu1.f #define OPRND(f) par_exec->operands.fmt_macwu1.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); { - DI opval = SRADI (SLLDI (ADDDI (m32rxf_h_accums_get (current_cpu, ((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); + DI opval = SRADI (SLLDI (ADDDI (GET_H_ACCUMS (((UINT) 1)), SLLDI (EXTSIDI (MULSI (EXTHISI (TRUNCSIHI (* FLD (i_src1))), SRASI (* FLD (i_src2), 16))), 16)), 8), 8); OPRND (h_accums_1) = opval; TRACE_RESULT (current_cpu, abuf, "accums-1", 'D', opval); } @@ -6179,10 +6179,10 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.fmt_macwu1.f #define OPRND(f) par_exec->operands.fmt_macwu1.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 0); - m32rxf_h_accums_set (current_cpu, ((UINT) 1), OPRND (h_accums_1)); + SET_H_ACCUMS (((UINT) 1), OPRND (h_accums_1)); #undef OPRND #undef FLD @@ -6196,7 +6196,7 @@ if (CPU (h_lock)) { #define FLD(f) abuf->fields.cti.fields.fmt_sc.f #define OPRND(f) par_exec->operands.fmt_sc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (CPU (h_cond)) { @@ -6215,7 +6215,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.cti.fields.fmt_sc.f #define OPRND(f) par_exec->operands.fmt_sc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); @@ -6233,7 +6233,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.cti.fields.fmt_sc.f #define OPRND(f) par_exec->operands.fmt_sc.f int UNUSED written = 0; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 2); if (NOTBI (CPU (h_cond))) { @@ -6252,7 +6252,7 @@ SEM_SKIP_INSN (current_cpu, 1); #define FLD(f) abuf->fields.cti.fields.fmt_sc.f #define OPRND(f) par_exec->operands.fmt_sc.f int UNUSED written = abuf->written; - PCADDR UNUSED pc = abuf->addr; + IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT vpc = SEM_NEXT_VPC (sem_arg, pc, 0); |