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-rw-r--r--sim/iq2000/ChangeLog7
-rw-r--r--sim/iq2000/cpu.h6
-rw-r--r--sim/iq2000/cpuall.h2
-rw-r--r--sim/iq2000/decode.c56
-rw-r--r--sim/iq2000/decode.h2
5 files changed, 42 insertions, 31 deletions
diff --git a/sim/iq2000/ChangeLog b/sim/iq2000/ChangeLog
index e034ca3..999008f 100644
--- a/sim/iq2000/ChangeLog
+++ b/sim/iq2000/ChangeLog
@@ -1,3 +1,10 @@
+2009-11-22 Doug Evans <dje@sebabeach.org>
+
+ * cpu.h: Regenerate.
+ * cpuall.h: Regenerate.
+ * decode.c: Regenerate.
+ * decode.h: Regenerate.
+
2009-11-03 Doug Evans <dje@sebabeach.org>
* arch.c: Regenerate.
diff --git a/sim/iq2000/cpu.h b/sim/iq2000/cpu.h
index 47ca845..edc50c4 100644
--- a/sim/iq2000/cpu.h
+++ b/sim/iq2000/cpu.h
@@ -32,6 +32,12 @@ This file is part of the GNU simulators.
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
/* CPU state information. */
typedef struct {
/* Hardware elements. */
diff --git a/sim/iq2000/cpuall.h b/sim/iq2000/cpuall.h
index 51a7d9b..8bac559 100644
--- a/sim/iq2000/cpuall.h
+++ b/sim/iq2000/cpuall.h
@@ -29,14 +29,12 @@ This file is part of the GNU simulators.
#ifdef WANT_CPU_IQ2000BF
#include "eng.h"
-#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif
#ifdef WANT_CPU_IQ10BF
#include "eng.h"
-#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif
diff --git a/sim/iq2000/decode.c b/sim/iq2000/decode.c
index 1bb77b1..1d08454 100644
--- a/sim/iq2000/decode.c
+++ b/sim/iq2000/decode.c
@@ -256,14 +256,14 @@ iq2000bf_init_idesc_table (SIM_CPU *cpu)
const IDESC *
iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
- CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
IQ2000BF_INSN_TYPE itype;
{
- CGEN_INSN_INT insn = base_insn;
+ CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 26) & (63 << 0)));
@@ -892,7 +892,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@@ -915,7 +915,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -938,7 +938,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ram:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rs;
UINT f_rt;
@@ -967,7 +967,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sll:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rt;
UINT f_rd;
@@ -990,7 +990,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slmv:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_ram.f
UINT f_rs;
UINT f_rt;
@@ -1016,7 +1016,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slt:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@@ -1039,7 +1039,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_slti:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1062,7 +1062,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bbi:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
UINT f_rt;
@@ -1091,7 +1091,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bbv:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
UINT f_rt;
@@ -1120,7 +1120,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bgez:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
SI f_offset;
@@ -1146,7 +1146,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bgezal:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
SI f_offset;
@@ -1172,7 +1172,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jalr:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rd;
@@ -1198,7 +1198,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jr:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_bbi.f
UINT f_rs;
@@ -1221,7 +1221,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1244,7 +1244,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lh:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1267,7 +1267,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lui:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rt;
UINT f_imm;
@@ -1287,7 +1287,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1310,7 +1310,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1333,7 +1333,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sh:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1356,7 +1356,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1411,7 +1411,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andoui:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1434,7 +1434,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mrgb:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mrgb.f
UINT f_rs;
UINT f_rt;
@@ -1473,7 +1473,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ldw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1496,7 +1496,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_sdw:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_addi.f
UINT f_rs;
UINT f_rt;
@@ -1519,7 +1519,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_j:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_j.f
USI f_jtarg;
@@ -1542,7 +1542,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jal:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
- CGEN_INSN_INT insn = entire_insn;
+ CGEN_INSN_WORD insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_j.f
USI f_jtarg;
diff --git a/sim/iq2000/decode.h b/sim/iq2000/decode.h
index 75d647e..01f30d6 100644
--- a/sim/iq2000/decode.h
+++ b/sim/iq2000/decode.h
@@ -26,7 +26,7 @@ This file is part of the GNU simulators.
#define IQ2000BF_DECODE_H
extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR,
- CGEN_INSN_INT, CGEN_INSN_INT,
+ CGEN_INSN_WORD, CGEN_INSN_WORD,
ARGBUF *);
extern void iq2000bf_init_idesc_table (SIM_CPU *);
extern void iq2000bf_sem_init_idesc_table (SIM_CPU *);
generated by cgit v1.1 at 2024-11-24 19:25:04 +0000