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-rw-r--r--sim/frv/pipeline.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sim/frv/pipeline.c b/sim/frv/pipeline.c
index 291a5dc..780e127 100644
--- a/sim/frv/pipeline.c
+++ b/sim/frv/pipeline.c
@@ -61,7 +61,7 @@ frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
{
/* Clear the appropriate MSR fields depending on which slot
this insn is in. */
- CGEN_ATTR_VALUE_TYPE preserve_ovf;
+ CGEN_ATTR_VALUE_ENUM_TYPE preserve_ovf;
SI msr0 = GET_MSR (0);
preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);