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diff --git a/sim/erc32/README.erc32 b/sim/erc32/README.erc32 deleted file mode 100644 index f413599..0000000 --- a/sim/erc32/README.erc32 +++ /dev/null @@ -1,130 +0,0 @@ - -1. MEC and ERC32 emulation - -The file 'erc32.c' contains a model of the MEC, 512 K rom and 4 M ram. - -The following paragraphs outline the implemented MEC functions. - -1.1 UARTs - -The UARTs are connected to two pseudo-devices, /dev/ttypc and /dev/ttypd. -The following registers are implemeted: - -- UART A RX and TX register (0x01f800e0) -- UART B RX and TX register (0x01f800e4) -- UART status register (0x01f800e8) - -To speed up simulation, the UARTs operate at approximately 115200 baud. -The UARTs generate interrupt 4 and 5 after each received or transmitted -character. The error interrupt is generated if overflow occurs - other -errors cannot occure. - -1.2 Real-time clock and general pupose timer A - -The following registers are implemeted: - -- Real-time clock timer (0x01f80080, read-only) -- Real-time clock scaler program register (0x01f80084, write-only) -- Real-time clock counter program register (0x01f80080, write-only) - -- Genearl pupose timer (0x01f80088, read-only) -- Real-time clock scaler program register (0x01f8008c, write-only) -- General purpose timer counter prog. register (0x01f80088, write-only) - -- Timer control register (0x01f80098, write-only) - -1.3 Interrupt controller - -The interrupt controller is implemented as in the MEC specification with -the exception of the interrupt shape register. Since external interrupts -are not possible, the interrupt shape register is not implemented. The -only internal interrupts that are generated are the real-time clock, -the general purpose timer and UARTs. However, all 15 interrupts -can be tested via the interrupt force register. - -The following registers are implemeted: - -- Interrupt pending register (0x01f80048, read-only) -- Interrupt mask register (0x01f8004c, read-write) -- Interrupt clear register (0x01f80050, write-only) -- Interrupt force register (0x01f80054, read-write) - -1.4 Breakpoint and watchpoint register - -The breakpoint and watchpoint functions are implemented as in the MEC -specification. Traps are correctly generated, and the system fault status -register is updated accordingly. Implemeted registers are: - -- Debug control register (0x01f800c0, read-write) -- Breakpoint register (0x01f800c4, write-only) -- Watchpoint register (0x01f800c8, write-only) -- System fault status register (0x01f800a0, read-write) -- Firts failing address register (0x01f800a4, read-write) - - -1.5 Memory interface - -The following memory areas are valid for the ERC32 simulator: - -0x00000000 - 0x00080000 ROM (512 Kbyte, loaded at start-up) -0x02000000 - 0x02400000 RAM (4 Mbyte, initialised to 0x0) -0x01f80000 - 0x01f800ff MEC registers - -Access to unimplemented MEC registers or non-existing memory will result -in a memory exception trap. However, access to unimplemented MEC registers -in the area 0x01f80000 - 0x01f80100 will not cause a memory exception trap. -The written value will be stored in a register and can be read back. It -does however not affect the function in any way. - -The memory configuartion register is used to define available memory -in the system. The fields RSIZ and PSIZ are used to set RAM and ROM -size, the remaining fields are not used. NOTE: after reset, the MEC -is set to decode 4 Kbyte of ROM and 256 Kbyte of RAM. The memory -configuration register has to be updated to reflect the available memory. - -The waitstate configuration register is used to generate waitstates. -This register must also be updated with the correct configuration after -reset. - -The memory protection scheme is implemented - it is enabled through bit 3 -in the MEC control register. - -The following registers are implemeted: - -- MEC control register (bit 3 only) (0x01f80000, read-write) -- Memory control register (0x01f80010, read-write) -- Waitstate configuration register (0x01f80018, read-write) -- Memory access register 0 (0x01f80020, read-write) -- Memory access register 1 (0x01f80024, read-write) - -1.6 Watchdog - -The watchdog is implemented as in the specification. The input clock is -always the system clock regardsless of WDCS bit in mec configuration -register. - -The following registers are implemeted: - -- Watchdog program and acknowledge register (0x01f80060, write-only) -- Watchdog trap door set register (0x01f80064, write-only) - -1.7 Software reset register - -Implemented as in the specification (0x01f800004, write-only). - -1.8 Power-down mode - -The power-down register (0x01f800008) is implemented as in the specification. -However, if the simulator event queue is empty, power-down mode is not -entered since no interrupt would be generated to exit from the mode. A -Ctrl-C in the simulator window will exit the power-down mode. - -1.9 MEC control register - -The following bits are implemented in the MEC control register: - -Bit Name Function -0 PRD Power-down mode enable -1 SWR Soft reset enable -3 APR Access protection enable - |