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-rw-r--r--sim/d10v/ChangeLog1
-rw-r--r--sim/d10v/simops.c12
2 files changed, 9 insertions, 4 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index b1a9568..013b93d 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -3,6 +3,7 @@ Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_3A00): For "macu", perform multiply stage using 32
bit rather than 16 bit precision.
(OP_3C00): For "mulxu", store unsigned product in ACC.
+ (OP_3800): For "msbu", subtract unsigned product from ACC,
Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index e5a0825..64c8a33 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1518,14 +1518,18 @@ OP_1800 ()
void
OP_3800 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
- tmp = SEXT40( (tmp << 1) & MASK40);
+ tmp = (tmp << 1);
- State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
+ State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
trace_output (OP_ACCUM);
}