diff options
Diffstat (limited to 'sim/cris/semcrisv32f-switch.c')
| -rw-r--r-- | sim/cris/semcrisv32f-switch.c | 462 |
1 files changed, 119 insertions, 343 deletions
diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c index 106b718..65c1c0a 100644 --- a/sim/cris/semcrisv32f-switch.c +++ b/sim/cris/semcrisv32f-switch.c @@ -83,15 +83,11 @@ with this program; if not, write to the Free Software Foundation, Inc., { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 }, { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 }, { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P0, && case_sem_INSN_MOVE_C_SPRV32_P0 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P1, && case_sem_INSN_MOVE_C_SPRV32_P1 }, { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 }, { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P4, && case_sem_INSN_MOVE_C_SPRV32_P4 }, { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 }, { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 }, { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 }, - { CRISV32F_INSN_MOVE_C_SPRV32_P8, && case_sem_INSN_MOVE_C_SPRV32_P8 }, { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 }, { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 }, { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 }, @@ -3113,7 +3109,7 @@ cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special regi SI tmp_newval; tmp_prno = FLD (f_operand2); tmp_newval = GET_H_SR (FLD (f_operand2)); -if (EQSI (tmp_prno, 0)) { +if (EQSI (tmp_prno, 2)) { { SI tmp_oldregval; tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); @@ -3125,7 +3121,7 @@ if (EQSI (tmp_prno, 0)) { } } } - else if (EQSI (tmp_prno, 1)) { + else if (EQSI (tmp_prno, 3)) { { SI tmp_oldregval; tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); @@ -3137,43 +3133,31 @@ if (EQSI (tmp_prno, 0)) { } } } - else if (EQSI (tmp_prno, 2)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 5)) { { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 3)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 6)) { { - SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 4)) { -{ - SI tmp_oldregval; - tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); + else if (EQSI (tmp_prno, 7)) { { - SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); + SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } -} - else if (EQSI (tmp_prno, 5)) { + else if (EQSI (tmp_prno, 9)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3181,7 +3165,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 6)) { + else if (EQSI (tmp_prno, 10)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3189,7 +3173,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 7)) { + else if (EQSI (tmp_prno, 11)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3197,7 +3181,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 8)) { + else if (EQSI (tmp_prno, 12)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3205,7 +3189,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 9)) { + else if (EQSI (tmp_prno, 13)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3213,7 +3197,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 10)) { + else if (EQSI (tmp_prno, 14)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3221,7 +3205,7 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 11)) { + else if (EQSI (tmp_prno, 15)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3229,31 +3213,43 @@ if (EQSI (tmp_prno, 0)) { TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 12)) { + else if (EQSI (tmp_prno, 0)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 13)) { +} + else if (EQSI (tmp_prno, 1)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 14)) { +} + else if (EQSI (tmp_prno, 4)) { +{ + SI tmp_oldregval; + tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); { - SI opval = tmp_newval; + SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); SET_H_GR (FLD (f_operand1), opval); written |= (1 << 4); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } - else if (EQSI (tmp_prno, 15)) { +} + else if (EQSI (tmp_prno, 8)) { { SI opval = tmp_newval; SET_H_GR (FLD (f_operand1), opval); @@ -3296,7 +3292,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); SI tmp_rno; SI tmp_newval; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { +if (EQSI (tmp_rno, 2)) { tmp_newval = EXTQISI (({ SI tmp_addr; QI tmp_tmp_mem; BI tmp_postinc; @@ -3311,51 +3307,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 1)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 2)) { - tmp_newval = EXTQISI (({ SI tmp_addr; - QI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3377,29 +3329,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; })); -} - else if (EQSI (tmp_rno, 4)) { - tmp_newval = EXTHISI (({ SI tmp_addr; - HI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3421,7 +3351,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3443,7 +3373,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3465,29 +3395,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); - TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); - } -} -} -; tmp_tmp_mem; }); -} - else if (EQSI (tmp_rno, 8)) { - tmp_newval = ({ SI tmp_addr; - SI tmp_tmp_mem; - BI tmp_postinc; - tmp_postinc = FLD (f_memmode); -; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); -; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); -; if (NEBI (tmp_postinc, 0)) { -{ -if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); -} - { - SI opval = tmp_addr; - SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3509,7 +3417,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3531,7 +3439,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3553,7 +3461,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3575,7 +3483,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3597,7 +3505,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3619,7 +3527,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3641,7 +3549,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { { SI opval = tmp_addr; SET_H_GR (FLD (f_operand1), opval); - written |= (1 << 9); + written |= (1 << 8); TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); } } @@ -3675,77 +3583,11 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); } NEXT (vpc); - CASE (sem, INSN_MOVE_C_SPRV32_P0) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P1) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */ { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3778,40 +3620,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P4) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3844,7 +3653,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3877,7 +3686,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3910,40 +3719,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f - int UNUSED written = 0; - IADDR UNUSED pc = abuf->addr; - vpc = SEM_NEXT_VPC (sem_arg, pc, 6); - -{ - { - SI opval = FLD (f_indir_pc__dword); - SET_H_SR (FLD (f_operand2), opval); - TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); - } -{ - { - BI opval = 0; - CPU (h_xbit) = opval; - TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); - } - { - BI opval = 0; - SET_H_INSN_PREFIXED_P (opval); - TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); - } -} -} - -#undef FLD -} - NEXT (vpc); - - CASE (sem, INSN_MOVE_C_SPRV32_P8) : /* move ${const32},${Pd} */ -{ - SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); - ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -3976,7 +3752,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4009,7 +3785,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4042,7 +3818,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4075,7 +3851,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4108,7 +3884,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4141,7 +3917,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4174,7 +3950,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; vpc = SEM_NEXT_VPC (sem_arg, pc, 6); @@ -4215,7 +3991,7 @@ cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); { SI tmp_rno; tmp_rno = FLD (f_operand2); -if (EQSI (tmp_rno, 0)) { +if (EQSI (tmp_rno, 2)) { { SI tmp_addr; BI tmp_postinc; @@ -4268,7 +4044,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 1)) { + else if (EQSI (tmp_rno, 3)) { { SI tmp_addr; BI tmp_postinc; @@ -4321,7 +4097,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 2)) { + else if (EQSI (tmp_rno, 5)) { { SI tmp_addr; BI tmp_postinc; @@ -4331,9 +4107,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4353,16 +4129,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4374,7 +4150,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 3)) { + else if (EQSI (tmp_rno, 6)) { { SI tmp_addr; BI tmp_postinc; @@ -4384,9 +4160,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4406,16 +4182,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - QI opval = GET_H_SR (FLD (f_operand2)); - SETMEMQI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 12); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 1); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4427,7 +4203,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 4)) { + else if (EQSI (tmp_rno, 7)) { { SI tmp_addr; BI tmp_postinc; @@ -4437,9 +4213,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4459,16 +4235,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - HI opval = GET_H_SR (FLD (f_operand2)); - SETMEMHI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 11); + SI opval = GET_H_SR (FLD (f_operand2)); + SETMEMSI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 13); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 2); + tmp_addr = ADDSI (tmp_addr, 4); } { SI opval = tmp_addr; @@ -4480,7 +4256,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 5)) { + else if (EQSI (tmp_rno, 9)) { { SI tmp_addr; BI tmp_postinc; @@ -4533,7 +4309,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 6)) { + else if (EQSI (tmp_rno, 10)) { { SI tmp_addr; BI tmp_postinc; @@ -4586,7 +4362,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 7)) { + else if (EQSI (tmp_rno, 11)) { { SI tmp_addr; BI tmp_postinc; @@ -4639,7 +4415,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 8)) { + else if (EQSI (tmp_rno, 12)) { { SI tmp_addr; BI tmp_postinc; @@ -4692,7 +4468,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 9)) { + else if (EQSI (tmp_rno, 13)) { { SI tmp_addr; BI tmp_postinc; @@ -4745,7 +4521,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 10)) { + else if (EQSI (tmp_rno, 14)) { { SI tmp_addr; BI tmp_postinc; @@ -4798,7 +4574,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 11)) { + else if (EQSI (tmp_rno, 15)) { { SI tmp_addr; BI tmp_postinc; @@ -4851,7 +4627,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 12)) { + else if (EQSI (tmp_rno, 0)) { { SI tmp_addr; BI tmp_postinc; @@ -4861,9 +4637,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4883,16 +4659,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4904,7 +4680,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 13)) { + else if (EQSI (tmp_rno, 1)) { { SI tmp_addr; BI tmp_postinc; @@ -4914,9 +4690,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4936,16 +4712,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + QI opval = GET_H_SR (FLD (f_operand2)); + SETMEMQI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 12); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 1); } { SI opval = tmp_addr; @@ -4957,7 +4733,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 14)) { + else if (EQSI (tmp_rno, 4)) { { SI tmp_addr; BI tmp_postinc; @@ -4967,9 +4743,9 @@ if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { if (EQBI (CPU (h_pbit), 0)) { { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } { @@ -4989,16 +4765,16 @@ if (EQBI (CPU (h_pbit), 0)) { } } else { { - SI opval = GET_H_SR (FLD (f_operand2)); - SETMEMSI (current_cpu, pc, tmp_addr, opval); - written |= (1 << 13); + HI opval = GET_H_SR (FLD (f_operand2)); + SETMEMHI (current_cpu, pc, tmp_addr, opval); + written |= (1 << 11); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } } if (NEBI (tmp_postinc, 0)) { { if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { - tmp_addr = ADDSI (tmp_addr, 4); + tmp_addr = ADDSI (tmp_addr, 2); } { SI opval = tmp_addr; @@ -5010,7 +4786,7 @@ if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { } } } - else if (EQSI (tmp_rno, 15)) { + else if (EQSI (tmp_rno, 8)) { { SI tmp_addr; BI tmp_postinc; @@ -12986,7 +12762,7 @@ cris_flush_simulator_decode_cache (current_cpu, pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT @@ -13155,7 +12931,7 @@ cris_flush_simulator_decode_cache (current_cpu, pc); { SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); ARGBUF *abuf = SEM_ARGBUF (sem_arg); -#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f +#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_BRANCH_INIT |