diff options
Diffstat (limited to 'sim/arm')
| -rw-r--r-- | sim/arm/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/arm/thumbemu.c | 7 |
2 files changed, 8 insertions, 5 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index b6d8266..9739fe1 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,9 @@ +2002-05-23 Nick Clifton <nickc@cambridge.redhat.com> + + * thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1) + instruction do not add in the second bit of the base address - + this has already been accounted for. + 2002-05-21 Nick Clifton <nickc@cambridge.redhat.com> * armcopro.c (check_cp13_access): Allow access to register 1 when diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c index 4f00733..283e7d5 100644 --- a/sim/arm/thumbemu.c +++ b/sim/arm/thumbemu.c @@ -520,12 +520,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr) { ARMword tmp = (pc + 2); - /* Bit one of the destination address comes from bit one of the - address of the first (H == 10) half of the instruction, not - from the offset in the instruction. */ state->Reg[15] = ((state->Reg[14] - + ((tinstr & 0x07FE) << 1) - + ((pc - 2) & 2)) + + ((tinstr & 0x07FE) << 1)) & 0xFFFFFFFC); CLEART; state->Reg[14] = (tmp | 1); @@ -538,6 +534,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr) break; } /* else we fall through to process the second half of the BL */ + pc += 2; /* point the pc at the 2nd half */ case 31: /* BL instruction 2 */ /* Format 19 */ /* There is no single ARM instruction equivalent for this |