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-rw-r--r--sim/arm/wrapper.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index c2fd8be..e00c21b 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -234,14 +234,18 @@ sim_create_inferior (sd, abfd, argv, env)
break;
case bfd_mach_arm_5:
- /* This is a special case in order to support COFF based ARM toolchains.
- The COFF header does not have enough room to store all the different
- kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
- to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
- machine type here, we assume it could be any of the above architectures
- and so select the most feature-full. */
- ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
- break;
+ if (bfd_family_coff (abfd))
+ {
+ /* This is a special case in order to support COFF based ARM toolchains.
+ The COFF header does not have enough room to store all the different
+ kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
+ to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
+ machine type here, we assume it could be any of the above architectures
+ and so select the most feature-full. */
+ ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
+ break;
+ }
+ /* Otherwise drop through. */
case bfd_mach_arm_5T:
ARMul_SelectProcessor (state, ARM_v5_Prop);