diff options
Diffstat (limited to 'sim/arm/armos.c')
| -rw-r--r-- | sim/arm/armos.c | 49 |
1 files changed, 39 insertions, 10 deletions
diff --git a/sim/arm/armos.c b/sim/arm/armos.c index 04916d6..613d07e 100644 --- a/sim/arm/armos.c +++ b/sim/arm/armos.c @@ -131,8 +131,11 @@ unsigned int swi_mask = -1; static ARMword softvectorcode[] = { - /* Basic: swi tidyexception + event; mov pc, lr; - ldmia r11,{r11,pc}; swi generateexception + event. */ + /* Installed instructions: + swi tidyexception + event; + mov lr, pc; + ldmia fp, {fp, pc}; + swi generateexception + event. */ 0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */ 0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */ 0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */ @@ -205,11 +208,15 @@ ARMul_OSInit (ARMul_State * state) /* Copy the code. */ ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]); + /* Scan backwards from the end of the code. */ for (i = FPESTART + fpesize;; i -= 4) { - /* Reverse the error strings. */ + /* When we reach the marker value, break out of + the loop, leaving i pointing at the maker. */ if ((j = ARMul_ReadWord (state, i)) == 0xffffffff) break; + + /* If necessary, reverse the error strings. */ if (state->bigendSig && j < 0x80000000) { /* It's part of the string so swap it. */ @@ -221,9 +228,9 @@ ARMul_OSInit (ARMul_State * state) } /* Copy old illegal instr vector. */ - ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, 4)); + ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV)); /* Install new vector. */ - ARMul_WriteWord (state, 4, FPENEWVECT (ARMul_ReadWord (state, i - 4))); + ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4))); ARMul_ConsolePrint (state, ", FPE"); /* #endif ASIM */ @@ -692,12 +699,34 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number) unhandled = TRUE; break; - case 0x90: - case 0x91: - case 0x92: - /* These are used by the FPE code. */ + /* The following SWIs are generated by the softvectorcode[] + installed by default by the simulator. */ + case 0x91: /* Undefined Instruction. */ + { + ARMword addr = state->RegBank[UNDEFBANK][14] - 4; + + sim_callback->printf_filtered + (sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n", + ARMul_ReadWord (state, addr), addr); + state->EndCondition = RDIError_SoftwareInterrupt; + state->Emulate = FALSE; + return FALSE; + } + + case 0x90: /* Reset. */ + case 0x92: /* SWI. */ + /* These two can be safely ignored. */ break; - + + case 0x93: /* Prefetch Abort. */ + case 0x94: /* Data Abort. */ + case 0x95: /* Address Exception. */ + case 0x96: /* IRQ. */ + case 0x97: /* FIQ. */ + case 0x98: /* Error. */ + unhandled = TRUE; + break; + case -1: /* This can happen when a SWI is interrupted (eg receiving a ctrl-C whilst processing SWIRead()). The SWI will complete |