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-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/i386-dis.c66
2 files changed, 56 insertions, 17 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7b57e5b..6713f2d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,12 @@
2005-05-25 Jan Beulich <jbeulich@novell.com>
+ * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
+ hex (but retain it being displayed as signed). Remove redundant
+ checks. Add handling of displacements for 16-bit addressing in Intel
+ mode.
+
+2005-05-25 Jan Beulich <jbeulich@novell.com>
+
* i386-dis.c (prefix_name): Remove pointless mode_64bit check.
(OP_E): Remove redundant REX_EXTZ handling. Remove pointless
masking of 'rm' in 16-bit memory address handling.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 9a8b73f..16c80b6 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3337,22 +3337,23 @@ OP_E (int bytemode, int sizeflag)
oappend (scratchbuf);
}
}
- if (intel_syntax)
- if (mod != 0 || (base & 7) == 5)
- {
- /* Don't print zero displacements. */
- if (disp != 0)
- {
- if ((bfd_signed_vma) disp > 0)
- {
- *obufp++ = '+';
- *obufp = '\0';
- }
-
- print_operand_value (scratchbuf, 0, disp);
- oappend (scratchbuf);
- }
- }
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
*obufp++ = close_char;
*obufp = '\0';
@@ -3410,10 +3411,41 @@ OP_E (int bytemode, int sizeflag)
{
*obufp++ = open_char;
*obufp = '\0';
- oappend (index16[rm + add]);
+ oappend (index16[rm]);
+ if (intel_syntax && disp)
+ {
+ if ((bfd_signed_vma) disp > 0)
+ {
+ *obufp++ = '+';
+ *obufp = '\0';
+ }
+ else if (mod != 1)
+ {
+ *obufp++ = '-';
+ *obufp = '\0';
+ disp = - (bfd_signed_vma) disp;
+ }
+
+ print_operand_value (scratchbuf, mod != 1, disp);
+ oappend (scratchbuf);
+ }
+
*obufp++ = close_char;
*obufp = '\0';
}
+ else if (intel_syntax)
+ {
+ if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
+ | PREFIX_ES | PREFIX_FS | PREFIX_GS))
+ ;
+ else
+ {
+ oappend (names_seg[ds_reg - es_reg]);
+ oappend (":");
+ }
+ print_operand_value (scratchbuf, 1, disp & 0xffff);
+ oappend (scratchbuf);
+ }
}
}