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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/i386-opc.tbl2
-rw-r--r--opcodes/i386-tbl.h2
3 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bf495d0..f0840e3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2021-04-26 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (lea): Add Optimize.
+ * opcodes/i386-tbl.h: Re-generate.
+
2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
* xtensa-dis.c (print_xtensa_operand): For PC-relative operand
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 0c35848..b0530e5 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -228,7 +228,7 @@ out, 0xe6, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
out, 0xee, None, 0, W|No_sSuf|No_qSuf|No_ldSuf, { InOutPortReg }
// Load effective address.
-lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf, { BaseIndex, Reg16|Reg32|Reg64 }
+lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|No_ldSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
// Load segment registers from memory.
lds, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index d2ca247..df139ba 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -1121,7 +1121,7 @@ const insn_template i386_optab[] =
{ "lea", 0x8d, None, 2,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,