diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 9 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 1 |
3 files changed, 15 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9bfaea2..70a7195 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2015-12-14 Matthew Wahab <matthew.wahab@arm.coM> + + * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment + and adjust calculation to ignore qualifier for type 2H. + * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H". + 2015-12-14 Matthew Wahab <matthew.wahab@arm.com> * aarch64-asm-2.c: Regenerate. diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 6763c36..647ce0d 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -173,12 +173,19 @@ get_greg_qualifier_from_value (aarch64_insn value) return qualifier; } -/* Given VALUE, return qualifier for a vector register. */ +/* Given VALUE, return qualifier for a vector register. This does not support + decoding instructions that accept the 2H vector type. */ + static inline enum aarch64_opnd_qualifier get_vreg_qualifier_from_value (aarch64_insn value) { enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value; + /* Instructions using vector type 2H should not call this function. Skip over + the 2H qualifier. */ + if (qualifier >= AARCH64_OPND_QLF_V_2H) + qualifier += 1; + assert (value <= 0x8 && aarch64_get_qualifier_standard_value (qualifier) == value); return qualifier; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 88c4a28..28b991c 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -578,6 +578,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {1, 8, 0x0, "8b", OQK_OPD_VARIANT}, {1, 16, 0x1, "16b", OQK_OPD_VARIANT}, + {2, 2, 0x0, "2h", OQK_OPD_VARIANT}, {2, 4, 0x2, "4h", OQK_OPD_VARIANT}, {2, 8, 0x3, "8h", OQK_OPD_VARIANT}, {4, 2, 0x4, "2s", OQK_OPD_VARIANT}, |