diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 15 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 11 |
3 files changed, 30 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a9e1356..ce6624c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + + * mips-dis.c (mips_arch_choices): Add CAM to loongson3a + descriptors. + (parse_mips_ase_option): Handle -M loongson-cam option. + (print_mips_disassembler_options): Document -M loongson-cam. + * mips-opc.c (LCAM): New macro. + (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM + instructions. + 2018-08-21 Alan Modra <amodra@gmail.com> * ppc-dis.c (operand_value_powerpc): Init "invalid". diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4663016..832d4dc 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -630,8 +630,9 @@ const struct mips_arch_choice mips_arch_choices[] = NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, - ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI, mips_cp0_names_numeric, - NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + ISA_MIPS64R2 | INSN_LOONGSON_3A, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, + mips_hwr_names_numeric }, { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, @@ -941,6 +942,12 @@ parse_mips_ase_option (const char *option) return TRUE; } + if (CONST_STRNEQ (option, "loongson-cam")) + { + mips_ase |= ASE_LOONGSON_CAM; + return TRUE; + } + return FALSE; } @@ -2592,6 +2599,10 @@ static struct N_("Recognize the Loongson MultiMedia extensions " "Instructions (MMI) ASE instructions.\n"), MIPS_OPTION_ARG_NONE }, + { "loongson-cam", + N_("Recognize the Loongson Content Address Memory (CAM) " + " instructions.\n"), + MIPS_OPTION_ARG_NONE }, { "gpr-names=", N_("Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n"), MIPS_OPTION_ARG_ABI }, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 31532f8..5c9f28a 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -415,6 +415,9 @@ decode_mips_operand (const char *p) /* Loongson MultiMedia extensions Instructions (MMI) support. */ #define LMMI ASE_LOONGSON_MMI +/* Loongson Content Address Memory (CAM) support. */ +#define LCAM ASE_LOONGSON_CAM + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -459,10 +462,10 @@ const struct mips_opcode mips_builtin_opcodes[] = /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 instructions. Put them here so that disassembler will find them first. The assemblers uses a hash table based on the instruction name anyhow. */ -{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, -{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, -{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, IL3A, 0, 0 }, -{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, +{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, +{"camwi", "d,s,t", 0x700000b5, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, LCAM, 0 }, +{"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 }, {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, {"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, |