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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arm-dis.c6
2 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 585169f..96bc41c 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+ * arm-dis.c (arm_opcodes): Add csdb.
+ (thumb32_opcodes): Add csdb.
+
+2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
+
* aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index db48b32..5efe031 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1901,6 +1901,9 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
+ /* CSDB. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"},
+
/* ARM V6K NOP hints. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
0x0320f001, 0x0fffffff, "yield%c"},
@@ -2819,6 +2822,9 @@ static const struct opcode32 thumb32_opcodes[] =
/* Security extension instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
+ /* CSDB. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"},
+
/* Instructions defined in the basic V6T2 set. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
{ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},