diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 27 | ||||
| -rw-r--r-- | opcodes/Makefile.in | 2 | ||||
| -rw-r--r-- | opcodes/cgen-asm.in | 6 | ||||
| -rw-r--r-- | opcodes/cgen-dis.in | 40 | ||||
| -rw-r--r-- | opcodes/cgen-ibld.in | 31 | ||||
| -rw-r--r-- | opcodes/fr30-asm.c | 53 | ||||
| -rw-r--r-- | opcodes/fr30-desc.c | 18 | ||||
| -rw-r--r-- | opcodes/fr30-dis.c | 113 | ||||
| -rw-r--r-- | opcodes/fr30-ibld.c | 58 | ||||
| -rw-r--r-- | opcodes/fr30-opc.c | 13 | ||||
| -rw-r--r-- | opcodes/m32r-asm.c | 36 | ||||
| -rw-r--r-- | opcodes/m32r-desc.c | 17 | ||||
| -rw-r--r-- | opcodes/m32r-dis.c | 74 | ||||
| -rw-r--r-- | opcodes/m32r-ibld.c | 68 | ||||
| -rw-r--r-- | opcodes/m32r-opc.c | 13 | ||||
| -rw-r--r-- | opcodes/m32r-opinst.c | 6 | ||||
| -rw-r--r-- | opcodes/openrisc-asm.c | 35 | ||||
| -rw-r--r-- | opcodes/openrisc-desc.c | 17 | ||||
| -rw-r--r-- | opcodes/openrisc-dis.c | 44 | ||||
| -rw-r--r-- | opcodes/openrisc-ibld.c | 70 | ||||
| -rw-r--r-- | opcodes/openrisc-opc.c | 13 | ||||
| -rw-r--r-- | opcodes/openrisc-opc.h | 5 | ||||
| -rw-r--r-- | opcodes/po/POTFILES.in | 10 | ||||
| -rw-r--r-- | opcodes/po/opcodes.pot | 128 |
24 files changed, 488 insertions, 409 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 539c726..a523785 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,30 @@ +2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-asm.in: Fix compile time warning messages in generated + C files. + * cgen-dis.in: The same. + * cgen-ibld.in: The same. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opinst.c Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + 2001-10-08 Aldy Hernandez <aldyh@redhat.com> * arm-opc.h (arm_opcodes): Add cirrus insns. diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 7d0605e..2943416 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -389,7 +389,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = tar +TAR = gtar GZIP_ENV = --best SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS) diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in index 20380a2..936c635 100644 --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -35,6 +35,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "@prefix@-opc.h" #include "opintl.h" #include "xregex.h" +#include "libiberty.h" #undef min #define min(a,b) ((a) < (b) ? (a) : (b)) @@ -57,14 +58,13 @@ static const char * parse_insn_normal It then compiles the regex and stores it in the opcode, for later use by @arch@_cgen_assemble_insn - returns NULL for success, an error message for failure -*/ + Returns NULL for success, an error message for failure. */ char * @arch@_cgen_build_insn_regex (insn) CGEN_INSN *insn; { - CGEN_OPCODE *opc = CGEN_INSN_OPCODE (insn); + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); int mnem_len; char rxbuf[CGEN_MAX_RX_ELEMENTS]; diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index 2c4ce7f..7065644 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -47,10 +47,13 @@ static void print_keyword static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); -static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, - disassemble_info *, char *, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); /* -- disassembler routines inserted here */ @@ -58,21 +61,12 @@ static int default_print_insn static void print_normal (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; long value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -93,21 +87,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; bfd_vma value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -190,9 +175,10 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) /* Subroutine of print_insn. Reads an insn into the given buffers and updates the extract info. Returns 0 if all is well, non-zero otherwise. */ + static int read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; bfd_vma pc; disassemble_info *info; char *buf; @@ -227,7 +213,7 @@ print_insn (cd, pc, info, buf, buflen) bfd_vma pc; disassemble_info *info; char *buf; - int buflen; + unsigned int buflen; { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -255,7 +241,7 @@ print_insn (cd, pc, info, buf, buflen) unsigned long insn_value_cropped; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not needed as insn shouldn't be in hash lists if not supported */ + /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ if (! @arch@_cgen_insn_supported (cd, insn)) { @@ -270,8 +256,8 @@ print_insn (cd, pc, info, buf, buflen) /* Base size may exceed this instruction's size. Extract the relevant part from the buffer. */ - if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && - (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), info->endian == BFD_ENDIAN_BIG); else @@ -286,8 +272,8 @@ print_insn (cd, pc, info, buf, buflen) /* Make sure the entire insn is loaded into insn_value, if it can fit. */ - if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && - (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { unsigned long full_insn_value; int rc = read_insn (cd, pc, info, buf, diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in index 61233bd..9103524 100644 --- a/opcodes/cgen-ibld.in +++ b/opcodes/cgen-ibld.in @@ -49,7 +49,6 @@ static const char * insert_normal static const char * insert_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - static int extract_normal PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, unsigned int, unsigned int, unsigned int, unsigned int, @@ -57,9 +56,19 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P static void put_insn_int_value PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); - +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif /* Operand insertion. */ @@ -76,7 +85,6 @@ insert_1 (cd, value, start, length, word_length, bufp) { unsigned long x,mask; int shift; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; x = cgen_get_insn_value (cd, bufp, word_length); @@ -248,8 +256,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #else - cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, - CGEN_FIELDS_BITSIZE (fields)), + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), value); #endif /* ! CGEN_INT_INSN_P */ @@ -275,6 +283,7 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } +#if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ @@ -298,6 +307,7 @@ put_insn_int_value (cd, buf, length, insn_length, value) *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } +#endif /* Operand extraction. */ @@ -311,14 +321,14 @@ put_insn_int_value (cd, buf, length, insn_length, value) static CGEN_INLINE int fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_EXTRACT_INFO *ex_info; int offset, bytes; bfd_vma pc; { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ - int mask; + unsigned int mask; disassemble_info *info = (disassemble_info *) ex_info->dis_info; /* First do a quick check. */ @@ -356,17 +366,18 @@ fill_cache (cd, ex_info, offset, bytes, pc) static CGEN_INLINE long extract_1 (cd, ex_info, start, length, word_length, bufp, pc) CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; int start,length,word_length; unsigned char *bufp; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { unsigned long x; int shift; +#if 0 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; x = cgen_get_insn_value (cd, bufp, word_length); - +#endif if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; else diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c index eae0620..da62c6e 100644 --- a/opcodes/fr30-asm.c +++ b/opcodes/fr30-asm.c @@ -26,9 +26,9 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" -#include "safe-ctype.h" #include "bfd.h" #include "symcat.h" #include "fr30-desc.h" @@ -42,19 +42,26 @@ along with this program; if not, write to the Free Software Foundation, Inc., #undef max #define max(a,b) ((a) > (b) ? (a) : (b)) -static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); -static int parse_register_number PARAMS ((const char **)); -static const char * parse_register_list PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int)); -static const char * parse_low_register_list_ld PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi_register_list_ld PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_low_register_list_st PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi_register_list_st PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); - const char * fr30_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); /* -- assembler routines inserted here */ /* -- asm.c */ -/* Handle register lists for LDMx and STMx */ +/* Handle register lists for LDMx and STMx. */ + +static int parse_register_number + PARAMS ((const char **)); +static const char * parse_register_list + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *, int, int)); +static const char * parse_low_register_list_ld + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi_register_list_ld + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_low_register_list_st + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi_register_list_st + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); static int parse_register_number (strp) @@ -62,7 +69,7 @@ parse_register_number (strp) { int regno; if (**strp < '0' || **strp > '9') - return -1; /* error */ + return -1; /* error. */ regno = **strp - '0'; ++*strp; @@ -85,6 +92,7 @@ parse_register_list (cd, strp, opindex, valuep, high_low, load_store) int load_store; /* 0 == load, 1 == store */ { int regno; + *valuep = 0; while (**strp && **strp != ')') { @@ -103,7 +111,7 @@ parse_register_list (cd, strp, opindex, valuep, high_low, load_store) if (high_low) regno -= 8; - if (load_store) /* mask is reversed for store */ + if (load_store) /* Mask is reversed for store. */ *valuep |= 0x80 >> regno; else *valuep |= 1 << regno; @@ -164,6 +172,9 @@ parse_hi_register_list_st (cd, strp, opindex, valuep) /* -- */ +const char * fr30_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + /* Main entry point for operand parsing. This function is basically just a big switch statement. Earlier versions @@ -175,7 +186,8 @@ parse_hi_register_list_st (cd, strp, opindex, valuep) This function could be moved into `parse_insn_normal', but keeping it separate makes clear the interface between `parse_insn_normal' and each of - the handlers. */ + the handlers. +*/ const char * fr30_cgen_parse_operand (cd, opindex, strp, fields) @@ -186,7 +198,7 @@ fr30_cgen_parse_operand (cd, opindex, strp, fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ - long junk; + long junk ATTRIBUTE_UNUSED; switch (opindex) { @@ -343,8 +355,7 @@ fr30_cgen_init_asm (cd) It then compiles the regex and stores it in the opcode, for later use by fr30_cgen_assemble_insn - returns NULL for success, an error message for failure -*/ + Returns NULL for success, an error message for failure. */ char * fr30_cgen_build_insn_regex (insn) @@ -467,14 +478,14 @@ parse_insn_normal (cd, insn, strp, fields) GAS's input scrubber will ensure mnemonics are lowercase, but we may not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && TOLOWER (*p) == TOLOWER (*str)) + while (*p && tolower (*p) == tolower (*str)) ++p, ++str; if (* p) return _("unrecognized instruction"); #ifndef CGEN_MNEMONIC_OPERANDS - if (* str && !ISSPACE (* str)) + if (* str && !isspace (* str)) return _("unrecognized instruction"); #endif @@ -503,7 +514,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (CGEN_SYNTAX_CHAR(* syn) == ' ') @@ -550,7 +561,7 @@ parse_insn_normal (cd, insn, strp, fields) blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; if (* str != '\0') @@ -599,7 +610,7 @@ fr30_cgen_assemble_insn (cd, str, fields, buf, errmsg) int recognized_mnemonic = 0; /* Skip leading white space. */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; /* The instructions are stored in hashed lists. diff --git a/opcodes/fr30-desc.c b/opcodes/fr30-desc.c index 9fc4379..e3a1c8b 100644 --- a/opcodes/fr30-desc.c +++ b/opcodes/fr30-desc.c @@ -23,6 +23,7 @@ with this program; if not, write to the Free Software Foundation, Inc., */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" @@ -33,14 +34,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "opintl.h" #include "libiberty.h" -static void init_tables PARAMS ((void)); -static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); - /* Attributes. */ static const CGEN_ATTR_ENTRY bool_attr[] = @@ -1368,12 +1361,21 @@ static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] = #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ +static void init_tables PARAMS ((void)); static void init_tables () { } +static const CGEN_MACH * lookup_mach_via_bfd_name + PARAMS ((const CGEN_MACH *, const char *)); +static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); +static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); + /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index f9adba5..5de2681 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -38,24 +38,38 @@ along with this program; if not, write to the Free Software Foundation, Inc., /* Default text to print if an instruction isn't recognized. */ #define UNKNOWN_INSN_MSG _("*unknown*") -static void print_normal PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_address PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned, bfd_vma, int)); -static void print_keyword PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned)); -static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); -static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int)); -static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); -static void print_register_list PARAMS ((PTR, long, long, int)); -static void print_hi_register_list_ld PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_low_register_list_ld PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_hi_register_list_st PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_low_register_list_st PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static void print_m4 PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); - void fr30_cgen_print_operand PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int)); -static int read_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *)); +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); /* -- disassembler routines inserted here */ /* -- dis.c */ +static void print_register_list + PARAMS ((PTR, long, long, int)); +static void print_hi_register_list_ld + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_low_register_list_ld + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_hi_register_list_st + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_low_register_list_st + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static void print_m4 + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); static void print_register_list (dis_info, value, offset, load_store) @@ -97,66 +111,70 @@ print_register_list (dis_info, value, offset, load_store) static void print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + unsigned int attrs; + bfd_vma pc; + int length; { print_register_list (dis_info, value, 8, 0/*load*/); } static void print_low_register_list_ld (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + unsigned int attrs; + bfd_vma pc; + int length; { print_register_list (dis_info, value, 0, 0/*load*/); } static void print_hi_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + unsigned int attrs; + bfd_vma pc; + int length; { print_register_list (dis_info, value, 8, 1/*store*/); } static void print_low_register_list_st (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + unsigned int attrs; + bfd_vma pc; + int length; { print_register_list (dis_info, value, 0, 1/*store*/); } static void print_m4 (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; long value; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + unsigned int attrs; + bfd_vma pc; + int length; { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "%ld", value); } /* -- */ +void fr30_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement of dis-asm.h on cgen.h. @@ -325,21 +343,12 @@ fr30_cgen_init_dis (cd) static void print_normal (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; long value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -360,21 +369,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; bfd_vma value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -457,6 +457,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) /* Subroutine of print_insn. Reads an insn into the given buffers and updates the extract info. Returns 0 if all is well, non-zero otherwise. */ + static int read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; @@ -494,7 +495,7 @@ print_insn (cd, pc, info, buf, buflen) bfd_vma pc; disassemble_info *info; char *buf; - int buflen; + unsigned int buflen; { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -522,7 +523,7 @@ print_insn (cd, pc, info, buf, buflen) unsigned long insn_value_cropped; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not needed as insn shouldn't be in hash lists if not supported */ + /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ if (! fr30_cgen_insn_supported (cd, insn)) { @@ -537,7 +538,7 @@ print_insn (cd, pc, info, buf, buflen) /* Base size may exceed this instruction's size. Extract the relevant part from the buffer. */ - if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), info->endian == BFD_ENDIAN_BIG); @@ -553,7 +554,7 @@ print_insn (cd, pc, info, buf, buflen) /* Make sure the entire insn is loaded into insn_value, if it can fit. */ - if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { unsigned long full_insn_value; diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c index 7c07886..99bf3ac 100644 --- a/opcodes/fr30-ibld.c +++ b/opcodes/fr30-ibld.c @@ -25,6 +25,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "dis-asm.h" @@ -59,27 +60,15 @@ static int extract_insn_normal static void put_insn_int_value PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); #endif -static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); -static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, - bfd_vma)); +#if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); -const char * fr30_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); -int fr30_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, - bfd_vma)); -int fr30_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma fr30_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -void fr30_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void fr30_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); - +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif /* Operand insertion. */ @@ -96,9 +85,8 @@ insert_1 (cd, value, start, length, word_length, bufp) { unsigned long x,mask; int shift; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); + x = cgen_get_insn_value (cd, bufp, word_length); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -108,7 +96,7 @@ insert_1 (cd, value, start, length, word_length, bufp) shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); } #endif /* ! CGEN_INT_INSN_P */ @@ -268,7 +256,7 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #else - cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, (unsigned) CGEN_FIELDS_BITSIZE (fields)), value); @@ -385,10 +373,11 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) { unsigned long x; int shift; +#if 0 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); - + x = cgen_get_insn_value (cd, bufp, word_length); +#endif if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; else @@ -550,6 +539,9 @@ extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) /* machine generated code added here */ +const char * fr30_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + /* Main entry point for operand insertion. This function is basically just a big switch statement. Earlier versions @@ -571,7 +563,7 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) int opindex; CGEN_FIELDS * fields; CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -744,6 +736,10 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) return errmsg; } +int fr30_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. ??? Actual values aren't well defined right now. @@ -958,6 +954,11 @@ cgen_extract_fn * const fr30_cgen_extract_handlers[] = extract_insn_normal, }; +int fr30_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma fr30_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. TODO: floating point, inlining support, remove cases where result type @@ -1221,6 +1222,11 @@ fr30_cgen_get_vma_operand (cd, opindex, fields) return value; } +void fr30_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void fr30_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. TODO: floating point, inlining support, remove cases where argument type diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c index caa039a..e1167d9 100644 --- a/opcodes/fr30-opc.c +++ b/opcodes/fr30-opc.c @@ -33,11 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc., /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); /* Instruction formats. */ @@ -1335,12 +1334,14 @@ asm_hash_insn (mnem) static unsigned int dis_hash_insn (buf, value) - const char * buf; + const char * buf ATTRIBUTE_UNUSED; CGEN_INSN_INT value ATTRIBUTE_UNUSED; { return CGEN_DIS_HASH (buf, value); } +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index a12cfd8..496ab47 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -26,9 +26,9 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" -#include "safe-ctype.h" #include "bfd.h" #include "symcat.h" #include "m32r-desc.h" @@ -42,16 +42,20 @@ along with this program; if not, write to the Free Software Foundation, Inc., #undef max #define max(a,b) ((a) > (b) ? (a) : (b)) -static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); -static const char * parse_hash PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_slo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); -static const char * parse_ulo16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); - const char * m32r_cgen_parse_operand PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); /* -- assembler routines inserted here */ /* -- asm.c */ +static const char * parse_hash + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_slo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_ulo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); /* Handle '#' prefixes (i.e. skip over them). */ @@ -201,6 +205,9 @@ parse_ulo16 (cd, strp, opindex, valuep) /* -- */ +const char * m32r_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + /* Main entry point for operand parsing. This function is basically just a big switch statement. Earlier versions @@ -224,7 +231,7 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ - long junk; + long junk ATTRIBUTE_UNUSED; switch (opindex) { @@ -350,8 +357,7 @@ m32r_cgen_init_asm (cd) It then compiles the regex and stores it in the opcode, for later use by m32r_cgen_assemble_insn - returns NULL for success, an error message for failure -*/ + Returns NULL for success, an error message for failure. */ char * m32r_cgen_build_insn_regex (insn) @@ -474,14 +480,14 @@ parse_insn_normal (cd, insn, strp, fields) GAS's input scrubber will ensure mnemonics are lowercase, but we may not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && TOLOWER (*p) == TOLOWER (*str)) + while (*p && tolower (*p) == tolower (*str)) ++p, ++str; if (* p) return _("unrecognized instruction"); #ifndef CGEN_MNEMONIC_OPERANDS - if (* str && !ISSPACE (* str)) + if (* str && !isspace (* str)) return _("unrecognized instruction"); #endif @@ -510,7 +516,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (CGEN_SYNTAX_CHAR(* syn) == ' ') @@ -557,7 +563,7 @@ parse_insn_normal (cd, insn, strp, fields) blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; if (* str != '\0') @@ -606,7 +612,7 @@ m32r_cgen_assemble_insn (cd, str, fields, buf, errmsg) int recognized_mnemonic = 0; /* Skip leading white space. */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; /* The instructions are stored in hashed lists. diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c index 824beea..5c63a2f 100644 --- a/opcodes/m32r-desc.c +++ b/opcodes/m32r-desc.c @@ -23,6 +23,7 @@ with this program; if not, write to the Free Software Foundation, Inc., */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" @@ -33,13 +34,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "opintl.h" #include "libiberty.h" -static void init_tables PARAMS ((void)); -static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); /* Attributes. */ static const CGEN_ATTR_ENTRY bool_attr[] = @@ -1091,12 +1085,21 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] = #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ +static void init_tables PARAMS ((void)); static void init_tables () { } +static const CGEN_MACH * lookup_mach_via_bfd_name + PARAMS ((const CGEN_MACH *, const char *)); +static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); +static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); + /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 150f6ee..287d6bc 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -48,13 +48,9 @@ static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int)); -static void print_hash - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); -static int my_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); -void m32r_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int)); static int read_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *)); @@ -62,31 +58,35 @@ static int read_insn /* -- disassembler routines inserted here */ /* -- dis.c */ +static void print_hash PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int)); +static int my_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); /* Immediate values are prefixed with '#'. */ -#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ -do { \ - if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ - (*info->fprintf_func) (info->stream, "#"); \ -} while (0) +#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length) \ + do \ + { \ + if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_HASH_PREFIX)) \ + (*info->fprintf_func) (info->stream, "#"); \ + } \ + while (0) /* Handle '#' prefixes as operands. */ static void print_hash (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_CPU_DESC cd; PTR dis_info; - long value ATTRIBUTE_UNUSED; - unsigned int attrs ATTRIBUTE_UNUSED; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; + long value; + unsigned int attrs; + bfd_vma pc; + int length; { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "#"); } -#undef CGEN_PRINT_INSN +#undef CGEN_PRINT_INSN #define CGEN_PRINT_INSN my_print_insn static int @@ -141,6 +141,10 @@ my_print_insn (cd, pc, info) /* -- */ +void m32r_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement of dis-asm.h on cgen.h. @@ -270,21 +274,12 @@ m32r_cgen_init_dis (cd) static void print_normal (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#else - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; long value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -305,21 +300,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; bfd_vma value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#else - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -402,6 +388,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) /* Subroutine of print_insn. Reads an insn into the given buffers and updates the extract info. Returns 0 if all is well, non-zero otherwise. */ + static int read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; @@ -439,7 +426,7 @@ print_insn (cd, pc, info, buf, buflen) bfd_vma pc; disassemble_info *info; char *buf; - int buflen; + unsigned int buflen; { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -467,7 +454,7 @@ print_insn (cd, pc, info, buf, buflen) unsigned long insn_value_cropped; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not needed as insn shouldn't be in hash lists if not supported */ + /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ if (! m32r_cgen_insn_supported (cd, insn)) { @@ -482,8 +469,8 @@ print_insn (cd, pc, info, buf, buflen) /* Base size may exceed this instruction's size. Extract the relevant part from the buffer. */ - if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen - && (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), info->endian == BFD_ENDIAN_BIG); else @@ -498,8 +485,8 @@ print_insn (cd, pc, info, buf, buflen) /* Make sure the entire insn is loaded into insn_value, if it can fit. */ - if ((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize - && ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { unsigned long full_insn_value; int rc = read_insn (cd, pc, info, buf, @@ -537,9 +524,7 @@ print_insn (cd, pc, info, buf, buflen) #ifndef CGEN_PRINT_INSN #define CGEN_PRINT_INSN default_print_insn - -static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +#endif static int default_print_insn (cd, pc, info) @@ -570,7 +555,6 @@ default_print_insn (cd, pc, info) return print_insn (cd, pc, info, buf, buflen); } -#endif /* Main entry point. Print one instruction from PC on INFO->STREAM. diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index 3541f71..6c32b23 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -25,6 +25,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "dis-asm.h" @@ -48,7 +49,6 @@ static const char * insert_normal static const char * insert_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - static int extract_normal PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, unsigned int, unsigned int, unsigned int, unsigned int, @@ -56,20 +56,19 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P static void put_insn_int_value PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); -const char * m32r_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); -int m32r_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); -int m32r_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma m32r_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -void m32r_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void m32r_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif /* Operand insertion. */ @@ -86,9 +85,8 @@ insert_1 (cd, value, start, length, word_length, bufp) { unsigned long x,mask; int shift; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); + x = cgen_get_insn_value (cd, bufp, word_length); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +96,7 @@ insert_1 (cd, value, start, length, word_length, bufp) shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); } #endif /* ! CGEN_INT_INSN_P */ @@ -258,8 +256,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #else - cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, - CGEN_FIELDS_BITSIZE (fields)), + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), value); #endif /* ! CGEN_INT_INSN_P */ @@ -285,6 +283,7 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } +#if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ @@ -308,6 +307,7 @@ put_insn_int_value (cd, buf, length, insn_length, value) *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } +#endif /* Operand extraction. */ @@ -321,14 +321,14 @@ put_insn_int_value (cd, buf, length, insn_length, value) static CGEN_INLINE int fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_EXTRACT_INFO *ex_info; int offset, bytes; bfd_vma pc; { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ - int mask; + unsigned int mask; disassemble_info *info = (disassemble_info *) ex_info->dis_info; /* First do a quick check. */ @@ -366,17 +366,18 @@ fill_cache (cd, ex_info, offset, bytes, pc) static CGEN_INLINE long extract_1 (cd, ex_info, start, length, word_length, bufp, pc) CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; int start,length,word_length; unsigned char *bufp; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { unsigned long x; int shift; +#if 0 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); - + x = cgen_get_insn_value (cd, bufp, word_length); +#endif if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; else @@ -538,6 +539,9 @@ extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) /* machine generated code added here */ +const char * m32r_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + /* Main entry point for operand insertion. This function is basically just a big switch statement. Earlier versions @@ -559,7 +563,7 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) int opindex; CGEN_FIELDS * fields; CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -661,6 +665,10 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) return errmsg; } +int m32r_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. ??? Actual values aren't well defined right now. @@ -801,6 +809,11 @@ cgen_extract_fn * const m32r_cgen_extract_handlers[] = extract_insn_normal, }; +int m32r_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma m32r_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. TODO: floating point, inlining support, remove cases where result type @@ -986,6 +999,11 @@ m32r_cgen_get_vma_operand (cd, opindex, fields) return value; } +void m32r_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void m32r_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. TODO: floating point, inlining support, remove cases where argument type diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 5793ad6..56e7c93 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -33,11 +33,10 @@ with this program; if not, write to the Free Software Foundation, Inc., /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); /* Instruction formats. */ @@ -1652,12 +1651,14 @@ asm_hash_insn (mnem) static unsigned int dis_hash_insn (buf, value) - const char * buf; + const char * buf ATTRIBUTE_UNUSED; CGEN_INSN_INT value ATTRIBUTE_UNUSED; { return CGEN_DIS_HASH (buf, value); } +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c index 781f8e7..aaaa1c0 100644 --- a/opcodes/m32r-opinst.c +++ b/opcodes/m32r-opinst.c @@ -36,9 +36,9 @@ with this program; if not, write to the Free Software Foundation, Inc., #else #define OP_ENT(op) M32R_OPERAND_/**/op #endif -#define INPUT CGEN_OPINST_INPUT -#define OUTPUT CGEN_OPINST_OUTPUT -#define END CGEN_OPINST_END, "", 0, 0, 0, 0, 0 +#define INPUT CGEN_OPINST_INPUT +#define OUTPUT CGEN_OPINST_OUTPUT +#define END CGEN_OPINST_END #define COND_REF CGEN_OPINST_COND_REF static const CGEN_OPINST sfmt_empty_ops[] = { diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c index b414cb5..de9b554 100644 --- a/opcodes/openrisc-asm.c +++ b/opcodes/openrisc-asm.c @@ -26,9 +26,9 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" -#include "safe-ctype.h" #include "bfd.h" #include "symcat.h" #include "openrisc-desc.h" @@ -44,14 +44,6 @@ along with this program; if not, write to the Free Software Foundation, Inc., static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); -long openrisc_sign_extend_16bit - PARAMS ((long)); -static const char * parse_hi16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -static const char * parse_lo16 - PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); -const char * openrisc_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); /* -- assembler routines inserted here */ @@ -59,6 +51,11 @@ const char * openrisc_cgen_parse_operand #define CGEN_VERBOSE_ASSEMBLER_ERRORS +static const char * parse_hi16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_lo16 + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); + long openrisc_sign_extend_16bit (value) long value; @@ -66,7 +63,6 @@ openrisc_sign_extend_16bit (value) return (long) (short) value; } - /* Handle hi(). */ static const char * @@ -116,8 +112,7 @@ parse_hi16 (cd, strp, opindex, valuep) return errmsg; } - -/* Handle lo() */ +/* Handle lo(). */ static const char * parse_lo16 (cd, strp, opindex, valuep) @@ -167,6 +162,9 @@ parse_lo16 (cd, strp, opindex, valuep) /* -- */ +const char * openrisc_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + /* Main entry point for operand parsing. This function is basically just a big switch statement. Earlier versions @@ -278,8 +276,7 @@ openrisc_cgen_init_asm (cd) It then compiles the regex and stores it in the opcode, for later use by openrisc_cgen_assemble_insn - returns NULL for success, an error message for failure -*/ + Returns NULL for success, an error message for failure. */ char * openrisc_cgen_build_insn_regex (insn) @@ -402,14 +399,14 @@ parse_insn_normal (cd, insn, strp, fields) GAS's input scrubber will ensure mnemonics are lowercase, but we may not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && TOLOWER (*p) == TOLOWER (*str)) + while (*p && tolower (*p) == tolower (*str)) ++p, ++str; if (* p) return _("unrecognized instruction"); #ifndef CGEN_MNEMONIC_OPERANDS - if (* str && !ISSPACE (* str)) + if (* str && !isspace (* str)) return _("unrecognized instruction"); #endif @@ -438,7 +435,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (CGEN_SYNTAX_CHAR(* syn) == ' ') @@ -485,7 +482,7 @@ parse_insn_normal (cd, insn, strp, fields) blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; if (* str != '\0') @@ -534,7 +531,7 @@ openrisc_cgen_assemble_insn (cd, str, fields, buf, errmsg) int recognized_mnemonic = 0; /* Skip leading white space. */ - while (ISSPACE (* str)) + while (isspace (* str)) ++ str; /* The instructions are stored in hashed lists. diff --git a/opcodes/openrisc-desc.c b/opcodes/openrisc-desc.c index 08eadeb..866dbdd 100644 --- a/opcodes/openrisc-desc.c +++ b/opcodes/openrisc-desc.c @@ -23,6 +23,7 @@ with this program; if not, write to the Free Software Foundation, Inc., */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include <stdarg.h> #include "ansidecl.h" @@ -33,13 +34,6 @@ with this program; if not, write to the Free Software Foundation, Inc., #include "opintl.h" #include "libiberty.h" -static void init_tables PARAMS ((void)); -static const CGEN_MACH * lookup_mach_via_bfd_name PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); /* Attributes. */ static const CGEN_ATTR_ENTRY bool_attr[] = @@ -670,12 +664,21 @@ static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] = #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ +static void init_tables PARAMS ((void)); static void init_tables () { } +static const CGEN_MACH * lookup_mach_via_bfd_name + PARAMS ((const CGEN_MACH *, const char *)); +static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); +static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); + /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * diff --git a/opcodes/openrisc-dis.c b/opcodes/openrisc-dis.c index cf9a24f..6bbb0cb 100644 --- a/opcodes/openrisc-dis.c +++ b/opcodes/openrisc-dis.c @@ -47,18 +47,21 @@ static void print_keyword static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); -static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, - disassemble_info *, char *, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); -void openrisc_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int)); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, unsigned long *)); + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); /* -- disassembler routines inserted here */ +void openrisc_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement of dis-asm.h on cgen.h. @@ -158,21 +161,12 @@ openrisc_cgen_init_dis (cd) static void print_normal (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; long value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -193,21 +187,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; bfd_vma value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -290,6 +275,7 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) /* Subroutine of print_insn. Reads an insn into the given buffers and updates the extract info. Returns 0 if all is well, non-zero otherwise. */ + static int read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; @@ -327,7 +313,7 @@ print_insn (cd, pc, info, buf, buflen) bfd_vma pc; disassemble_info *info; char *buf; - int buflen; + unsigned int buflen; { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -355,7 +341,7 @@ print_insn (cd, pc, info, buf, buflen) unsigned long insn_value_cropped; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not needed as insn shouldn't be in hash lists if not supported */ + /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ if (! openrisc_cgen_insn_supported (cd, insn)) { @@ -370,8 +356,8 @@ print_insn (cd, pc, info, buf, buflen) /* Base size may exceed this instruction's size. Extract the relevant part from the buffer. */ - if ((CGEN_INSN_BITSIZE (insn) / 8) < buflen && - ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), info->endian == BFD_ENDIAN_BIG); else @@ -386,8 +372,8 @@ print_insn (cd, pc, info, buf, buflen) /* Make sure the entire insn is loaded into insn_value, if it can fit. */ - if ( (unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && - ((unsigned) CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { unsigned long full_insn_value; int rc = read_insn (cd, pc, info, buf, diff --git a/opcodes/openrisc-ibld.c b/opcodes/openrisc-ibld.c index b219f53..cb29a26 100644 --- a/opcodes/openrisc-ibld.c +++ b/opcodes/openrisc-ibld.c @@ -25,6 +25,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" +#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "dis-asm.h" @@ -48,7 +49,6 @@ static const char * insert_normal static const char * insert_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - static int extract_normal PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, unsigned int, unsigned int, unsigned int, unsigned int, @@ -56,20 +56,19 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P static void put_insn_int_value PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); -const char * openrisc_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); -int openrisc_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); -int openrisc_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma openrisc_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -void openrisc_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void openrisc_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif /* Operand insertion. */ @@ -86,9 +85,8 @@ insert_1 (cd, value, start, length, word_length, bufp) { unsigned long x,mask; int shift; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); + x = cgen_get_insn_value (cd, bufp, word_length); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +96,7 @@ insert_1 (cd, value, start, length, word_length, bufp) shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); } #endif /* ! CGEN_INT_INSN_P */ @@ -258,8 +256,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #else - cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, - CGEN_FIELDS_BITSIZE (fields)), + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), value); #endif /* ! CGEN_INT_INSN_P */ @@ -285,6 +283,7 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } +#if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ @@ -308,6 +307,7 @@ put_insn_int_value (cd, buf, length, insn_length, value) *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } +#endif /* Operand extraction. */ @@ -321,14 +321,14 @@ put_insn_int_value (cd, buf, length, insn_length, value) static CGEN_INLINE int fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_EXTRACT_INFO *ex_info; int offset, bytes; bfd_vma pc; { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ - int mask; + unsigned int mask; disassemble_info *info = (disassemble_info *) ex_info->dis_info; /* First do a quick check. */ @@ -366,17 +366,18 @@ fill_cache (cd, ex_info, offset, bytes, pc) static CGEN_INLINE long extract_1 (cd, ex_info, start, length, word_length, bufp, pc) CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; int start,length,word_length; unsigned char *bufp; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { unsigned long x; int shift; +#if 0 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); - + x = cgen_get_insn_value (cd, bufp, word_length); +#endif if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; else @@ -538,6 +539,9 @@ extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) /* machine generated code added here */ +const char * openrisc_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + /* Main entry point for operand insertion. This function is basically just a big switch statement. Earlier versions @@ -559,7 +563,7 @@ openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc) int opindex; CGEN_FIELDS * fields; CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -635,6 +639,10 @@ openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc) return errmsg; } +int openrisc_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. ??? Actual values aren't well defined right now. @@ -713,8 +721,6 @@ openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_i16_2); if (length <= 0) break; { - extern long openrisc_sign_extend_16bit PARAMS ((long)); - FLD (f_i16nc) = openrisc_sign_extend_16bit (((((FLD (f_i16_2)) << (11))) | (FLD (f_i16_1)))); } } @@ -746,6 +752,11 @@ cgen_extract_fn * const openrisc_cgen_extract_handlers[] = extract_insn_normal, }; +int openrisc_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma openrisc_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. TODO: floating point, inlining support, remove cases where result type @@ -871,6 +882,11 @@ openrisc_cgen_get_vma_operand (cd, opindex, fields) return value; } +void openrisc_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void openrisc_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. TODO: floating point, inlining support, remove cases where argument type diff --git a/opcodes/openrisc-opc.c b/opcodes/openrisc-opc.c index 12ca306..87a397b 100644 --- a/opcodes/openrisc-opc.c +++ b/opcodes/openrisc-opc.c @@ -35,11 +35,10 @@ with this program; if not, write to the Free Software Foundation, Inc., /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); /* Instruction formats. */ @@ -645,12 +644,14 @@ asm_hash_insn (mnem) static unsigned int dis_hash_insn (buf, value) - const char * buf; + const char * buf ATTRIBUTE_UNUSED; CGEN_INSN_INT value ATTRIBUTE_UNUSED; { return CGEN_DIS_HASH (buf, value); } +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void diff --git a/opcodes/openrisc-opc.h b/opcodes/openrisc-opc.h index 50515ac..bdd7e24 100644 --- a/opcodes/openrisc-opc.h +++ b/opcodes/openrisc-opc.h @@ -26,11 +26,12 @@ with this program; if not, write to the Free Software Foundation, Inc., #define OPENRISC_OPC_H /* -- opc.h */ -#undef CGEN_DIS_HASH_SIZE +#undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 64 -#undef CGEN_DIS_HASH +#undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) +extern long openrisc_sign_extend_16bit PARAMS ((long)); /* -- */ /* Enum declaration for openrisc instruction types. */ typedef enum cgen_insn_type { diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index 220711c..6b01ed9 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -16,8 +16,8 @@ d10v-dis.c d10v-opc.c d30v-dis.c d30v-opc.c -dis-buf.c disassemble.c +dis-buf.c fr30-asm.c fr30-desc.c fr30-desc.h @@ -40,12 +40,12 @@ ia64-dis.c ia64-gen.c ia64-opc-a.c ia64-opc-b.c +ia64-opc.c ia64-opc-d.c ia64-opc-f.c +ia64-opc.h ia64-opc-i.c ia64-opc-m.c -ia64-opc.c -ia64-opc.h m10200-dis.c m10200-opc.c m10300-dis.c @@ -65,9 +65,9 @@ m68k-opc.c m88k-dis.c mcore-dis.c mcore-opc.h +mips16-opc.c mips-dis.c mips-opc.c -mips16-opc.c ns32k-dis.c openrisc-asm.c openrisc-desc.c @@ -101,5 +101,5 @@ vax-dis.c w65-dis.c w65-opc.h z8k-dis.c -z8k-opc.h z8kgen.c +z8k-opc.h diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot index e813574..8baf99e 100644 --- a/opcodes/po/opcodes.pot +++ b/opcodes/po/opcodes.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2001-04-27 15:23+0100\n" +"POT-Creation-Date: 2001-10-09 09:40+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -22,21 +22,21 @@ msgstr "" msgid "jump hint unaligned" msgstr "" -#: arm-dis.c:490 +#: arm-dis.c:509 msgid "<illegal precision>" msgstr "" -#: arm-dis.c:922 +#: arm-dis.c:941 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" -#: arm-dis.c:929 +#: arm-dis.c:948 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:1101 +#: arm-dis.c:1120 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -56,21 +56,21 @@ msgstr "" msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:224 +#: cgen-asm.c:232 msgid "unrecognized keyword/register name" msgstr "" -#: cgen-asm.c:332 fr30-ibld.c:172 m32r-ibld.c:172 openrisc-ibld.c:172 +#: cgen-asm.c:340 fr30-ibld.c:207 m32r-ibld.c:197 openrisc-ibld.c:197 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" -#: cgen-asm.c:353 +#: cgen-asm.c:361 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" -#: d30v-dis.c:306 +#: d30v-dis.c:312 #, c-format msgid "<unknown register %d>" msgstr "" @@ -86,99 +86,108 @@ msgstr "" msgid "Address 0x%x is out of bounds.\n" msgstr "" -#: fr30-asm.c:305 m32r-asm.c:313 openrisc-asm.c:237 +#: fr30-asm.c:312 m32r-asm.c:319 openrisc-asm.c:247 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:458 fr30-asm.c:552 m32r-asm.c:377 -#: m32r-asm.c:381 m32r-asm.c:466 m32r-asm.c:560 openrisc-asm.c:301 -#: openrisc-asm.c:305 openrisc-asm.c:390 openrisc-asm.c:484 +#: fr30-asm.c:474 fr30-asm.c:478 fr30-asm.c:563 fr30-asm.c:665 m32r-asm.c:481 +#: m32r-asm.c:485 m32r-asm.c:570 m32r-asm.c:672 openrisc-asm.c:409 +#: openrisc-asm.c:413 openrisc-asm.c:498 openrisc-asm.c:600 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:415 m32r-asm.c:423 openrisc-asm.c:347 +#: fr30-asm.c:520 m32r-asm.c:527 openrisc-asm.c:455 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:424 m32r-asm.c:432 openrisc-asm.c:356 +#: fr30-asm.c:529 m32r-asm.c:536 openrisc-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:452 m32r-asm.c:460 openrisc-asm.c:384 +#: fr30-asm.c:557 m32r-asm.c:564 openrisc-asm.c:492 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:563 m32r-asm.c:571 openrisc-asm.c:495 +#: fr30-asm.c:664 m32r-asm.c:671 openrisc-asm.c:599 +msgid "unrecognized form of instruction" +msgstr "" + +#: fr30-asm.c:676 m32r-asm.c:683 openrisc-asm.c:611 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:566 m32r-asm.c:574 openrisc-asm.c:498 +#: fr30-asm.c:679 m32r-asm.c:686 openrisc-asm.c:614 #, c-format msgid "bad instruction `%.50s'" msgstr "" -#: fr30-dis.c:300 m32r-dis.c:239 openrisc-dis.c:130 +#: fr30-dis.c:301 m32r-dis.c:246 openrisc-dis.c:134 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:156 m32r-ibld.c:156 openrisc-ibld.c:156 +#: fr30-ibld.c:178 m32r-ibld.c:168 openrisc-ibld.c:168 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "" + +#: fr30-ibld.c:191 m32r-ibld.c:181 openrisc-ibld.c:181 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:702 m32r-ibld.c:631 openrisc-ibld.c:605 +#: fr30-ibld.c:739 m32r-ibld.c:656 openrisc-ibld.c:630 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:906 m32r-ibld.c:761 openrisc-ibld.c:704 +#: fr30-ibld.c:943 m32r-ibld.c:786 openrisc-ibld.c:731 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1050 m32r-ibld.c:866 openrisc-ibld.c:779 +#: fr30-ibld.c:1087 m32r-ibld.c:891 openrisc-ibld.c:806 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1179 m32r-ibld.c:956 openrisc-ibld.c:839 +#: fr30-ibld.c:1216 m32r-ibld.c:981 openrisc-ibld.c:866 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1308 m32r-ibld.c:1049 openrisc-ibld.c:903 +#: fr30-ibld.c:1345 m32r-ibld.c:1074 openrisc-ibld.c:930 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1430 m32r-ibld.c:1135 openrisc-ibld.c:960 +#: fr30-ibld.c:1467 m32r-ibld.c:1160 openrisc-ibld.c:987 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:380 +#: h8300-dis.c:384 #, c-format msgid "Hmmmm %x" msgstr "" -#: h8300-dis.c:391 +#: h8300-dis.c:395 #, c-format msgid "Don't understand %x \n" msgstr "" -#: h8500-dis.c:141 +#: h8500-dis.c:143 #, c-format msgid "can't cope with insert %d\n" msgstr "" #. Couldn't understand anything. -#: h8500-dis.c:348 +#: h8500-dis.c:350 #, c-format msgid "%02x\t\t*unknown*" msgstr "" @@ -198,61 +207,70 @@ msgstr "" msgid "unknown\t0x%04x" msgstr "" -#: m68k-dis.c:430 +#: m68k-dis.c:429 #, c-format msgid "<internal error in opcode table: %s %s>\n" msgstr "" -#: m68k-dis.c:1008 +#: m68k-dis.c:1007 #, c-format msgid "<function code %d>" msgstr "" -#: m88k-dis.c:274 +#: m88k-dis.c:255 #, c-format msgid "# <dis error: %08x>" msgstr "" -#: mips-dis.c:274 +#: mips-dis.c:292 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" +#: mips-dis.c:1129 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + #. I and Z are output operands and can`t be immediate #. * A is an address and we can`t have the address of #. * an immediate either. We don't know how much to increase #. * aoffsetp by since whatever generated this is broken #. * anyway! #. -#: ns32k-dis.c:619 +#: ns32k-dis.c:628 msgid "$<undefined>" msgstr "" -#: ppc-opc.c:620 ppc-opc.c:651 +#: ppc-opc.c:625 ppc-opc.c:656 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:653 +#: ppc-opc.c:658 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:708 +#: ppc-opc.c:688 +msgid "offset not a multiple of 4" +msgstr "" + +#: ppc-opc.c:715 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:743 ppc-opc.c:780 +#: ppc-opc.c:750 ppc-opc.c:787 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:849 +#: ppc-opc.c:856 msgid "value out of range" msgstr "" -#: ppc-opc.c:923 +#: ppc-opc.c:930 msgid "index register in load range" msgstr "" -#: ppc-opc.c:938 +#: ppc-opc.c:945 msgid "invalid register operand when updating" msgstr "" @@ -276,12 +294,12 @@ msgstr "" msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" -#: v850-dis.c:221 +#: v850-dis.c:224 #, c-format msgid "unknown operand shift: %x\n" msgstr "" -#: v850-dis.c:233 +#: v850-dis.c:236 #, c-format msgid "unknown pop reg: %d\n" msgstr "" @@ -291,46 +309,46 @@ msgstr "" #. v850_insert_operand() in gas/config/tc-v850.c. Error messages #. containing the string 'out of range' will be ignored unless a #. specific command line option is given to GAS. -#: v850-opc.c:46 +#: v850-opc.c:68 msgid "displacement value is not in range and is not aligned" msgstr "" -#: v850-opc.c:47 +#: v850-opc.c:69 msgid "displacement value is out of range" msgstr "" -#: v850-opc.c:48 +#: v850-opc.c:70 msgid "displacement value is not aligned" msgstr "" -#: v850-opc.c:50 +#: v850-opc.c:72 msgid "immediate value is out of range" msgstr "" -#: v850-opc.c:61 +#: v850-opc.c:83 msgid "branch value not in range and to odd offset" msgstr "" -#: v850-opc.c:63 v850-opc.c:95 +#: v850-opc.c:85 v850-opc.c:117 msgid "branch value out of range" msgstr "" -#: v850-opc.c:66 v850-opc.c:98 +#: v850-opc.c:88 v850-opc.c:120 msgid "branch to odd offset" msgstr "" -#: v850-opc.c:93 +#: v850-opc.c:115 msgid "branch value not in range and to an odd offset" msgstr "" -#: v850-opc.c:321 +#: v850-opc.c:346 msgid "invalid register for stack adjustment" msgstr "" -#: v850-opc.c:343 +#: v850-opc.c:370 msgid "immediate value not in range and not even" msgstr "" -#: v850-opc.c:348 +#: v850-opc.c:375 msgid "immediate value must be even" msgstr "" |