diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 18 | ||||
| -rw-r--r-- | opcodes/ppc-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 7 |
3 files changed, 26 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 43841f5..e5917d4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,21 @@ +2017-03-08 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; + <vsx>: Do not use PPC_OPCODE_VSX3; + +2017-03-08 Peter Bergner <bergner@vnet.ibm.com> + + Apply from master. + 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> + * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. + +2017-22-28 Peter Bergner <bergner@vnet.ibm.com> + + Apply from master. + 2017-02-10 Nicholas Piggin <npiggin@gmail.com> + + * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. + 2016-09-16 Peter Bergner <bergner@vnet.ibm.com> Apply from master. diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 77a2a60..e7a59b3 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -93,7 +93,7 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_A2), 0 }, { "altivec", PPC_OPCODE_PPC, - PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 }, + PPC_OPCODE_ALTIVEC }, { "any", 0, PPC_OPCODE_ANY }, { "booke", PPC_OPCODE_PPC | PPC_OPCODE_BOOKE, @@ -216,7 +216,7 @@ struct ppc_mopt ppc_opts[] = { | PPC_OPCODE_E500), PPC_OPCODE_VLE }, { "vsx", PPC_OPCODE_PPC, - PPC_OPCODE_VSX | PPC_OPCODE_VSX3 }, + PPC_OPCODE_VSX }, { "htm", PPC_OPCODE_PPC, PPC_OPCODE_HTM }, }; diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7003e0c..5926db0 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_operands[] = #define L1 L0 + 1 { 0x1, 21, insert_l1, extract_l1, 0 }, - /* The LEV field in a POWER SVC form instruction. */ + /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ #define SVC_LEV L1 + 1 { 0x7f, 5, NULL, NULL, 0 }, @@ -2487,6 +2487,8 @@ extract_vleil (unsigned long insn, /* An DX form instruction. */ #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) #define DX_MASK DX (0x3f, 0x1f) +/* An DX form instruction with the D bits specified. */ +#define NODX_MASK (DX_MASK | 0x1fffc1) /* An EVSEL form instruction. */ #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) @@ -4185,6 +4187,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, +{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, @@ -4197,6 +4200,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, +{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}}, {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}}, @@ -4434,6 +4438,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, +{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, |