diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/configure.in | 4 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 12 | ||||
| -rw-r--r-- | opcodes/m32c-asm.c | 510 | ||||
| -rw-r--r-- | opcodes/m32c-desc.c | 263 | ||||
| -rw-r--r-- | opcodes/m32c-desc.h | 437 | ||||
| -rw-r--r-- | opcodes/m32c-dis.c | 191 | ||||
| -rw-r--r-- | opcodes/m32c-ibld.c | 169 | ||||
| -rw-r--r-- | opcodes/m32c-opc.c | 186 | ||||
| -rw-r--r-- | opcodes/m32c-opc.h | 32 |
9 files changed, 783 insertions, 1021 deletions
diff --git a/opcodes/configure.in b/opcodes/configure.in index 41f8a13..6e22f80 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; bfd_fr30_arch) ta="$ta fr30-asm.lo fr30-desc.lo fr30-dis.lo fr30-ibld.lo fr30-opc.lo" using_cgen=yes ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; bfd_h8300_arch) ta="$ta h8300-dis.lo" ;; bfd_h8500_arch) ta="$ta h8500-dis.lo" ;; bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; @@ -176,6 +177,7 @@ if test x${all_targets} = xfalse ; then bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; + bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -230,8 +232,6 @@ if test x${all_targets} = xfalse ; then bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; - bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; - bfd_m32c_arch) ta="$ta m32c-asm.lo m32c-desc.lo m32c-dis.lo m32c-ibld.lo m32c-opc.lo" using_cgen=yes ;; "") ;; *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 997a359..377e64f 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -30,6 +30,8 @@ #define ARCH_d10v #define ARCH_d30v #define ARCH_dlx +#define ARCH_fr30 +#define ARCH_frv #define ARCH_h8300 #define ARCH_h8500 #define ARCH_hppa @@ -37,13 +39,14 @@ #define ARCH_i386 #define ARCH_i860 #define ARCH_i960 -#define ARCH_ip2k #define ARCH_ia64 -#define ARCH_fr30 +#define ARCH_ip2k +#define ARCH_iq2000 +#define ARCH_m32c #define ARCH_m32r -#define ARCH_m68k #define ARCH_m68hc11 #define ARCH_m68hc12 +#define ARCH_m68k #define ARCH_m88k #define ARCH_maxq #define ARCH_mcore @@ -73,9 +76,6 @@ #define ARCH_xstormy16 #define ARCH_xtensa #define ARCH_z8k -#define ARCH_frv -#define ARCH_iq2000 -#define ARCH_m32c #define INCLUDE_SHMEDIA #endif diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index 991d007..60c1055 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -1,26 +1,27 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-asm.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-asm.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -48,7 +49,7 @@ static const char * parse_insn_normal /* -- assembler routines inserted here. */ /* -- asm.c */ -#include <ctype.h> +#include "safe-ctype.h" #define MACH_M32C 5 /* Must match md_begin. */ @@ -76,25 +77,40 @@ m32c_cgen_isa_register (const char **strp) return 0; } +#define PARSE_UNSIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + +#define PARSE_SIGNED \ + do \ + { \ + /* Don't successfully parse literals beginning with '['. */ \ + if (**strp == '[') \ + return "Invalid literal"; /* Anything -- will not be seen. */ \ + \ + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \ + if (errmsg) \ + return errmsg; \ + } \ + while (0) + static const char * parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { const char *errmsg = 0; unsigned long value; - long have_zero = 0; - - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; + PARSE_UNSIGNED; if (value > 0x3f) return _("imm:6 immediate is out of range"); @@ -111,17 +127,11 @@ parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp, unsigned long value; long have_zero = 0; - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) have_zero = 1; - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; + PARSE_UNSIGNED; if (value > 0xff) return _("dsp:8 immediate is out of range"); @@ -141,18 +151,12 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp, const char *errmsg = 0; signed long value; long have_zero = 0; - - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) have_zero = 1; - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; + PARSE_SIGNED; if (value < -8 || value > 7) return _("Immediate is out of range -8 to 7"); @@ -172,13 +176,7 @@ parse_signed8 (CGEN_CPU_DESC cd, const char **strp, const char *errmsg = 0; signed long value; - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; + PARSE_SIGNED; if (value <= 255 && value > 127) value -= 0x100; @@ -198,13 +196,13 @@ parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, unsigned long value; long have_zero = 0; - /* Don't successfully parse literals beginning with '[' */ + /* Don't successfully parse literals beginning with '['. */ if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ - /* Don't successfully parse register names */ + /* Don't successfully parse register names. */ if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) @@ -234,14 +232,8 @@ parse_signed16 (CGEN_CPU_DESC cd, const char **strp, { const char *errmsg = 0; signed long value; - - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; + PARSE_SIGNED; if (value <= 65535 && value > 32767) value -= 0x10000; @@ -260,13 +252,13 @@ parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp, const char *errmsg = 0; unsigned long value; - /* Don't successfully parse literals beginning with '[' */ + /* Don't successfully parse literals beginning with '['. */ if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ - /* Don't successfully parse register names */ + /* Don't successfully parse register names. */ if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) @@ -286,13 +278,13 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, const char *errmsg = 0; unsigned long value; - /* Don't successfully parse literals beginning with '[' */ + /* Don't successfully parse literals beginning with '['. */ if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ - /* Don't successfully parse register names */ + /* Don't successfully parse register names. */ if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ + return "Invalid literal"; /* Anything -- will not be seen. */ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) @@ -307,21 +299,11 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, static const char * parse_signed32 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) + int opindex, signed long *valuep) { const char *errmsg = 0; signed long value; -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - - /* Don't successfully parse register names */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ -#endif - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; @@ -336,18 +318,8 @@ parse_imm1_S (CGEN_CPU_DESC cd, const char **strp, { const char *errmsg = 0; signed long value; - -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - /* Don't successfully parse register names */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ -#endif - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; @@ -365,17 +337,7 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, const char *errmsg = 0; signed long value; -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ - - /* Don't successfully parse register names */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* anything -- will not be seen */ -#endif - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; @@ -387,18 +349,48 @@ parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, } static const char * +parse_lab_5_3 (CGEN_CPU_DESC cd, + const char **strp, + int opindex ATTRIBUTE_UNUSED, + int opinfo, + enum cgen_parse_operand_result *type_addr, + unsigned long *valuep) +{ + const char *errmsg = 0; + unsigned long value; + enum cgen_parse_operand_result op_res; + + errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, + opinfo, & op_res, & value); + + if (type_addr) + *type_addr = op_res; + + if (op_res == CGEN_PARSE_OPERAND_ADDRESS) + { + /* This is a hack; the field cannot handle near-zero signed + offsets that CGEN wants to put in to indicate an "empty" + operand at first. */ + *valuep = 2; + return 0; + } + if (errmsg) + return errmsg; + + if (value < 2 || value > 9) + return _("immediate is out of range 2-9"); + + *valuep = value; + return 0; +} + +static const char * parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { const char *errmsg = 0; unsigned long value; -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ -#endif - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; @@ -421,12 +413,6 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, const char *newp = *strp; unsigned long long bitbase; -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ -#endif - errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); if (errmsg) return errmsg; @@ -439,7 +425,7 @@ parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, if (errmsg) return errmsg; - bitbase = (unsigned long long)bit + ((unsigned long long)base * 8); + bitbase = (unsigned long long) bit + ((unsigned long long) base * 8); if (bitbase >= (1ull << bits)) return _("bit,base is out of range"); @@ -461,12 +447,6 @@ parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp, long long bitbase; long long limit; -#if 0 - /* Don't successfully parse literals beginning with '[' */ - if (**strp == '[') - return "Invalid literal"; /* anything -- will not be seen */ -#endif - errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); if (errmsg) return errmsg; @@ -547,21 +527,22 @@ parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp, } /* Parse the suffix as :<char> or as nothing followed by a whitespace. */ + static const char * parse_suffix (const char **strp, char suffix) { const char *newp = *strp; - if (**strp == ':' && tolower (*(*strp + 1)) == suffix) + if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix) newp = *strp + 2; - if (isspace (*newp)) + if (ISSPACE (*newp)) { *strp = newp; return 0; } - return "Invalid suffix"; /* anything -- will not be seen */ + return "Invalid suffix"; /* Anything -- will not be seen. */ } static const char * @@ -593,6 +574,7 @@ parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, } /* Parse an empty suffix. Fail if the next char is ':'. */ + static const char * parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) @@ -611,16 +593,16 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, signed long junk; const char *newp = *strp; - /* Parse r0[hl] */ + /* Parse r0[hl]. */ errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value); if (errmsg) return errmsg; if (*newp != ',') - return "not a valid r0l/r0h pair"; + return _("not a valid r0l/r0h pair"); ++newp; - /* Parse the second register in the pair */ + /* Parse the second register in the pair. */ if (value == 0) /* r0l */ errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk); else @@ -633,7 +615,8 @@ parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, return 0; } -/* Accept .b or .w in any case */ +/* Accept .b or .w in any case. */ + static const char * parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) @@ -643,196 +626,14 @@ parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, || *(*strp + 1) == 'w' || *(*strp + 1) == 'W')) { *strp += 2; - return 0; + return NULL; } - return "Invalid size specifier"; + + return _("Invalid size specifier"); } -/* static const char * parse_abs (CGEN_CPU_DESC, const char **, int, */ -/* unsigned long *, unsigned long); */ -/* static const char * parse_abs16 (CGEN_CPU_DESC, const char **, int, */ -/* int ATTRIBUTE_UNUSED, */ -/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */ -/* unsigned long * ); */ -/* static const char * parse_abs24 (CGEN_CPU_DESC, const char **, int, */ -/* int ATTRIBUTE_UNUSED, */ -/* enum cgen_parse_operand_result * ATTRIBUTE_UNUSED, */ -/* unsigned long *); */ - -/* /\* Parse absolute *\/ */ - -/* static const char * */ -/* parse_abs16 (CGEN_CPU_DESC cd, const char **strp, int opindex, */ -/* int reloc ATTRIBUTE_UNUSED, */ -/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */ -/* unsigned long *valuep) */ -/* { */ -/* return parse_abs (cd, strp, opindex, valuep, 16); */ -/* } */ - -/* static const char * */ -/* parse_abs24 (CGEN_CPU_DESC cd, const char **strp, int opindex, */ -/* int reloc ATTRIBUTE_UNUSED, */ -/* enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, */ -/* unsigned long *valuep) */ -/* { */ -/* return parse_abs (cd, strp, opindex, valuep, 24); */ -/* } */ - -/* static const char * */ -/* parse_abs (CGEN_CPU_DESC cd, const char **strp, int opindex, */ -/* unsigned long *valuep, */ -/* unsigned long length) */ -/* { */ -/* const char *errmsg = 0; */ -/* const char *op; */ -/* int has_register = 0; */ - -/* for (op = *strp; *op != '\0'; op++) */ -/* { */ -/* if (*op == '[') */ -/* { */ -/* has_register = 1; */ -/* break; */ -/* } */ -/* else if (*op == ',') */ -/* break; */ -/* } */ - -/* if (has_register || m32c_cgen_isa_register (strp)) */ -/* errmsg = _("immediate value cannot be register"); */ -/* else */ -/* { */ -/* enum cgen_parse_operand_result result_type; */ -/* bfd_vma value; */ -/* const char *errmsg; */ - -/* errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, */ -/* &result_type, &value); */ -/* *valuep = value; */ -/* } */ -/* return errmsg; */ -/* } */ -/* /\* Handle signed/unsigned literal. *\/ */ - -/* static const char * */ -/* parse_imm8 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg = 0; */ -/* long value; */ -/* long have_zero = 0; */ - -/* if (strncmp (*strp, "0x0", 3) == 0 */ -/* || (**strp == '0' && *(*strp + 1) != 'x')) */ -/* have_zero = 1; */ -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* *valuep = value; */ -/* /\* If this field may require a relocation then use larger dsp16. *\/ */ -/* if (! have_zero && value == 0) */ -/* errmsg = _("immediate value may not fit in dsp8 field"); */ - -/* return errmsg; */ -/* } */ - -/* static const char * */ -/* parse_imm16 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg; */ -/* long value; */ - -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* *valuep = value; */ -/* return errmsg; */ -/* } */ - -/* static const char * */ -/* parse_imm24 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg; */ -/* long value; */ - -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* *valuep = value; */ -/* return errmsg; */ -/* } */ - -/* static const char * */ -/* parse_imm32 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg; */ -/* long value; */ - -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* *valuep = value; */ -/* return errmsg; */ -/* } */ - -/* /\* Handle bitfields. *\/ */ - -/* static const char * */ -/* parse_boff8 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg; */ -/* long bit_value, value; */ - -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */ -/* if (errmsg == 0) */ -/* { */ -/* *strp = *strp + 1; */ -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* } */ -/* value = value * 8 + bit_value; */ -/* *valuep = value; */ -/* if (value > 0x100) */ -/* errmsg = _("Operand out of range. Must be between 0 and 255."); */ -/* return errmsg; */ -/* } */ - -/* static const char * */ -/* parse_boff16 (cd, strp, opindex, valuep) */ -/* CGEN_CPU_DESC cd; */ -/* const char **strp; */ -/* int opindex; */ -/* unsigned long *valuep; */ -/* { */ -/* const char *errmsg; */ -/* long bit_value, value; */ - -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & bit_value); */ -/* if (errmsg == 0) */ -/* { */ -/* *strp = *strp + 1; */ -/* errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); */ -/* } */ -/* value = value * 8 + bit_value; */ -/* *valuep = value; */ -/* if (value > 0x1000) */ -/* errmsg = _("Operand out of range. Must be between 0 and 65535."); */ -/* return errmsg; */ -/* } */ - - -/* Special check to ensure that instruction exists for given machine */ +/* Special check to ensure that instruction exists for given machine. */ + int m32c_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) @@ -840,7 +641,7 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd, int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA); - /* If attributes are absent, assume no restriction. */ + /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; @@ -855,8 +656,7 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, int opindex ATTRIBUTE_UNUSED, unsigned long *valuep, - int push - ) + int push) { const char *errmsg = 0; int regno = 0; @@ -912,23 +712,23 @@ parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, return errmsg; } -#define POP 0 +#define POP 0 #define PUSH 1 static const char * parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep) + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) { return parse_regset (cd, strp, opindex, valuep, POP); } static const char * parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep) + const char **strp, + int opindex ATTRIBUTE_UNUSED, + unsigned long *valuep) { return parse_regset (cd, strp, opindex, valuep, PUSH); } @@ -936,7 +736,7 @@ parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, /* -- dis.c */ const char * m32c_cgen_parse_operand - PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); /* Main entry point for operand parsing. @@ -952,11 +752,10 @@ const char * m32c_cgen_parse_operand the handlers. */ const char * -m32c_cgen_parse_operand (cd, opindex, strp, fields) - CGEN_CPU_DESC cd; - int opindex; - const char ** strp; - CGEN_FIELDS * fields; +m32c_cgen_parse_operand (CGEN_CPU_DESC cd, + int opindex, + const char ** strp, + CGEN_FIELDS * fields) { const char * errmsg = NULL; /* Used by scalar operands that still need to be parsed. */ @@ -992,7 +791,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_gr_QI, & fields->f_dst32_rn_unprefixed_QI); break; case M32C_OPERAND_BITBASE16_16_S8 : - errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (unsigned long *) (& fields->f_dsp_16_s8)); + errmsg = parse_signed_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_S8, (long *) (& fields->f_dsp_16_s8)); break; case M32C_OPERAND_BITBASE16_16_U16 : errmsg = parse_unsigned_bitbase16 (cd, strp, M32C_OPERAND_BITBASE16_16_U16, (unsigned long *) (& fields->f_dsp_16_u16)); @@ -1001,7 +800,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) errmsg = parse_unsigned_bitbase8 (cd, strp, M32C_OPERAND_BITBASE16_16_U8, (unsigned long *) (& fields->f_dsp_16_u8)); break; case M32C_OPERAND_BITBASE16_8_U11_S : - errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (long *) (& fields->f_bitbase16_u11_S)); + errmsg = parse_unsigned_bitbase11 (cd, strp, M32C_OPERAND_BITBASE16_8_U11_S, (unsigned long *) (& fields->f_bitbase16_u11_S)); break; case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : errmsg = parse_signed_bitbase11 (cd, strp, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, (long *) (& fields->f_bitbase32_16_s11_unprefixed)); @@ -1100,10 +899,10 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_32_U8, (unsigned long *) (& fields->f_dsp_32_u8)); break; case M32C_OPERAND_DSP_40_S16 : - errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (unsigned long *) (& fields->f_dsp_40_s16)); + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_40_S16, (long *) (& fields->f_dsp_40_s16)); break; case M32C_OPERAND_DSP_40_S8 : - errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (unsigned long *) (& fields->f_dsp_40_s8)); + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_40_S8, (long *) (& fields->f_dsp_40_s8)); break; case M32C_OPERAND_DSP_40_U16 : errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_40_U16, (unsigned long *) (& fields->f_dsp_40_u16)); @@ -1115,10 +914,10 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) errmsg = parse_unsigned8 (cd, strp, M32C_OPERAND_DSP_40_U8, (unsigned long *) (& fields->f_dsp_40_u8)); break; case M32C_OPERAND_DSP_48_S16 : - errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (unsigned long *) (& fields->f_dsp_48_s16)); + errmsg = parse_signed16 (cd, strp, M32C_OPERAND_DSP_48_S16, (long *) (& fields->f_dsp_48_s16)); break; case M32C_OPERAND_DSP_48_S8 : - errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (unsigned long *) (& fields->f_dsp_48_s8)); + errmsg = parse_signed8 (cd, strp, M32C_OPERAND_DSP_48_S8, (long *) (& fields->f_dsp_48_s8)); break; case M32C_OPERAND_DSP_48_U16 : errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_48_U16, (unsigned long *) (& fields->f_dsp_48_u16)); @@ -1135,6 +934,9 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) case M32C_OPERAND_DSP_8_U16 : errmsg = parse_unsigned16 (cd, strp, M32C_OPERAND_DSP_8_U16, (unsigned long *) (& fields->f_dsp_8_u16)); break; + case M32C_OPERAND_DSP_8_U24 : + errmsg = parse_unsigned24 (cd, strp, M32C_OPERAND_DSP_8_U24, (unsigned long *) (& fields->f_dsp_8_u24)); + break; case M32C_OPERAND_DSP_8_U6 : errmsg = parse_unsigned6 (cd, strp, M32C_OPERAND_DSP_8_U6, (unsigned long *) (& fields->f_dsp_8_u6)); break; @@ -1238,7 +1040,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4)); break; case M32C_OPERAND_IMM_13_U3 : - errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (unsigned long *) (& fields->f_imm_13_u3)); + errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3)); break; case M32C_OPERAND_IMM_16_HI : errmsg = parse_signed16 (cd, strp, M32C_OPERAND_IMM_16_HI, (long *) (& fields->f_dsp_16_s16)); @@ -1352,7 +1154,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) case M32C_OPERAND_LAB_5_3 : { bfd_vma value = 0; - errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value); + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB_5_3, 0, NULL, & value); fields->f_lab_5_3 = value; } break; @@ -1380,7 +1182,7 @@ m32c_cgen_parse_operand (cd, opindex, strp, fields) case M32C_OPERAND_LAB32_JMP_S : { bfd_vma value = 0; - errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value); + errmsg = parse_lab_5_3 (cd, strp, M32C_OPERAND_LAB32_JMP_S, 0, NULL, & value); fields->f_lab32_jmp_s = value; } break; @@ -1574,8 +1376,7 @@ cgen_parse_fn * const m32c_cgen_parse_handlers[] = }; void -m32c_cgen_init_asm (cd) - CGEN_CPU_DESC cd; +m32c_cgen_init_asm (CGEN_CPU_DESC cd) { m32c_cgen_init_opcode_table (cd); m32c_cgen_init_ibld_table (cd); @@ -1958,30 +1759,3 @@ m32c_cgen_assemble_insn (CGEN_CPU_DESC cd, return NULL; } } - -#if 0 /* This calls back to GAS which we can't do without care. */ - -/* Record each member of OPVALS in the assembler's symbol table. - This lets GAS parse registers for us. - ??? Interesting idea but not currently used. */ - -/* Record each member of OPVALS in the assembler's symbol table. - FIXME: Not currently used. */ - -void -m32c_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) -{ - CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); - const CGEN_KEYWORD_ENTRY * ke; - - while ((ke = cgen_keyword_search_next (& search)) != NULL) - { -#if 0 /* Unnecessary, should be done in the search routine. */ - if (! m32c_cgen_opval_supported (ke)) - continue; -#endif - cgen_asm_record_register (cd, ke->name, ke->value); - } -} - -#endif /* 0 */ diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c index e721d35..a86c086 100644 --- a/opcodes/m32c-desc.c +++ b/opcodes/m32c-desc.c @@ -824,6 +824,7 @@ const CGEN_IFLD m32c_cgen_ifld_table[] = { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, @@ -833,6 +834,8 @@ const CGEN_IFLD m32c_cgen_ifld_table[] = { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } }, { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } }, @@ -895,6 +898,7 @@ const CGEN_IFLD m32c_cgen_ifld_table[] = { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, @@ -1466,6 +1470,10 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, +/* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */ + { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24, + { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } }, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */ { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } }, @@ -1547,7 +1555,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */ - { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_UINT, 8, 8, + { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */ @@ -1555,7 +1563,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */ - { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_UINT, 8, 16, + { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */ @@ -1567,7 +1575,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */ - { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_UINT, 16, 8, + { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */ @@ -1575,7 +1583,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */ - { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_UINT, 16, 16, + { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */ @@ -1607,7 +1615,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */ - { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_UINT, 13, 3, + { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */ @@ -1715,7 +1723,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */ - { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_UINT, 16, 8, + { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */ @@ -1723,7 +1731,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } }, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */ - { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_SINT, 5, 11, + { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11, { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } }, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */ @@ -1769,19 +1777,19 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = /* Lab-5-3: 3 bit label */ { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab32-jmp-s: 3 bit label */ { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3, { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } }, - { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-8: 8 bit label */ { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-16: 16 bit label */ { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } }, - { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-8-24: 24 bit label */ { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } }, @@ -1789,7 +1797,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] = /* Lab-16-8: 8 bit label */ { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } }, - { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, + { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } }, /* Lab-24-8: 8 bit label */ { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8, { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } }, @@ -29584,71 +29592,6 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, -/* mov.b${S} #${Imm-8-QI},r0l */ - { - M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } - }, -/* mov.b${S} #${Imm-8-QI},r0h */ - { - M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ - { - M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ - { - M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ - { - M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } - }, -/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ - { - M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ - { - M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ - { - M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.w${S} #${Imm-8-HI},r0 */ - { - M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ - { - M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ - { - M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ - { - M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, -/* mov.b${S} #${Imm-8-QI},r0l */ - { - M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16, - { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } - }, /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16, @@ -29859,6 +29802,71 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, +/* mov.b${S} #${Imm-8-QI},r0h */ + { + M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32, + { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.w${S} #${Imm-8-HI},r0 */ + { + M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16, + { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } + }, /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48, @@ -61737,32 +61745,32 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* j$cond16j5 ${Lab-8-8} */ { M32C_INSN_JCND16_5, "jcnd16-5", "j", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* j$cond16j ${Lab-16-8} */ { M32C_INSN_JCND16, "jcnd16", "j", 24, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* j$cond32j ${Lab-8-8} */ { M32C_INSN_JCND32, "jcnd32", "j", 16, - { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* jmp.s ${Lab-5-3} */ { M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* jmp.b ${Lab-8-8} */ { M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* jmp.w ${Lab-8-16} */ { M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* jmp.a ${Lab-8-24} */ { @@ -61777,17 +61785,17 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* jmp.s ${Lab32-jmp-s} */ { M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* jmp.b ${Lab-8-8} */ { M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* jmp.w ${Lab-8-16} */ { M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* jmp.a ${Lab-8-24} */ { @@ -61802,7 +61810,7 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* jsr.w ${Lab-8-16} */ { M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } } }, /* jsr.a ${Lab-8-24} */ { @@ -61812,7 +61820,7 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = /* jsr.w ${Lab-8-16} */ { M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } + { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } } }, /* jsr.a ${Lab-8-24} */ { @@ -61909,12 +61917,12 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, -/* mov.l$S #${Dsp-16-u24},a0 */ +/* mov.l$S #${Dsp-8-u24},a0 */ { M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } }, -/* mov.l$S #${Dsp-16-u24},a1 */ +/* mov.l$S #${Dsp-8-u24},a1 */ { M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32, { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } @@ -62265,27 +62273,23 @@ static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] = #undef A /* Initialize anything needed to be done once, before any cpu_open call. */ -static void init_tables PARAMS ((void)); static void -init_tables () +init_tables (void) { } -static const CGEN_MACH * lookup_mach_via_bfd_name - PARAMS ((const CGEN_MACH *, const char *)); -static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); -static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); -static void m32c_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); +static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); +static void build_hw_table (CGEN_CPU_TABLE *); +static void build_ifield_table (CGEN_CPU_TABLE *); +static void build_operand_table (CGEN_CPU_TABLE *); +static void build_insn_table (CGEN_CPU_TABLE *); +static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *); /* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */ static const CGEN_MACH * -lookup_mach_via_bfd_name (table, name) - const CGEN_MACH *table; - const char *name; +lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) { while (table->name) { @@ -62299,8 +62303,7 @@ lookup_mach_via_bfd_name (table, name) /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ static void -build_hw_table (cd) - CGEN_CPU_TABLE *cd; +build_hw_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -62326,8 +62329,7 @@ build_hw_table (cd) /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ static void -build_ifield_table (cd) - CGEN_CPU_TABLE *cd; +build_ifield_table (CGEN_CPU_TABLE *cd) { cd->ifld_table = & m32c_cgen_ifld_table[0]; } @@ -62335,8 +62337,7 @@ build_ifield_table (cd) /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */ static void -build_operand_table (cd) - CGEN_CPU_TABLE *cd; +build_operand_table (CGEN_CPU_TABLE *cd) { int i; int machs = cd->machs; @@ -62344,8 +62345,7 @@ build_operand_table (cd) /* MAX_OPERANDS is only an upper bound on the number of selected entries. However each entry is indexed by it's enum so there can be holes in the table. */ - const CGEN_OPERAND **selected = - (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); cd->operand_table.init_entries = init; cd->operand_table.entry_size = sizeof (CGEN_OPERAND); @@ -62368,12 +62368,11 @@ build_operand_table (cd) operand elements to be in the table [which they mightn't be]. */ static void -build_insn_table (cd) - CGEN_CPU_TABLE *cd; +build_insn_table (CGEN_CPU_TABLE *cd) { int i; const CGEN_IBASE *ib = & m32c_cgen_insn_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); for (i = 0; i < MAX_INSNS; ++i) @@ -62386,8 +62385,7 @@ build_insn_table (cd) /* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */ static void -m32c_cgen_rebuild_tables (cd) - CGEN_CPU_TABLE *cd; +m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) { int i; unsigned int isas = cd->isas; @@ -62399,7 +62397,7 @@ m32c_cgen_rebuild_tables (cd) #define UNSET (CGEN_SIZE_UNKNOWN + 1) cd->default_insn_bitsize = UNSET; cd->base_insn_bitsize = UNSET; - cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ cd->max_insn_bitsize = 0; for (i = 0; i < MAX_ISAS; ++i) if (((1 << i) & isas) != 0) @@ -62411,7 +62409,7 @@ m32c_cgen_rebuild_tables (cd) if (cd->default_insn_bitsize == UNSET) cd->default_insn_bitsize = isa->default_insn_bitsize; else if (isa->default_insn_bitsize == cd->default_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -62420,7 +62418,7 @@ m32c_cgen_rebuild_tables (cd) if (cd->base_insn_bitsize == UNSET) cd->base_insn_bitsize = isa->base_insn_bitsize; else if (isa->base_insn_bitsize == cd->base_insn_bitsize) - ; /* this is ok */ + ; /* This is ok. */ else cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; @@ -62532,12 +62530,12 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) } va_end (ap); - /* mach unspecified means "all" */ + /* Mach unspecified means "all". */ if (machs == 0) machs = (1 << MAX_MACHS) - 1; - /* base mach is always selected */ + /* Base mach is always selected. */ machs |= 1; - /* isa unspecified means "all" */ + /* ISA unspecified means "all". */ if (isas == 0) isas = (1 << MAX_ISAS) - 1; if (endian == CGEN_ENDIAN_UNKNOWN) @@ -62570,9 +62568,7 @@ m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) MACH_NAME is the bfd name of the mach. */ CGEN_CPU_DESC -m32c_cgen_cpu_open_1 (mach_name, endian) - const char *mach_name; - enum cgen_endian endian; +m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) { return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, CGEN_CPU_OPEN_ENDIAN, endian, @@ -62585,8 +62581,7 @@ m32c_cgen_cpu_open_1 (mach_name, endian) place as some simulator ports use this but they don't use libopcodes. */ void -m32c_cgen_cpu_close (cd) - CGEN_CPU_DESC cd; +m32c_cgen_cpu_close (CGEN_CPU_DESC cd) { unsigned int i; const CGEN_INSN *insns; @@ -62595,23 +62590,17 @@ m32c_cgen_cpu_close (cd) { insns = cd->macro_insn_table.init_entries; for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX ((insns))) - regfree (CGEN_INSN_RX (insns)); - } + if (CGEN_INSN_RX ((insns))) + regfree (CGEN_INSN_RX (insns)); } if (cd->insn_table.init_entries) { insns = cd->insn_table.init_entries; for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) - { - if (CGEN_INSN_RX (insns)) - regfree (CGEN_INSN_RX (insns)); - } - } - - + if (CGEN_INSN_RX (insns)) + regfree (CGEN_INSN_RX (insns)); + } if (cd->macro_insn_table.init_entries) free ((CGEN_INSN *) cd->macro_insn_table.init_entries); diff --git a/opcodes/m32c-desc.h b/opcodes/m32c-desc.h index 277c90b..ef27541 100644 --- a/opcodes/m32c-desc.h +++ b/opcodes/m32c-desc.h @@ -104,24 +104,25 @@ typedef enum ifield_type { , M32C_F_11_1, M32C_F_12_1, M32C_F_12_2, M32C_F_12_3 , M32C_F_12_4, M32C_F_12_6, M32C_F_13_3, M32C_F_14_1 , M32C_F_14_2, M32C_F_15_1, M32C_F_16_1, M32C_F_16_2 - , M32C_F_16_4, M32C_F_18_1, M32C_F_18_2, M32C_F_18_3 - , M32C_F_20_1, M32C_F_20_3, M32C_F_20_2, M32C_F_20_4 - , M32C_F_21_3, M32C_F_24_2, M32C_F_SRC16_RN, M32C_F_SRC16_AN - , M32C_F_SRC32_AN_UNPREFIXED, M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI - , M32C_F_SRC32_RN_UNPREFIXED_HI, M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI - , M32C_F_DST32_RN_EXT_UNPREFIXED, M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S - , M32C_F_DST16_AN, M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED - , M32C_F_DST32_RN_UNPREFIXED_QI, M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI - , M32C_F_DST32_RN_UNPREFIXED_SI, M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4 - , M32C_F_IMM_12_S4, M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S - , M32C_F_IMM3_S, M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8 - , M32C_F_DSP_10_U6, M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8 - , M32C_F_DSP_24_S8, M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8 - , M32C_F_DSP_40_S8, M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8 - , M32C_F_DSP_56_S8, M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16 - , M32C_F_DSP_8_S16, M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16 - , M32C_F_DSP_24_S16, M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16 - , M32C_F_DSP_40_S16, M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16 + , M32C_F_16_4, M32C_F_16_8, M32C_F_18_1, M32C_F_18_2 + , M32C_F_18_3, M32C_F_20_1, M32C_F_20_3, M32C_F_20_2 + , M32C_F_20_4, M32C_F_21_3, M32C_F_24_2, M32C_F_24_8 + , M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN, M32C_F_SRC32_AN_UNPREFIXED + , M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI, M32C_F_SRC32_RN_UNPREFIXED_HI + , M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI, M32C_F_DST32_RN_EXT_UNPREFIXED + , M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S, M32C_F_DST16_AN + , M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED, M32C_F_DST32_RN_UNPREFIXED_QI + , M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI, M32C_F_DST32_RN_UNPREFIXED_SI + , M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4, M32C_F_IMM_12_S4 + , M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S, M32C_F_IMM3_S + , M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8, M32C_F_DSP_10_U6 + , M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8, M32C_F_DSP_24_S8 + , M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8, M32C_F_DSP_40_S8 + , M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8, M32C_F_DSP_56_S8 + , M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16, M32C_F_DSP_8_S16 + , M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16, M32C_F_DSP_24_S16 + , M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16, M32C_F_DSP_40_S16 + , M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16, M32C_F_DSP_8_U24 , M32C_F_DSP_16_U24, M32C_F_DSP_24_U24, M32C_F_DSP_32_U24, M32C_F_DSP_40_U24 , M32C_F_DSP_40_S32, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32 , M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16 @@ -208,209 +209,209 @@ typedef enum cgen_operand_type { , M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB , M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP , M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6 - , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_10_U6 - , M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24 - , M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16 - , M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16 - , M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20 - , M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8 - , M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8 - , M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U24 - , M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI, M32C_OPERAND_IMM_8_HI - , M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4 - , M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI - , M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI - , M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI - , M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI - , M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S - , M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED - , M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S - , M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED - , M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED - , M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S - , M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8 - , M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT - , M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT - , M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16 - , M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24 - , M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J - , M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32 - , M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32 - , M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32 - , M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G - , M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX - , M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI - , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI - , M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI - , M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI - , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI - , M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI - , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI - , M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI - , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI - , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI - , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI - , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI - , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI - , M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI - , M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI - , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI - , M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI - , M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI - , M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI - , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI - , M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI, M32C_OPERAND_DST16_RN_DIRECT_SI - , M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI - , M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI - , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI, M32C_OPERAND_DST16_AN_DIRECT_HI - , M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI - , M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_DST16_AN_INDIRECT_QI - , M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI - , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI - , M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI - , M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI - , M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI - , M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI - , M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI - , M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI - , M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI - , M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI - , M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI - , M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI - , M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI - , M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI - , M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI - , M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI - , M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI - , M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI - , M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI - , M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI - , M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI - , M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI - , M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI - , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI - , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI - , M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI - , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI - , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI - , M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI - , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI - , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI - , M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI - , M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI - , M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI - , M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI - , M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI - , M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI - , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI - , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI - , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI - , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI - , M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI - , M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI - , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI - , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI - , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI - , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI - , M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI - , M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI - , M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED - , M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT - , M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE - , M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED - , M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED - , M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED - , M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED - , M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED - , M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED - , M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI - , M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI - , M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI - , M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI - , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI - , M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI - , M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI - , M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI - , M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI - , M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI - , M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI - , M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI - , M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI - , M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI - , M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI - , M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI - , M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI - , M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI - , M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI - , M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI - , M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI - , M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI - , M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI - , M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI - , M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI - , M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_UNPREFIXED_SI - , M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI, M32C_OPERAND_DST16_24_QI - , M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI, M32C_OPERAND_DST32_24_8_PREFIXED_QI - , M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI, M32C_OPERAND_DST32_24_PREFIXED_HI - , M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI, M32C_OPERAND_DST32_24_UNPREFIXED_SI - , M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI, M32C_OPERAND_DST32_24_24_PREFIXED_SI - , M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI, M32C_OPERAND_DST32_32_PREFIXED_QI - , M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI, M32C_OPERAND_DST32_32_PREFIXED_SI - , M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI, M32C_OPERAND_DST32_40_PREFIXED_HI - , M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI, M32C_OPERAND_DST32_48_PREFIXED_HI - , M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC, M32C_OPERAND_BIT16_16_8 - , M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED, M32C_OPERAND_BIT32_BASIC_UNPREFIXED - , M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED, M32C_OPERAND_SRC16_2_S - , M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8, M32C_OPERAND_DST16_3_S_16 - , M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI, M32C_OPERAND_DST32_2_S_8_QI - , M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI, M32C_OPERAND_DST32_2_S_8_SI - , M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S, M32C_OPERAND_RN16_PUSH_S_ANYOF - , M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX + , M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_U24 + , M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16, M32C_OPERAND_DSP_16_U20 + , M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16, M32C_OPERAND_DSP_24_U8 + , M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24, M32C_OPERAND_DSP_24_S8 + , M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16, M32C_OPERAND_DSP_32_U24 + , M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16, M32C_OPERAND_DSP_40_U8 + , M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16, M32C_OPERAND_DSP_40_U24 + , M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8, M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16 + , M32C_OPERAND_DSP_48_U24, M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI + , M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_SH_12_S4, M32C_OPERAND_IMM_13_U3 + , M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI, M32C_OPERAND_IMM_16_HI + , M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI, M32C_OPERAND_IMM_24_SI + , M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI, M32C_OPERAND_IMM_40_QI + , M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI, M32C_OPERAND_IMM_48_HI + , M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI, M32C_OPERAND_IMM_64_HI + , M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED + , M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8, M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16 + , M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED + , M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED + , M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED, M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3 + , M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8, M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24 + , M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8, M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8 + , M32C_OPERAND_SBIT, M32C_OPERAND_OBIT, M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT + , M32C_OPERAND_UBIT, M32C_OPERAND_IBIT, M32C_OPERAND_BBIT, M32C_OPERAND_DBIT + , M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24, M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16 + , M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32, M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C + , M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5, M32C_OPERAND_COND32, M32C_OPERAND_COND32J + , M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16, M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16 + , M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32, M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32 + , M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z, M32C_OPERAND_S, M32C_OPERAND_Q + , M32C_OPERAND_G, M32C_OPERAND_X, M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX + , M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX, M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI + , M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI + , M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI + , M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI + , M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI + , M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI + , M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI + , M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI + , M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI + , M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI + , M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI + , M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI + , M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI + , M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI + , M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI + , M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI + , M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI + , M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI + , M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI + , M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI + , M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI + , M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI + , M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI + , M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI + , M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI + , M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI + , M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI + , M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI + , M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI + , M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI + , M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI + , M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI + , M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI + , M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI + , M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI + , M32C_OPERAND_DST16_32_16_ABSOLUTE_QI, M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI + , M32C_OPERAND_DST16_24_16_ABSOLUTE_HI, M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI + , M32C_OPERAND_DST16_16_16_ABSOLUTE_SI, M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI + , M32C_OPERAND_DST16_48_16_ABSOLUTE_SI, M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI + , M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI + , M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI + , M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED + , M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED + , M32C_OPERAND_BIT16_AN_INDIRECT, M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE + , M32C_OPERAND_BIT16_16_16_SB_RELATIVE, M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE + , M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED + , M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED + , M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED + , M32C_OPERAND_AN16_PUSH_S_DERIVED, M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED + , M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED, M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI + , M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI + , M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI + , M32C_OPERAND_DST32_2_S_R0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI + , M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI + , M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI + , M32C_OPERAND_SRC16_BASIC_QI, M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI + , M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI, M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI + , M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI, M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI + , M32C_OPERAND_SRC16_16_16_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI + , M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI + , M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI + , M32C_OPERAND_SRC32_24_24_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI + , M32C_OPERAND_SRC32_24_8_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI + , M32C_OPERAND_DST16_BASIC_HI, M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI + , M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI, M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI + , M32C_OPERAND_DST16_16_QI, M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_HI + , M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI + , M32C_OPERAND_DST16_16_16_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI + , M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI + , M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI + , M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_UNPREFIXED_QI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI + , M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI + , M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI + , M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI + , M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI + , M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI + , M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI + , M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI + , M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI + , M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI + , M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC + , M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED + , M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED + , M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8 + , M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI + , M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI + , M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S + , M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 869 +#define MAX_OPERANDS 870 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index c81a893..b2ddb16 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -1,27 +1,27 @@ /* Disassembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -THIS FILE IS MACHINE GENERATED WITH CGEN. -- the resultant file is machine generated, cgen-dis.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN. + - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 -Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -56,24 +56,26 @@ static int read_insn (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, unsigned long *); -/* -- disassembler routines inserted here */ +/* -- disassembler routines inserted here. */ /* -- dis.c */ #include "elf/m32c.h" #include "elf-bfd.h" -/* Always print the short insn format suffix as ':<char>' */ +/* Always print the short insn format suffix as ':<char>'. */ + static void -print_suffix (PTR dis_info, char suffix) +print_suffix (void * dis_info, char suffix) { disassemble_info *info = dis_info; + (*info->fprintf_func) (info->stream, ":%c", suffix); } static void print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, @@ -85,7 +87,7 @@ print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, @@ -96,7 +98,7 @@ print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, @@ -107,7 +109,7 @@ print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, @@ -116,10 +118,11 @@ print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, print_suffix (dis_info, 'z'); } -/* Print the empty suffix */ +/* Print the empty suffix. */ + static void print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info ATTRIBUTE_UNUSED, + void * dis_info ATTRIBUTE_UNUSED, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, @@ -130,13 +133,14 @@ print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = dis_info; + if (value == 0) (*info->fprintf_func) (info->stream, "r0h,r0l"); else @@ -145,62 +149,65 @@ print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, unsigned long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = dis_info; + (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); } static void print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, signed long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = dis_info; + (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); } static void print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, + void * dis_info, long value ATTRIBUTE_UNUSED, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { - /* Always print the size as '.w' */ + /* Always print the size as '.w'. */ disassemble_info *info = dis_info; + (*info->fprintf_func) (info->stream, ".w"); } -#define POP 0 +#define POP 0 #define PUSH 1 -static void print_pop_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int); -static void print_push_regset (CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int); +static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); +static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); /* Print a set of registers, R0,R1,A0,A1,SB,FB. */ static void print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED, - int push) + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED, + int push) { static char * m16c_register_names [] = - { - "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" - }; + { + "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" + }; disassemble_info *info = dis_info; int mask; int index = 0; @@ -235,45 +242,28 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, static void print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { print_regset (cd, dis_info, value, attrs, pc, length, POP); } static void print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) + void * dis_info, + long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { print_regset (cd, dis_info, value, attrs, pc, length, PUSH); } -#if 0 /* not used? */ -static void -print_boff (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - PTR dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = dis_info; - if (value) - info->fprintf_func (info->stream, "%d,%d", value % 16, - (value / 16) * 2); -} - -#endif /* not used? */ void m32c_cgen_print_operand - PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, - void const *, bfd_vma, int)); + (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); /* Main entry point for printing operands. XINFO is a `void *' and not a `disassemble_info *' to not put a requirement @@ -291,16 +281,15 @@ void m32c_cgen_print_operand the handlers. */ void -m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) - CGEN_CPU_DESC cd; - int opindex; - PTR xinfo; - CGEN_FIELDS *fields; - void const *attrs ATTRIBUTE_UNUSED; - bfd_vma pc; - int length; +m32c_cgen_print_operand (CGEN_CPU_DESC cd, + int opindex, + void * xinfo, + CGEN_FIELDS *fields, + void const *attrs ATTRIBUTE_UNUSED, + bfd_vma pc, + int length) { - disassemble_info *info = (disassemble_info *) xinfo; + disassemble_info *info = (disassemble_info *) xinfo; switch (opindex) { @@ -332,7 +321,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); break; case M32C_OPERAND_BITBASE16_16_S8 : - print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0, pc, length); + print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_BITBASE16_16_U16 : print_unsigned_bitbase (cd, info, fields->f_dsp_16_u16, 0, pc, length); @@ -341,7 +330,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length); break; case M32C_OPERAND_BITBASE16_8_U11_S : - print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); break; case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : print_signed_bitbase (cd, info, fields->f_bitbase32_16_s11_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); @@ -440,10 +429,10 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length); break; case M32C_OPERAND_DSP_40_S16 : - print_normal (cd, info, fields->f_dsp_40_s16, 0, pc, length); + print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_DSP_40_S8 : - print_normal (cd, info, fields->f_dsp_40_s8, 0, pc, length); + print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_DSP_40_U16 : print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length); @@ -455,10 +444,10 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length); break; case M32C_OPERAND_DSP_48_S16 : - print_normal (cd, info, fields->f_dsp_48_s16, 0, pc, length); + print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_DSP_48_S8 : - print_normal (cd, info, fields->f_dsp_48_s8, 0, pc, length); + print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_DSP_48_U16 : print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length); @@ -475,6 +464,9 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) case M32C_OPERAND_DSP_8_U16 : print_normal (cd, info, fields->f_dsp_8_u16, 0, pc, length); break; + case M32C_OPERAND_DSP_8_U24 : + print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length); + break; case M32C_OPERAND_DSP_8_U6 : print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length); break; @@ -578,7 +570,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_IMM_13_U3 : - print_normal (cd, info, fields->f_imm_13_u3, 0, pc, length); + print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32C_OPERAND_IMM_16_HI : print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); @@ -662,7 +654,7 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); break; case M32C_OPERAND_LAB_16_8 : - print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); break; case M32C_OPERAND_LAB_24_8 : print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); @@ -674,19 +666,19 @@ m32c_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); break; case M32C_OPERAND_LAB_5_3 : - print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); break; case M32C_OPERAND_LAB_8_16 : - print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); break; case M32C_OPERAND_LAB_8_24 : print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); break; case M32C_OPERAND_LAB_8_8 : - print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); + print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); break; case M32C_OPERAND_LAB32_JMP_S : - print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); + print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); break; case M32C_OPERAND_Q : print_Q (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); @@ -878,8 +870,7 @@ cgen_print_fn * const m32c_cgen_print_handlers[] = void -m32c_cgen_init_dis (cd) - CGEN_CPU_DESC cd; +m32c_cgen_init_dis (CGEN_CPU_DESC cd) { m32c_cgen_init_opcode_table (cd); m32c_cgen_init_ibld_table (cd); @@ -931,7 +922,7 @@ print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, /* Print the operand as directed by the attributes. */ if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) - ; /* nothing to do */ + ; /* Nothing to do. */ else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) (*info->print_address_func) (value, info); else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) @@ -1013,6 +1004,7 @@ read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) { (*info->memory_error_func) (status, pc, info); @@ -1117,13 +1109,13 @@ print_insn (CGEN_CPU_DESC cd, length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value_cropped, &fields, pc); - /* length < 0 -> error */ + /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* length is in bits, result is in bytes */ + /* Length is in bits, result is in bytes. */ return length / 8; } } @@ -1173,7 +1165,8 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) Print one instruction from PC on INFO->STREAM. Return the size of the instruction (in bytes). */ -typedef struct cpu_desc_list { +typedef struct cpu_desc_list +{ struct cpu_desc_list *next; int isa; int mach; @@ -1236,7 +1229,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) break; } } - } + } /* If we haven't initialized yet, initialize the opcode table. */ if (! cd) @@ -1258,7 +1251,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) if (!cd) abort (); - /* save this away for future reference */ + /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; cl->isa = isa; diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index 9692575..f5c2dc3 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -1,25 +1,26 @@ /* Instruction building/extraction support for m32c. -*- C -*- -THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. -- the resultant file is machine generated, cgen-ibld.in isn't + THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. + - the resultant file is machine generated, cgen-ibld.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005 + Free Software Foundation, Inc. -This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of the GNU Binutils and GDB, the GNU debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* ??? Eventually more and more of this stuff can go to cpu-independent files. Keep that in mind. */ @@ -35,9 +36,9 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "opintl.h" #include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) /* Used by the ifield rtx function. */ @@ -136,12 +137,6 @@ insert_normal (CGEN_CPU_DESC cd, if (length == 0) return NULL; -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -286,7 +281,7 @@ insert_insn_normal (CGEN_CPU_DESC cd, #if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here - because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, @@ -304,6 +299,7 @@ put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int shift = insn_length - length; /* Written this way to avoid undefined behaviour. */ CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } @@ -374,9 +370,7 @@ extract_1 (CGEN_CPU_DESC cd, { unsigned long x; int shift; -#if 0 - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; -#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) @@ -439,12 +433,6 @@ extract_normal (CGEN_CPU_DESC cd, return 1; } -#if 0 - if (CGEN_INT_INSN_P - && word_offset != 0) - abort (); -#endif - if (word_length > 32) abort (); @@ -539,10 +527,10 @@ extract_insn_normal (CGEN_CPU_DESC cd, return CGEN_INSN_BITSIZE (insn); } -/* machine generated code added here */ +/* Machine generated code added here. */ const char * m32c_cgen_insert_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); /* Main entry point for operand insertion. @@ -559,12 +547,11 @@ const char * m32c_cgen_insert_operand resolved during parsing. */ const char * -m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc ATTRIBUTE_UNUSED; +m32c_cgen_insert_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc ATTRIBUTE_UNUSED) { const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); @@ -1050,6 +1037,13 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc) errmsg = insert_normal (cd, value, 0, 0, 8, 16, 32, total_length, buffer); } break; + case M32C_OPERAND_DSP_8_U24 : + { + long value = fields->f_dsp_8_u24; + value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + errmsg = insert_normal (cd, value, 0, 0, 8, 24, 32, total_length, buffer); + } + break; case M32C_OPERAND_DSP_8_U6 : errmsg = insert_normal (cd, fields->f_dsp_8_u6, 0, 0, 8, 6, 32, total_length, buffer); break; @@ -1422,7 +1416,7 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc) { long value = fields->f_lab_5_3; value = ((value) - (((pc) + (2)))); - errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, buffer); + errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, buffer); } break; case M32C_OPERAND_LAB_8_16 : @@ -1449,8 +1443,10 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc) case M32C_OPERAND_LAB32_JMP_S : { { - FLD (f_7_1) = ((((FLD (f_lab32_jmp_s)) - (pc))) & (1)); - FLD (f_2_2) = ((unsigned int) (((FLD (f_lab32_jmp_s)) - (pc))) >> (1)); + SI tmp_val; + tmp_val = ((((FLD (f_lab32_jmp_s)) - (pc))) - (2)); + FLD (f_7_1) = ((tmp_val) & (1)); + FLD (f_2_2) = ((unsigned int) (tmp_val) >> (1)); } errmsg = insert_normal (cd, fields->f_2_2, 0, 0, 2, 2, 32, total_length, buffer); if (errmsg) @@ -1678,8 +1674,7 @@ m32c_cgen_insert_operand (cd, opindex, fields, buffer, pc) } int m32c_cgen_extract_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); /* Main entry point for operand extraction. The result is <= 0 for error, >0 for success. @@ -1697,13 +1692,12 @@ int m32c_cgen_extract_operand the handlers. */ int -m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - int opindex; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS * fields; - bfd_vma pc; +m32c_cgen_extract_operand (CGEN_CPU_DESC cd, + int opindex, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS * fields, + bfd_vma pc) { /* Assume success (for those operands that are nops). */ int length = 1; @@ -2152,6 +2146,14 @@ m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) fields->f_dsp_8_u16 = value; } break; + case M32C_OPERAND_DSP_8_U24 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 24, 32, total_length, pc, & value); + value = ((((((unsigned int) (value) >> (16))) | (((value) & (65280))))) | (((((value) & (255))) << (16)))); + fields->f_dsp_8_u24 = value; + } + break; case M32C_OPERAND_DSP_8_U6 : length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 6, 32, total_length, pc, & fields->f_dsp_8_u6); break; @@ -2526,7 +2528,7 @@ m32c_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case M32C_OPERAND_LAB_5_3 : { long value; - length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, pc, & value); + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 3, 32, total_length, pc, & value); value = ((value) + (((pc) + (2)))); fields->f_lab_5_3 = value; } @@ -2793,10 +2795,8 @@ cgen_extract_fn * const m32c_cgen_extract_handlers[] = extract_insn_normal, }; -int m32c_cgen_get_int_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); -bfd_vma m32c_cgen_get_vma_operand - PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +int m32c_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); +bfd_vma m32c_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); /* Getting values from cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they return. @@ -2804,10 +2804,9 @@ bfd_vma m32c_cgen_get_vma_operand not appropriate. */ int -m32c_cgen_get_int_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +m32c_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { int value; @@ -2984,6 +2983,9 @@ m32c_cgen_get_int_operand (cd, opindex, fields) case M32C_OPERAND_DSP_8_U16 : value = fields->f_dsp_8_u16; break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; case M32C_OPERAND_DSP_8_U6 : value = fields->f_dsp_8_u6; break; @@ -3383,10 +3385,9 @@ m32c_cgen_get_int_operand (cd, opindex, fields) } bfd_vma -m32c_cgen_get_vma_operand (cd, opindex, fields) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - const CGEN_FIELDS * fields; +m32c_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + const CGEN_FIELDS * fields) { bfd_vma value; @@ -3563,6 +3564,9 @@ m32c_cgen_get_vma_operand (cd, opindex, fields) case M32C_OPERAND_DSP_8_U16 : value = fields->f_dsp_8_u16; break; + case M32C_OPERAND_DSP_8_U24 : + value = fields->f_dsp_8_u24; + break; case M32C_OPERAND_DSP_8_U6 : value = fields->f_dsp_8_u6; break; @@ -3961,10 +3965,8 @@ m32c_cgen_get_vma_operand (cd, opindex, fields) return value; } -void m32c_cgen_set_int_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); -void m32c_cgen_set_vma_operand - PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); +void m32c_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); +void m32c_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); /* Stuffing values in cgen_fields is handled by a collection of functions. They are distinguished by the type of the VALUE argument they accept. @@ -3972,11 +3974,10 @@ void m32c_cgen_set_vma_operand not appropriate. */ void -m32c_cgen_set_int_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - int value; +m32c_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + int value) { switch (opindex) { @@ -4149,6 +4150,9 @@ m32c_cgen_set_int_operand (cd, opindex, fields, value) case M32C_OPERAND_DSP_8_U16 : fields->f_dsp_8_u16 = value; break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; case M32C_OPERAND_DSP_8_U6 : fields->f_dsp_8_u6 = value; break; @@ -4529,11 +4533,10 @@ m32c_cgen_set_int_operand (cd, opindex, fields, value) } void -m32c_cgen_set_vma_operand (cd, opindex, fields, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - int opindex; - CGEN_FIELDS * fields; - bfd_vma value; +m32c_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + int opindex, + CGEN_FIELDS * fields, + bfd_vma value) { switch (opindex) { @@ -4706,6 +4709,9 @@ m32c_cgen_set_vma_operand (cd, opindex, fields, value) case M32C_OPERAND_DSP_8_U16 : fields->f_dsp_8_u16 = value; break; + case M32C_OPERAND_DSP_8_U24 : + fields->f_dsp_8_u24 = value; + break; case M32C_OPERAND_DSP_8_U6 : fields->f_dsp_8_u6 = value; break; @@ -5088,8 +5094,7 @@ m32c_cgen_set_vma_operand (cd, opindex, fields, value) /* Function to call before using the instruction builder tables. */ void -m32c_cgen_init_ibld_table (cd) - CGEN_CPU_DESC cd; +m32c_cgen_init_ibld_table (CGEN_CPU_DESC cd) { cd->insert_handlers = & m32c_cgen_insert_handlers[0]; cd->extract_handlers = & m32c_cgen_extract_handlers[0]; diff --git a/opcodes/m32c-opc.c b/opcodes/m32c-opc.c index 9521183..eeb7321 100644 --- a/opcodes/m32c-opc.c +++ b/opcodes/m32c-opc.c @@ -53,10 +53,10 @@ m32c_asm_hash (const char *mnem) /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ -static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int asm_hash_insn PARAMS ((const char *)); -static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); -static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); +static int asm_hash_insn_p (const CGEN_INSN *); +static unsigned int asm_hash_insn (const char *); +static int dis_hash_insn_p (const CGEN_INSN *); +static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ @@ -7638,7 +7638,7 @@ static const CGEN_IFMT ifmt_mov16_w_S_imm_a0 ATTRIBUTE_UNUSED = { }; static const CGEN_IFMT ifmt_mov32_l_a0 ATTRIBUTE_UNUSED = { - 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_DSP_16_U24) }, { F (F_4_4) }, { 0 } } + 32, 32, 0xff000000, { { F (F_0_4) }, { F (F_4_4) }, { F (F_DSP_8_U24) }, { 0 } } }; static const CGEN_IFMT ifmt_popc16_imm16 ATTRIBUTE_UNUSED = { @@ -40026,84 +40026,6 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (Z), ' ', '#', '0', ',', OP (DSP_8_U16), 0 } }, & ifmt_mov16_b_Z_imm8_dst3_dst16_3_S_8_16_absolute_QI, { 0xb70000 } }, -/* mov.b${S} #${Imm-8-QI},r0l */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, - & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 } - }, -/* mov.b${S} #${Imm-8-QI},r0h */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, - & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 } - }, -/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, - & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 } - }, -/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 } - }, -/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 } - }, -/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, - & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 } - }, -/* mov.w${S} #${Imm-8-HI},r0 */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, - & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 } - }, -/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, - & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 } - }, -/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, - & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 } - }, -/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, - & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 } - }, -/* mov.b${S} #${Imm-8-QI},r0l */ - { - { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, - & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 } - }, /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */ { { 0, 0, 0, 0 }, @@ -40356,6 +40278,84 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (Q), ' ', '#', OP (IMM_8_S4), ',', OP (DSP_16_U16), 0 } }, & ifmt_mov16_w_imm4_Q_16_dst16_16_16_absolute_QI, { 0xd80f0000 } }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0l_direct_QI, { 0xc400 } + }, +/* mov.b${S} #${Imm-8-QI},r0h */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'h', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_R0h_direct_QI, { 0xc300 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_SB_relative_QI, { 0xc50000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_8_FB_relative_QI, { 0xc60000 } + }, +/* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', OP (DSP_16_U16), 0 } }, + & ifmt_stz16_b_S_imm8_dst3_dst16_3_S_16_16_absolute_QI, { 0xc7000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_SB_relative_HI, { 0x25000000 } + }, +/* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_HI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_w_imm_S_2_S_8_dst32_2_S_8_FB_relative_HI, { 0x35000000 } + }, +/* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_HI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_w_imm_S_2_S_16_dst32_2_S_16_absolute_HI, { 0x15000000 } + }, +/* mov.w${S} #${Imm-8-HI},r0 */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'r', '0', 0 } }, + & ifmt_tst32_w_imm_S_2_S_basic_dst32_2_S_R0_direct_HI, { 0x50000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_U8), '[', 's', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_SB_relative_QI, { 0x240000 } + }, +/* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_16_QI), ',', OP (DSP_8_S8), '[', 'f', 'b', ']', 0 } }, + & ifmt_tst32_b_imm_S_2_S_8_dst32_2_S_8_FB_relative_QI, { 0x340000 } + }, +/* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_24_QI), ',', OP (DSP_8_U16), 0 } }, + & ifmt_tst32_b_imm_S_2_S_16_dst32_2_S_16_absolute_QI, { 0x14000000 } + }, +/* mov.b${S} #${Imm-8-QI},r0l */ + { + { 0, 0, 0, 0 }, + { { MNEM, OP (S), ' ', '#', OP (IMM_8_QI), ',', 'r', '0', 'l', 0 } }, + & ifmt_tst32_b_imm_S_2_S_basic_dst32_2_S_R0l_direct_QI, { 0x400 } + }, /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */ { { 0, 0, 0, 0 }, @@ -78816,16 +78816,16 @@ static const CGEN_OPCODE m32c_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (S), ' ', '#', OP (IMM_8_HI), ',', 'a', '1', 0 } }, & ifmt_mov16_w_S_imm_a0, { 0x9d0000 } }, -/* mov.l$S #${Dsp-16-u24},a0 */ +/* mov.l$S #${Dsp-8-u24},a0 */ { { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (DSP_16_U24), ',', 'a', '0', 0 } }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '0', 0 } }, & ifmt_mov32_l_a0, { 0xbc000000 } }, -/* mov.l$S #${Dsp-16-u24},a1 */ +/* mov.l$S #${Dsp-8-u24},a1 */ { { 0, 0, 0, 0 }, - { { MNEM, OP (S), ' ', '#', OP (DSP_16_U24), ',', 'a', '1', 0 } }, + { { MNEM, OP (S), ' ', '#', OP (DSP_8_U24), ',', 'a', '1', 0 } }, & ifmt_mov32_l_a0, { 0xbd000000 } }, /* mov.b$S r0l,a1 */ @@ -79353,14 +79353,10 @@ dis_hash_insn (buf, value) return CGEN_DIS_HASH (buf, value); } -static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); - /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ static void -set_fields_bitsize (fields, size) - CGEN_FIELDS *fields; - int size; +set_fields_bitsize (CGEN_FIELDS *fields, int size) { CGEN_FIELDS_BITSIZE (fields) = size; } @@ -79369,15 +79365,15 @@ set_fields_bitsize (fields, size) This plugs the opcode entries and macro instructions into the cpu table. */ void -m32c_cgen_init_opcode_table (cd) - CGEN_CPU_DESC cd; +m32c_cgen_init_opcode_table (CGEN_CPU_DESC cd) { int i; int num_macros = (sizeof (m32c_cgen_macro_insn_table) / sizeof (m32c_cgen_macro_insn_table[0])); const CGEN_IBASE *ib = & m32c_cgen_macro_insn_table[0]; const CGEN_OPCODE *oc = & m32c_cgen_macro_insn_opcode_table[0]; - CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); for (i = 0; i < num_macros; ++i) { diff --git a/opcodes/m32c-opc.h b/opcodes/m32c-opc.h index 3fea93d..4e49ff4 100644 --- a/opcodes/m32c-opc.h +++ b/opcodes/m32c-opc.h @@ -1393,20 +1393,20 @@ typedef enum cgen_insn_type { , M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI , M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI , M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI - , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI - , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI - , M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI - , M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI - , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI - , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI - , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI - , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI - , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI - , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI - , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI - , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI - , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI - , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI + , M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI + , M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI + , M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI + , M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI + , M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI + , M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI + , M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI , M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI , M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI , M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI @@ -3080,6 +3080,7 @@ struct cgen_fields long f_16_1; long f_16_2; long f_16_4; + long f_16_8; long f_18_1; long f_18_2; long f_18_3; @@ -3089,6 +3090,8 @@ struct cgen_fields long f_20_4; long f_21_3; long f_24_2; + long f_24_8; + long f_32_16; long f_src16_rn; long f_src16_an; long f_src32_an_unprefixed; @@ -3151,6 +3154,7 @@ struct cgen_fields long f_dsp_48_u16; long f_dsp_48_s16; long f_dsp_64_u16; + long f_dsp_8_u24; long f_dsp_16_u24; long f_dsp_24_u24; long f_dsp_32_u24; |