diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/arc-ext.c | 73 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 1 | ||||
| -rw-r--r-- | opcodes/tic54x-opc.c | 650 |
4 files changed, 370 insertions, 361 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dcf63bc..e3f28d8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2001-08-31 Andreas Jaeger <aj@suse.de> + + * tic54x-opc.c: Add default initializers to avoid warnings. + + * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. + * arc-ext.c: Likewise. + 2001-08-28 matthew gren <mrg@redhat.com> * ppc-opc.c (icbt): Order correctly. diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c index 1a53da9..fd43d29 100644 --- a/opcodes/arc-ext.c +++ b/opcodes/arc-ext.c @@ -1,4 +1,4 @@ -/* ARC target-dependent stuff. Extension structure access functions +/* ARC target-dependent stuff. Extension structure access functions Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. This file is part of GDB. @@ -17,6 +17,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include <stdlib.h> #include <stdio.h> #include "bfd.h" @@ -29,9 +30,9 @@ static struct arcExtMap arc_extension_map; /* Get the name of an extension instruction. */ const char * -arcExtMap_instName(int opcode, int minor, int *flags) +arcExtMap_instName(int opcode, int minor, int *flags) { - if (opcode == 3) + if (opcode == 3) { /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ if (minor < 0x09 || minor == 0x3f) @@ -53,7 +54,7 @@ arcExtMap_instName(int opcode, int minor, int *flags) /* Get the name of an extension core register. */ const char * -arcExtMap_coreRegName(int value) +arcExtMap_coreRegName(int value) { if (value < 32) return 0; @@ -63,7 +64,7 @@ arcExtMap_coreRegName(int value) /* Get the name of an extension condition code. */ const char * -arcExtMap_condCodeName(int value) +arcExtMap_condCodeName(int value) { if (value < 16) return 0; @@ -88,7 +89,7 @@ arcExtMap_auxRegName(long address) /* Recursively free auxilliary register strcture pointers until the list is empty. */ -static void +static void clean_aux_registers(struct ExtAuxRegister *r) { if (r -> next) @@ -98,14 +99,14 @@ clean_aux_registers(struct ExtAuxRegister *r) free(r -> next); r ->next = NULL; } - else + else free(r -> name); } - + /* Free memory that has been allocated for the extensions. */ -static void -cleanup_ext_map(void) +static void +cleanup_ext_map(void) { struct ExtAuxRegister *r; struct ExtInstruction *insn; @@ -113,45 +114,45 @@ cleanup_ext_map(void) /* clean aux reg structure */ r = arc_extension_map.auxRegisters; - if (r) + if (r) { (clean_aux_registers(r)); free(r); } - + /* clean instructions */ - for (i = 0; i < NUM_EXT_INST; i++) + for (i = 0; i < NUM_EXT_INST; i++) { insn = arc_extension_map.instructions[i]; if (insn) free(insn->name); } - + /* clean core reg struct */ - for (i = 0; i < NUM_EXT_CORE; i++) + for (i = 0; i < NUM_EXT_CORE; i++) { if (arc_extension_map.coreRegisters[i]) free(arc_extension_map.coreRegisters[i]); } - + for (i = 0; i < NUM_EXT_COND; i++) { if (arc_extension_map.condCodes[i]) free(arc_extension_map.condCodes[i]); } - - memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); + + memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); } -int -arcExtMap_add(void *base, unsigned long length) +int +arcExtMap_add(void *base, unsigned long length) { unsigned char *block = base; unsigned char *p = block; - + /* Clean up and reset everything if needed. */ cleanup_ext_map(); - while (p && p < (block + length)) + while (p && p < (block + length)) { /* p[0] == length of record p[1] == type of record @@ -170,7 +171,7 @@ arcExtMap_add(void *base, unsigned long length) if (p[0] == 0) return -1; - + switch (p[1]) { case EXT_INSTRUCTION: @@ -178,9 +179,9 @@ arcExtMap_add(void *base, unsigned long length) char opcode = p[2]; char minor = p[3]; char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); - struct ExtInstruction * insn = + struct ExtInstruction * insn = (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); - + if (opcode==3) opcode = 0x1f - 0x10 + minor - 0x09 + 1; else @@ -191,8 +192,8 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.instructions[(int) opcode] = insn; } break; - - case EXT_CORE_REGISTER: + + case EXT_CORE_REGISTER: { char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); @@ -200,19 +201,19 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.coreRegisters[p[2]-32] = core_name; } break; - - case EXT_COND_CODE: + + case EXT_COND_CODE: { char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); strcpy(cc_name, (p+3)); arc_extension_map.condCodes[p[2]-16] = cc_name; - } + } break; - - case EXT_AUX_REGISTER: + + case EXT_AUX_REGISTER: { /* trickier -- need to store linked list to these */ - struct ExtAuxRegister *newAuxRegister = + struct ExtAuxRegister *newAuxRegister = (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); @@ -223,14 +224,14 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.auxRegisters = newAuxRegister; } break; - + default: return -1; - + } p += p[0]; /* move to next record */ } - + return 0; } diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index b05edf0..b7afb86 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -17,6 +17,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include <stdio.h> #include "ansidecl.h" #include "opcode/arc.h" diff --git a/opcodes/tic54x-opc.c b/opcodes/tic54x-opc.c index 39714be..55bc2d8 100644 --- a/opcodes/tic54x-opc.c +++ b/opcodes/tic54x-opc.c @@ -1,5 +1,5 @@ /* Table of opcodes for the Texas Instruments TMS320C54X - Copyright 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Timothy Wall (twall@cygnus.com) This program is free software; you can redistribute it and/or modify @@ -22,90 +22,90 @@ /* these are the only register names not found in mmregs */ const symbol regs[] = { - { "AR0", 16 }, { "ar0", 16 }, - { "AR1", 17 }, { "ar1", 17 }, - { "AR2", 18 }, { "ar2", 18 }, - { "AR3", 19 }, { "ar3", 19 }, - { "AR4", 20 }, { "ar4", 20 }, - { "AR5", 21 }, { "ar5", 21 }, - { "AR6", 22 }, { "ar6", 22 }, - { "AR7", 23 }, { "ar7", 23 }, - { NULL, } + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { NULL, 0} }; /* status bits, MM registers, condition codes, etc */ /* some symbols are only valid for certain chips... */ const symbol mmregs[] = { - { "IMR", 0 }, { "imr", 0 }, - { "IFR", 1 }, { "ifr", 1 }, - { "ST0", 6 }, { "st0", 6 }, - { "ST1", 7 }, { "st1", 7 }, - { "AL", 8 }, { "al", 8 }, - { "AH", 9 }, { "ah", 9 }, - { "AG", 10 }, { "ag", 10 }, - { "BL", 11 }, { "bl", 11 }, - { "BH", 12 }, { "bh", 12 }, - { "BG", 13 }, { "bg", 13 }, - { "T", 14 }, { "t", 14 }, - { "TRN", 15 }, { "trn", 15 }, - { "AR0", 16 }, { "ar0", 16 }, - { "AR1", 17 }, { "ar1", 17 }, - { "AR2", 18 }, { "ar2", 18 }, - { "AR3", 19 }, { "ar3", 19 }, - { "AR4", 20 }, { "ar4", 20 }, - { "AR5", 21 }, { "ar5", 21 }, - { "AR6", 22 }, { "ar6", 22 }, - { "AR7", 23 }, { "ar7", 23 }, - { "SP", 24 }, { "sp", 24 }, - { "BK", 25 }, { "bk", 25 }, - { "BRC", 26 }, { "brc", 26 }, - { "RSA", 27 }, { "rsa", 27 }, - { "REA", 28 }, { "rea", 28 }, - { "PMST",29 }, { "pmst",29 }, - { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ - /* optional peripherals */ /* optional peripherals */ - { "M1F", 31 }, { "m1f", 31 }, - { "DRR0",0x20 }, { "drr0",0x20 }, - { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ - { "DXR0",0x21 }, { "dxr0",0x21 }, - { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ - { "SPC0",0x22 }, { "spc0",0x22 }, - { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ - { "SPCE0",0x23 }, { "spce0",0x23 }, - { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ - { "TIM", 0x24 }, { "tim", 0x24 }, - { "PRD", 0x25 }, { "prd", 0x25 }, - { "TCR", 0x26 }, { "tcr", 0x26 }, - { "SWWSR",0x28 }, { "swwsr",0x28 }, - { "BSCR",0x29 }, { "bscr",0x29 }, - { "HPIC",0x2C }, { "hpic",0x2c }, - /* 'c541, 'c545 */ /* 'c541, 'c545 */ - { "DRR1",0x30 }, { "drr1",0x30 }, - { "DXR1",0x31 }, { "dxr1",0x31 }, - { "SPC1",0x32 }, { "spc1",0x32 }, - /* 'c542, 'c543 */ /* 'c542, 'c543 */ - { "TRCV",0x30 }, { "trcv",0x30 }, - { "TDXR",0x31 }, { "tdxr",0x31 }, - { "TSPC",0x32 }, { "tspc",0x32 }, - { "TCSR",0x33 }, { "tcsr",0x33 }, - { "TRTA",0x34 }, { "trta",0x34 }, - { "TRAD",0x35 }, { "trad",0x35 }, - { "AXR0",0x38 }, { "axr0",0x38 }, - { "BKX0",0x39 }, { "bkx0",0x39 }, - { "ARR0",0x3A }, { "arr0",0x3a }, - { "BKR0",0x3B }, { "bkr0",0x3b }, - /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ - { "CLKMD",0x58 }, { "clkmd",0x58 }, - /* 'c548 */ /* 'c548 */ - { "AXR1",0x3C }, { "axr1",0x3c }, - { "BKX1",0x3D }, { "bkx1",0x3d }, - { "ARR1",0x3E }, { "arr1",0x3e }, - { "BKR1",0x3F }, { "bkr1",0x3f }, - { "BDRR1",0x40 }, { "bdrr1",0x40 }, - { "BDXR1",0x41 }, { "bdxr1",0x41 }, - { "BSPC1",0x42 }, { "bspc1",0x42 }, - { "BSPCE1",0x43 }, { "bspce1",0x43 }, - { NULL }, + { "IMR", 0 }, { "imr", 0 }, + { "IFR", 1 }, { "ifr", 1 }, + { "ST0", 6 }, { "st0", 6 }, + { "ST1", 7 }, { "st1", 7 }, + { "AL", 8 }, { "al", 8 }, + { "AH", 9 }, { "ah", 9 }, + { "AG", 10 }, { "ag", 10 }, + { "BL", 11 }, { "bl", 11 }, + { "BH", 12 }, { "bh", 12 }, + { "BG", 13 }, { "bg", 13 }, + { "T", 14 }, { "t", 14 }, + { "TRN", 15 }, { "trn", 15 }, + { "AR0", 16 }, { "ar0", 16 }, + { "AR1", 17 }, { "ar1", 17 }, + { "AR2", 18 }, { "ar2", 18 }, + { "AR3", 19 }, { "ar3", 19 }, + { "AR4", 20 }, { "ar4", 20 }, + { "AR5", 21 }, { "ar5", 21 }, + { "AR6", 22 }, { "ar6", 22 }, + { "AR7", 23 }, { "ar7", 23 }, + { "SP", 24 }, { "sp", 24 }, + { "BK", 25 }, { "bk", 25 }, + { "BRC", 26 }, { "brc", 26 }, + { "RSA", 27 }, { "rsa", 27 }, + { "REA", 28 }, { "rea", 28 }, + { "PMST",29 }, { "pmst",29 }, + { "XPC", 30 }, { "xpc", 30 }, /* 'c548 only */ + /* optional peripherals */ /* optional peripherals */ + { "M1F", 31 }, { "m1f", 31 }, + { "DRR0",0x20 }, { "drr0",0x20 }, + { "BDRR0",0x20 }, { "bdrr0",0x20 }, /* 'c543, 545 */ + { "DXR0",0x21 }, { "dxr0",0x21 }, + { "BDXR0",0x21 }, { "bdxr0",0x21 }, /* 'c543, 545 */ + { "SPC0",0x22 }, { "spc0",0x22 }, + { "BSPC0",0x22 }, { "bspc0",0x22 }, /* 'c543, 545 */ + { "SPCE0",0x23 }, { "spce0",0x23 }, + { "BSPCE0",0x23 }, { "bspce0",0x23 }, /* 'c543, 545 */ + { "TIM", 0x24 }, { "tim", 0x24 }, + { "PRD", 0x25 }, { "prd", 0x25 }, + { "TCR", 0x26 }, { "tcr", 0x26 }, + { "SWWSR",0x28 }, { "swwsr",0x28 }, + { "BSCR",0x29 }, { "bscr",0x29 }, + { "HPIC",0x2C }, { "hpic",0x2c }, + /* 'c541, 'c545 */ /* 'c541, 'c545 */ + { "DRR1",0x30 }, { "drr1",0x30 }, + { "DXR1",0x31 }, { "dxr1",0x31 }, + { "SPC1",0x32 }, { "spc1",0x32 }, + /* 'c542, 'c543 */ /* 'c542, 'c543 */ + { "TRCV",0x30 }, { "trcv",0x30 }, + { "TDXR",0x31 }, { "tdxr",0x31 }, + { "TSPC",0x32 }, { "tspc",0x32 }, + { "TCSR",0x33 }, { "tcsr",0x33 }, + { "TRTA",0x34 }, { "trta",0x34 }, + { "TRAD",0x35 }, { "trad",0x35 }, + { "AXR0",0x38 }, { "axr0",0x38 }, + { "BKX0",0x39 }, { "bkx0",0x39 }, + { "ARR0",0x3A }, { "arr0",0x3a }, + { "BKR0",0x3B }, { "bkr0",0x3b }, + /* 'c545, 'c546, 'c548 */ /* 'c545, 'c546, 'c548 */ + { "CLKMD",0x58 }, { "clkmd",0x58 }, + /* 'c548 */ /* 'c548 */ + { "AXR1",0x3C }, { "axr1",0x3c }, + { "BKX1",0x3D }, { "bkx1",0x3d }, + { "ARR1",0x3E }, { "arr1",0x3e }, + { "BKR1",0x3F }, { "bkr1",0x3f }, + { "BDRR1",0x40 }, { "bdrr1",0x40 }, + { "BDXR1",0x41 }, { "bdxr1",0x41 }, + { "BSPC1",0x42 }, { "bspc1",0x42 }, + { "BSPCE1",0x43 }, { "bspce1",0x43 }, + { NULL, 0}, }; const symbol condition_codes[] = { @@ -131,25 +131,25 @@ const symbol condition_codes[] = { { "aneq", CC1|CCNEQ }, { "ANEQ", CC1|CCNEQ }, { "alt", CC1|CCLT }, { "ALT", CC1|CCLT }, { "aleq", CC1|CCLEQ }, { "ALEQ", CC1|CCLEQ }, - { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, - { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, - { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, - { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, - { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, - { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, - { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, - { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, - { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, - { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, - { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, - { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, - { "tc", CCTC }, { "TC", CCTC }, - { "ntc", CCNTC }, { "NTC", CCNTC }, - { "c", CCC }, { "C", CCC }, - { "nc", CCNC }, { "NC", CCNC }, - { "bio", CCBIO }, { "BIO", CCBIO }, - { "nbio", CCNBIO }, { "NBIO", CCNBIO }, - { NULL, } + { "agt", CC1|CCGT }, { "AGT", CC1|CCGT }, + { "ageq", CC1|CCGEQ }, { "AGEQ", CC1|CCGEQ }, + { "aov", CC1|CCOV }, { "AOV", CC1|CCOV }, + { "anov", CC1|CCNOV }, { "ANOV", CC1|CCNOV }, + { "beq", CC1|CCB|CCEQ }, { "BEQ", CC1|CCB|CCEQ }, + { "bneq", CC1|CCB|CCNEQ }, { "BNEQ", CC1|CCB|CCNEQ }, + { "blt", CC1|CCB|CCLT }, { "BLT", CC1|CCB|CCLT }, + { "bleq", CC1|CCB|CCLEQ }, { "BLEQ", CC1|CCB|CCLEQ }, + { "bgt", CC1|CCB|CCGT }, { "BGT", CC1|CCB|CCGT }, + { "bgeq", CC1|CCB|CCGEQ }, { "BGEQ", CC1|CCB|CCGEQ }, + { "bov", CC1|CCB|CCOV }, { "BOV", CC1|CCB|CCOV }, + { "bnov", CC1|CCB|CCNOV }, { "BNOV", CC1|CCB|CCNOV }, + { "tc", CCTC }, { "TC", CCTC }, + { "ntc", CCNTC }, { "NTC", CCNTC }, + { "c", CCC }, { "C", CCC }, + { "nc", CCNC }, { "NC", CCNC }, + { "bio", CCBIO }, { "BIO", CCBIO }, + { "nbio", CCNBIO }, { "NBIO", CCNBIO }, + { NULL, 0 } }; const symbol cc2_codes[] = { @@ -166,7 +166,7 @@ const symbol cc2_codes[] = { { "BLT", 11 }, { "blt", 11 }, { "BLEQ", 15 },{ "bleq", 15 }, { "BGEQ", 10 },{ "bgeq", 10 }, - { NULL }, + { NULL, 0 }, }; const symbol cc3_codes[] = { @@ -174,15 +174,15 @@ const symbol cc3_codes[] = { { "LT", 0x0100 }, { "lt", 0x0100 }, { "GT", 0x0200 }, { "gt", 0x0200 }, { "NEQ", 0x0300 }, { "neq", 0x0300 }, - { "0", 0x0000 }, + { "0", 0x0000 }, { "1", 0x0100 }, { "2", 0x0200 }, { "3", 0x0300 }, - { "00", 0x0000 }, + { "00", 0x0000 }, { "01", 0x0100 }, { "10", 0x0200 }, { "11", 0x0300 }, - { NULL }, + { NULL, 0 }, }; /* FIXME -- also allow decimal digits */ @@ -203,7 +203,7 @@ const symbol status_bits[] = { { "C16", 7 }, { "c16", 7 }, { "FRCT", 6 }, { "frct", 6 }, { "CMPT", 5 }, { "cmpt", 5 }, - { NULL }, + { NULL, 0 }, }; const char *misc_symbols[] = { @@ -216,7 +216,7 @@ const char *misc_symbols[] = { /* Due to the way instructions are hashed and scanned in gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively - placed + placed Items marked with "PREFER" have been moved prior to a more costly instruction with a similar operand format. @@ -225,236 +225,236 @@ const char *misc_symbols[] = { as an argument are arranged so that the more restrictive (predefined symbol) version is checked first (marked "SRC"). */ -const template tic54x_unknown_opcode = - { "???", 1,0,0,0x0000, 0x0000, {0}, }; +const template tic54x_unknown_opcode = + { "???", 1,0,0,0x0000, 0x0000, {0}, 0, 0, 0}; const template tic54x_optab[] = { /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */ - { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, - { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, - { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, }, - { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, }, + { "fb", 2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, 0, 0 }, + { "fbd", 2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, + { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, 0, 0 }, + { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, - { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, }, - { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, - { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ - { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ - { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, - { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR}, - { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, },/*PREFER*/ - { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 }, + { "abs", 1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "add", 1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "add", 1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0},/*SRC*/ + { "add", 1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "add", 1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, 0, 0 }, + { "add", 1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 }, + { "add", 1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, 0, 0 },/*PREFER*/ + { "add", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, FL_EXT|FL_SMR, 0x0C00, 0xFCE0}, - { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, - { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, }, - { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, - { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, - { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, }, - { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, - { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, - { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, }, - { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, - { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, - { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, - { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, - { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, }, - { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, }, - { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_BRANCH|FL_NR, }, + { "add", 1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0}, + { "add", 2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "add", 2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "addc", 1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "addm", 2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, 0, 0 }, + { "adds", 1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "and", 1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 }, + { "and", 1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "and", 2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "and", 2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "andm", 2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, 0, 0 }, + { "b", 2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, 0, 0 }, + { "bd", 2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 }, + { "bacc", 1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, 0, 0 }, + { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, 0, 0 }, + { "banz", 2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, 0, 0 }, + { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 }, + { "bc", 2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, 0, 0 }, { "bcd", 2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_BRANCH|FL_DELAY|FL_NR, }, - { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, }, - { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, - { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR }, - { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, }, - { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, }, - { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, }, - { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, }, - { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_BRANCH|FL_NR, }, + B_BRANCH|FL_DELAY|FL_NR, 0, 0 }, + { "bit", 1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, 0, 0 }, + { "bitf", 2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, 0, 0 }, + { "bitt", 1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "cala", 1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, 0, 0 }, + { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, 0, 0 }, + { "call", 2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, 0, 0 }, + { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, 0, 0 }, + { "cc", 2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_BRANCH|FL_NR, 0, 0 }, { "ccd", 2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_BRANCH|FL_DELAY|FL_NR, }, - { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, - { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR }, - { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, }, - { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, }, - { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, }, - { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, }, - { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR }, - { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, }, - { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, }, - { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, }, - { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, }, - { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, }, - { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, }, - { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, }, - { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, - { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, - { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, }, - { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, }, - { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, }, - { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, }, - { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, - { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, - { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, }, - { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, }, - { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, }, - { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, - { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ - { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, },/*SRC*/ + B_BRANCH|FL_DELAY|FL_NR, 0, 0 }, + { "cmpl", 1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "cmpm", 2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, 0, 0 }, + { "cmpr", 1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, 0, 0 }, + { "cmps", 1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 }, + { "dadd", 1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 }, + { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "dld", 1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 }, + { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, 0, 0 }, + { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 }, + { "dst", 1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, 0, 0 }, + { "dsub", 1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, 0, 0 }, + { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, 0, 0 }, + { "exp", 1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, 0, 0 }, + { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, + { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, 0, 0 }, + { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, + { "firs", 2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, 0, 0 }, + { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, 0, 0 }, + { "fret", 1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, 0, 0 }, + { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, + { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, 0, 0 }, + { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, 0, 0 }, + { "idle", 1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, 0, 0 }, + { "intr", 1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, 0, 0 }, + { "ld", 1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, 0, 0 },/*SRC*/ /* alternate syntax */ - { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, },/*SRC*/ - { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, },/*SRC*/ - { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, },/*SRC*/ - { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, },/*SRC*/ - { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, },/*PREFER */ - { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR },/*SRC*/ - { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR },/*SRC*/ - { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR },/*SRC*/ - { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR }, - { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR }, - { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, },/*PREFER*/ - { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, + { "ld", 1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, 0, 0 },/*PREFER */ + { "ld", 1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, 0, 0 },/*SRC*/ + { "ld", 1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "ld", 1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, 0, 0 }, + { "ld", 1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, 0, 0 }, + { "ld", 1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, 0, 0 },/*PREFER*/ + { "ld", 2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST}, FL_EXT|FL_SMR, 0x0C40, 0xFEE0 }, - { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, }, - { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, }, - { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, }, - { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR},/*pseudo-op*/ - { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, }, - { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR }, - { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, - { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, }, - { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR }, - { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR}, - { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ - { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, - { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR },/*SRC*/ - { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, - { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, - { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR }, - { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, }, - { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, }, - { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, - { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, }, - { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, },/*SRC*/ - { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR }, - { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, }, - { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, }, - { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, }, - { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, - { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR }, - { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, }, - { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, }, /*SRC*/ - { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR }, - { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, }, - { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR }, - { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, }, - { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR }, - { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, }, - { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, }, - { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, }, - { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, }, - { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, - { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, }, - { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, }, - { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ - { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, - { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, - { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, }, - { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR }, - { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, }, - { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, }, - { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, }, - { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR }, - { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR }, - { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, }, - { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, }, - { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, - { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_RET|FL_NR, }, - { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, - B_RET|FL_DELAY|FL_NR, }, - { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, }, - { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, }, - { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, }, - { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, - { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, }, - { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, }, - { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR }, - { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, }, - { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, }, - { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, }, - { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, }, - { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, }, - { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, }, - { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, }, - { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, }, - { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, }, - { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, - { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, }, - { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, }, - { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, - { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, }, - { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, }, - { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, }, - { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, },/*SRC*/ - { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR }, - { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, }, - { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, }, - { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, }, - { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, }, - { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, }, - { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, }, - { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, - { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, - { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + { "ld", 2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, 0, 0 }, + { "ld", 2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, 0, 0 }, + { "ldm", 1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, 0, 0 }, + { "ldr", 1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "ldu", 1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "ldx", 2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, 0, 0},/*pseudo-op*/ + { "lms", 1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 }, + { "ltd", 1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "mac", 1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "mac", 1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "mac", 2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "mac", 2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 }, + { "macr", 1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "macr", 1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, 0, 0 }, + { "maca", 1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },/*SRC*/ + { "maca", 1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 }, + { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 },/*SRC*/ + { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 }, + { "macd", 2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, 0, 0 }, + { "macp", 2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, 0, 0 }, + { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, 0, 0 }, + { "mar", 1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, 0, 0 }, + { "mas", 1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "mas", 1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "masr", 1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "masr", 1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "masa", 1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "masa", 1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, 0, 0 }, + { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "max", 1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, 0, 0 }, + { "min", 1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, 0, 0 }, + { "mpy", 1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "mpy", 1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0 }, + { "mpy", 2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, 0, 0 }, + { "mpy", 2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, 0, 0 }, + { "mpyr", 1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "mpya", 1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, 0, 0 }, /*SRC*/ + { "mpya", 1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "mpyu", 1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "mvdd", 1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 }, + { "mvdk", 2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, 0, 0 }, + { "mvdm", 2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, 0, 0 }, + { "mvdp", 2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, 0, 0 }, + { "mvkd", 2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, 0, 0 }, + { "mvmd", 2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, 0, 0 }, + { "mvmm", 1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, 0, 0 }, + { "mvpd", 2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, 0, 0 }, + { "neg", 1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "nop", 1,0,0,0xF495, 0xFFFF, {OP_None}, 0, 0, 0 }, + { "norm", 1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "or", 1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "or", 1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "or", 2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "or", 2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "orm", 2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, 0, 0 }, + { "poly", 1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "popd", 1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, 0, 0 }, + { "popm", 1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, 0, 0 }, + { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, 0, 0 }, + { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, 0, 0 }, + { "pshd", 1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "pshm", 1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, 0, 0 }, + { "ret", 1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 }, + { "retd", 1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 }, + { "rc", 1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_NR, 0, 0 }, + { "rcd", 1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC}, + B_RET|FL_DELAY|FL_NR, 0, 0 }, + { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, 0, 0 }, + { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, 0, 0 }, + { "rete", 1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 }, + { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 }, + { "retf", 1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, 0, 0 }, + { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, 0, 0 }, + { "rnd", 1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, 0, 0 }, + { "rol", 1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "ror", 1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "rpt", 1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, 0, 0 }, + { "rpt", 1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, 0, 0 }, + { "rpt", 2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, 0, 0 }, + { "rptb", 2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, 0, 0 }, + { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, 0, 0 }, + { "rptz", 2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, 0, 0 }, + { "rsbx", 1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, 0, 0 }, + { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, 0, 0 }, + { "sat", 1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "sfta", 1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 }, + { "sftc", 1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, 0, 0 }, + { "sftl", 1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, 0, 0 }, + { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, 0, 0 }, + { "squr", 1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, 0, 0 },/*SRC*/ + { "squr", 1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, 0, 0 }, + { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, 0, 0 }, + { "ssbx", 1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, 0, 0 }, + { "st", 1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, 0, 0 }, + { "st", 1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, 0, 0 }, + { "st", 2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, 0, 0 }, + { "sth", 1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 }, + { "sth", 1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, 0, 0 }, + { "sth", 1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, 0, 0 }, + { "sth", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, FL_EXT, 0x0C60, 0xFEE0 }, - { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, }, - { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, }, - { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, }, - { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, + { "stl", 1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, 0, 0 }, + { "stl", 1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, 0, 0 }, + { "stl", 1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, 0, 0 }, + { "stl", 2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem}, FL_EXT, 0x0C80, 0xFEE0 }, - { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, }, - { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, }, - { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, }, - { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ - { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, },/*SRC*/ - { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR }, - { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR }, - { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, }, /*PREFER*/ - { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, + { "stlm", 1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, 0, 0 }, + { "stm", 2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, 0, 0 }, + { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, 0, 0 }, + { "sub", 1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "sub", 1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "sub", 1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "sub", 1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, 0, 0 }, + { "sub", 1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, 0, 0 }, + { "sub", 1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, 0, 0 }, /*PREFER*/ + { "sub", 2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, FL_EXT|FL_SMR, 0x0C20, 0xFCE0 }, - { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, }, - { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, - { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, }, - { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, }, - { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR }, - { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, }, - { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, },/*SRC*/ - { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR }, - { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, }, - { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, }, - { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, }, - { NULL, }, + { "sub", 1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, 0, 0 }, + { "sub", 2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "sub", 2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "subb", 1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "subc", 1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "subs", 1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "trap", 1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, 0, 0 }, + { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, 0, 0 }, + { "xc", 1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, 0, 0 }, + { "xor", 1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, 0, 0 },/*SRC*/ + { "xor", 1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, 0, 0 }, + { "xor", 2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "xor", 2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, 0, 0 }, + { "xorm", 2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, 0, 0 }, + { NULL, 0,0,0,0,0, {}, 0, 0, 0 }, }; /* assume all parallel instructions have at least three operands */ @@ -472,5 +472,5 @@ const partemplate tic54x_paroptab[] = { { "st","masr",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, { "st","mpy", 1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, { "st","sub", 1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},{OP_Xmem,OP_DST}, }, - { NULL,NULL }, + { NULL,NULL, 0, 0, 0, 0, 0, {}, {}, }, }; |