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-rw-r--r--opcodes/ChangeLog17
-rw-r--r--opcodes/aarch64-dis.c5
-rw-r--r--opcodes/aarch64-opc.c7
-rw-r--r--opcodes/arc-dis.c1
-rw-r--r--opcodes/arm-dis.c1
-rw-r--r--opcodes/i386-dis.c10
-rw-r--r--opcodes/m68k-dis.c1
-rw-r--r--opcodes/mep-asm.c1
-rw-r--r--opcodes/ns32k-dis.c1
-rw-r--r--opcodes/sh-dis.c2
-rw-r--r--opcodes/tic4x-dis.c1
-rw-r--r--opcodes/tic6x-dis.c1
-rw-r--r--opcodes/vax-dis.c3
13 files changed, 47 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6602768..4416659 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,22 @@
2016-10-06 Alan Modra <amodra@gmail.com>
+ * aarch64-opc.c: Spell fall through comments consistently.
+ * i386-dis.c: Likewise.
+ * aarch64-dis.c: Add missing fall through comments.
+ * aarch64-opc.c: Likewise.
+ * arc-dis.c: Likewise.
+ * arm-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * m68k-dis.c: Likewise.
+ * mep-asm.c: Likewise.
+ * ns32k-dis.c: Likewise.
+ * sh-dis.c: Likewise.
+ * tic4x-dis.c: Likewise.
+ * tic6x-dis.c: Likewise.
+ * vax-dis.c: Likewise.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
* arc-ext.c (create_map): Add missing break.
* msp430-decode.opc (encode_as): Likewise.
* msp430-decode.c: Regenerate.
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 82afe8b..d8c5fa7 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -788,10 +788,15 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
switch (simd_size)
{
case 2: imm = (imm << 2) | imm;
+ /* Fall through. */
case 4: imm = (imm << 4) | imm;
+ /* Fall through. */
case 8: imm = (imm << 8) | imm;
+ /* Fall through. */
case 16: imm = (imm << 16) | imm;
+ /* Fall through. */
case 32: imm = (imm << 32) | imm;
+ /* Fall through. */
case 64: break;
default: assert (0); return 0;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index adc34e2..4b1411f 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1156,10 +1156,15 @@ build_immediate_table (void)
switch (log_e)
{
case 1: imm = (imm << 2) | imm;
+ /* Fall through. */
case 2: imm = (imm << 4) | imm;
+ /* Fall through. */
case 3: imm = (imm << 8) | imm;
+ /* Fall through. */
case 4: imm = (imm << 16) | imm;
+ /* Fall through. */
case 5: imm = (imm << 32) | imm;
+ /* Fall through. */
case 6: break;
default: abort ();
}
@@ -1969,7 +1974,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
case OP_MOV_IMM_WIDEN:
imm = ~imm;
- /* Fall through... */
+ /* Fall through. */
case OP_MOV_IMM_WIDE:
if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
{
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index e4df678..c4e118e 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -703,6 +703,7 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
if (minor_opcode < 4)
return 2;
}
+ /* Fall through. */
case bfd_mach_arc_arc600:
return (major_opcode > 0xb) ? 2 : 4;
break;
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index fc9ac61..87d4930 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4686,6 +4686,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
case 'S':
allow_unpredictable = TRUE;
+ /* Fall through. */
case 's':
if ((given & 0x004f0000) == 0x004f0000)
{
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index c08109e..5c5f926 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -14850,13 +14850,14 @@ intel_operand_size (int bytemode, int sizeflag)
oappend ("QWORD PTR ");
break;
}
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
oappend ("QWORD PTR ");
break;
}
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
@@ -15233,6 +15234,7 @@ OP_E_register (int bytemode, int sizeflag)
names = names64;
break;
}
+ /* Fall through. */
case stack_v_mode:
if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
@@ -15240,7 +15242,7 @@ OP_E_register (int bytemode, int sizeflag)
break;
}
bytemode = v_mode;
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
@@ -15321,7 +15323,7 @@ OP_E_memory (int bytemode, int sizeflag)
shift = vex.w ? 3 : 2;
break;
}
- /* Fall through if vex.b == 0. */
+ /* Fall through. */
case xmmqd_mode:
case xmmdw_mode:
case ymmq_mode:
@@ -17301,6 +17303,7 @@ get_vex_imm8 (int sizeflag, int opnum)
if (base != 5)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 4 byte displacement. */
bytes_before_imm += 4;
@@ -17327,6 +17330,7 @@ get_vex_imm8 (int sizeflag, int opnum)
if (modrm.rm != 6)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 2 byte displacement. */
bytes_before_imm += 2;
diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c
index 11c057d..1e7c830 100644
--- a/opcodes/m68k-dis.c
+++ b/opcodes/m68k-dis.c
@@ -1220,6 +1220,7 @@ print_insn_arg (const char *d,
case 'X':
place = '8';
+ /* Fall through. */
case 'Y':
case 'Z':
case 'W':
diff --git a/opcodes/mep-asm.c b/opcodes/mep-asm.c
index d8a1cf3..89116ee 100644
--- a/opcodes/mep-asm.c
+++ b/opcodes/mep-asm.c
@@ -745,6 +745,7 @@ expand_string (const char *in, int first_only)
break;
case '(':
depth++;
+ /* Fall through. */
default:
args[narg].len++;
break;
diff --git a/opcodes/ns32k-dis.c b/opcodes/ns32k-dis.c
index dd52cff..b14d5d7 100644
--- a/opcodes/ns32k-dis.c
+++ b/opcodes/ns32k-dis.c
@@ -472,6 +472,7 @@ print_insn_arg (int d,
case 'f':
/* A "gen" operand but 5 bits from the end of instruction. */
ioffset -= 5;
+ /* Fall through. */
case 'Z':
case 'F':
case 'L':
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 1f8dc8a..7af514b 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -836,6 +836,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
fprintf_fn (stream, "xd%d", rn & ~1);
break;
}
+ /* Fall through. */
case D_REG_N:
fprintf_fn (stream, "dr%d", rn);
break;
@@ -845,6 +846,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
fprintf_fn (stream, "xd%d", rm & ~1);
break;
}
+ /* Fall through. */
case D_REG_M:
fprintf_fn (stream, "dr%d", rm);
break;
diff --git a/opcodes/tic4x-dis.c b/opcodes/tic4x-dis.c
index c35e050..92c9dcb 100644
--- a/opcodes/tic4x-dis.c
+++ b/opcodes/tic4x-dis.c
@@ -467,6 +467,7 @@ tic4x_print_op (struct disassemble_info *info,
return 0;
break;
}
+ /* Fall through. */
case 'J': /* Indirect (short) 8--15. */
if (! tic4x_print_indirect (info, INDIRECT_SHORT,
diff --git a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c
index ec1dcc1..f642656 100644
--- a/opcodes/tic6x-dis.c
+++ b/opcodes/tic6x-dis.c
@@ -1075,6 +1075,7 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
case tic6x_coding_mem_offset_minus_one_noscale:
case tic6x_coding_mem_offset_minus_one:
fld_val += 1;
+ /* Fall through. */
case tic6x_coding_mem_offset_noscale:
case tic6x_coding_mem_offset:
mem_offset = fld_val;
diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c
index 937c452..0aec812 100644
--- a/opcodes/vax-dis.c
+++ b/opcodes/vax-dis.c
@@ -296,6 +296,7 @@ print_insn_mode (const char *d,
break;
case 0xB0: /* Displacement byte deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
+ /* Fall through. */
case 0xA0: /* Displacement byte: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 2 + NEXTBYTE (p), info);
@@ -305,6 +306,7 @@ print_insn_mode (const char *d,
break;
case 0xD0: /* Displacement word deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
+ /* Fall through. */
case 0xC0: /* Displacement word: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 3 + NEXTWORD (p), info);
@@ -314,6 +316,7 @@ print_insn_mode (const char *d,
break;
case 0xF0: /* Displacement long deferred: *displ(Rn). */
(*info->fprintf_func) (info->stream, "*");
+ /* Fall through. */
case 0xE0: /* Displacement long: displ(Rn). */
if (reg == 0xF)
(*info->print_address_func) (addr + 5 + NEXTLONG (p), info);
generated by cgit v1.1 at 2024-11-27 09:15:42 +0000