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-rw-r--r--opcodes/ChangeLog10
-rw-r--r--opcodes/Makefile.am9
-rw-r--r--opcodes/Makefile.in17
-rwxr-xr-xopcodes/configure1
-rw-r--r--opcodes/configure.in1
-rw-r--r--opcodes/cr16-dis.c820
-rw-r--r--opcodes/cr16-opc.c611
-rw-r--r--opcodes/disassemble.c6
8 files changed, 1471 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e73943d..4efc5c3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
+
+ * cr16-opc.c: New file.
+ * cr16-dis.c: New file.
+ * Makefile.am: Entries for cr16.
+ * Makefile.in: Regenerate.
+ * cofigure.in: Add cr16 target information.
+ * configure : Regenerate.
+ * disassemble.c: Add cr16 target information.
+
2007-06-28 H.J. Lu <hongjiu.lu@intel.com>
* Makefile.am (HFILES): Add i386-opc.h and i386-tbl.h.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 4ed12e7..1397b8c 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -68,6 +68,8 @@ CFILES = \
cgen-bitset.c \
cgen-dis.c \
cgen-opc.c \
+ cr16-dis.c \
+ cr16-opc.c \
cris-dis.c \
cris-opc.c \
crx-dis.c \
@@ -220,6 +222,8 @@ ALL_MACHINES = \
cgen-bitset.lo \
cgen-dis.lo \
cgen-opc.lo \
+ cr16-dis.lo \
+ cr16-opc.lo \
cris-dis.lo \
cris-opc.lo \
crx-dis.lo \
@@ -686,6 +690,11 @@ cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
$(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
+cr16-dis.lo: cr16-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
+ $(INCDIR)/opcode/cr16.h
+cr16-opc.lo: cr16-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cr16.h
cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
$(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index d9e44f2..0035a49 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -292,6 +292,8 @@ CFILES = \
cgen-bitset.c \
cgen-dis.c \
cgen-opc.c \
+ cr16-dis.c \
+ cr16-opc.c \
cris-dis.c \
cris-opc.c \
crx-dis.c \
@@ -444,6 +446,8 @@ ALL_MACHINES = \
cgen-bitset.lo \
cgen-dis.lo \
cgen-opc.lo \
+ cr16-dis.lo \
+ cr16-opc.lo \
cris-dis.lo \
cris-opc.lo \
crx-dis.lo \
@@ -643,15 +647,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__confi
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
- echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
- cd $(srcdir) && $(AUTOMAKE) --cygnus \
+ echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
+ cd $(srcdir) && $(AUTOMAKE) --foreign \
&& exit 0; \
exit 1;; \
esac; \
done; \
- echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus Makefile'; \
+ echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \
cd $(top_srcdir) && \
- $(AUTOMAKE) --cygnus Makefile
+ $(AUTOMAKE) --foreign Makefile
.PRECIOUS: Makefile
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
@case '$?' in \
@@ -1233,6 +1237,11 @@ cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h $(INCDIR)/safe-ctype.h \
$(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/symcat.h \
$(INCDIR)/opcode/cgen.h $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen-bitset.h
+cr16-dis.lo: cr16-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
+ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
+ $(INCDIR)/opcode/cr16.h
+cr16-opc.lo: cr16-opc.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \
+ $(INCDIR)/symcat.h $(INCDIR)/opcode/cr16.h
cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \
$(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \
$(INCDIR)/ansidecl.h $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h \
diff --git a/opcodes/configure b/opcodes/configure
index db6d869..7b91e40 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -11419,6 +11419,7 @@ if test x${all_targets} = xfalse ; then
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
+ bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;;
bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 33a2068..104653f 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -159,6 +159,7 @@ if test x${all_targets} = xfalse ; then
bfd_arm_arch) ta="$ta arm-dis.lo" ;;
bfd_avr_arch) ta="$ta avr-dis.lo" ;;
bfd_bfin_arch) ta="$ta bfin-dis.lo" ;;
+ bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;;
bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;;
bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;;
bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;;
diff --git a/opcodes/cr16-dis.c b/opcodes/cr16-dis.c
new file mode 100644
index 0000000..724cb9b
--- /dev/null
+++ b/opcodes/cr16-dis.c
@@ -0,0 +1,820 @@
+/* Disassembler code for CR16.
+ Copyright 2007 Free Software Foundation, Inc.
+ Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com).
+
+ This file is part of GAS, GDB and the GNU binutils.
+
+ This program is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include "dis-asm.h"
+#include "sysdep.h"
+#include "opcode/cr16.h"
+#include "libiberty.h"
+
+/* String to print when opcode was not matched. */
+#define ILLEGAL "illegal"
+ /* Escape to 16-bit immediate. */
+#define ESCAPE_16_BIT 0xB
+
+/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
+#define EXTRACT(a, offs, n_bits) \
+ (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \
+ : (((a) >> (offs)) & ((1 << (n_bits)) -1)))
+
+/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */
+#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs)))
+
+typedef unsigned long dwordU;
+typedef unsigned short wordU;
+
+typedef struct
+{
+ dwordU val;
+ int nbits;
+} parameter;
+
+/* Structure to map valid 'cinv' instruction options. */
+
+typedef struct
+ {
+ /* Cinv printed string. */
+ char *istr;
+ /* Value corresponding to the string. */
+ char *ostr;
+ }
+cinv_entry;
+
+/* CR16 'cinv' options mapping. */
+const cinv_entry cr16_cinvs[] =
+{
+ {"cinv[i]", "cinv [i]"},
+ {"cinv[i,u]", "cinv [i,u]"},
+ {"cinv[d]", "cinv [d]"},
+ {"cinv[d,u]", "cinv [d,u]"},
+ {"cinv[d,i]", "cinv [d,i]"},
+ {"cinv[d,i,u]", "cinv [d,i,u]"}
+};
+
+/* Number of valid 'cinv' instruction options. */
+static int NUMCINVS = ARRAY_SIZE (cr16_cinvs);
+
+/* Enum to distinguish different registers argument types. */
+typedef enum REG_ARG_TYPE
+ {
+ /* General purpose register (r<N>). */
+ REG_ARG = 0,
+ /*Processor register */
+ P_ARG,
+ }
+REG_ARG_TYPE;
+
+/* Current opcode table entry we're disassembling. */
+const inst *instruction;
+/* Current instruction we're disassembling. */
+ins currInsn;
+/* The current instruction is read into 3 consecutive words. */
+wordU words[3];
+/* Contains all words in appropriate order. */
+ULONGLONG allWords;
+/* Holds the current processed argument number. */
+int processing_argument_number;
+/* Nonzero means a IMM4 instruction. */
+int imm4flag;
+/* Nonzero means the instruction's original size is
+ incremented (escape sequence is used). */
+int size_changed;
+
+
+/* Print the constant expression length. */
+
+static char *
+print_exp_len (int size)
+{
+ switch (size)
+ {
+ case 4:
+ case 5:
+ case 6:
+ case 8:
+ case 14:
+ case 16:
+ return ":s";
+ case 20:
+ case 24:
+ case 32:
+ return ":m";
+ case 48:
+ return ":l";
+ default:
+ return "";
+ }
+}
+
+
+/* Retrieve the number of operands for the current assembled instruction. */
+
+static int
+get_number_of_operands (void)
+{
+ int i;
+
+ for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+ ;
+
+ return i;
+}
+
+/* Return the bit size for a given operand. */
+
+static int
+getbits (operand_type op)
+{
+ if (op < MAX_OPRD)
+ return cr16_optab[op].bit_size;
+
+ return 0;
+}
+
+/* Return the argument type of a given operand. */
+
+static argtype
+getargtype (operand_type op)
+{
+ if (op < MAX_OPRD)
+ return cr16_optab[op].arg_type;
+
+ return nullargs;
+}
+
+/* Given a 'CC' instruction constant operand, return its corresponding
+ string. This routine is used when disassembling the 'CC' instruction. */
+
+static char *
+getccstring (unsigned cc)
+{
+ return (char *) cr16_b_cond_tab[cc];
+}
+
+
+/* Given a 'cinv' instruction constant operand, return its corresponding
+ string. This routine is used when disassembling the 'cinv' instruction. */
+
+static char *
+getcinvstring (char *str)
+{
+ const cinv_entry *cinv;
+
+ for (cinv = cr16_cinvs; cinv < (cr16_cinvs + NUMCINVS); cinv++)
+ if (strcmp (cinv->istr, str) == 0)
+ return cinv->ostr;
+
+ return ILLEGAL;
+}
+
+/* Given the trap index in dispatch table, return its name.
+ This routine is used when disassembling the 'excp' instruction. */
+
+static char *
+gettrapstring (unsigned int index)
+{
+ const trap_entry *trap;
+
+ for (trap = cr16_traps; trap < cr16_traps + NUMTRAPS; trap++)
+ if (trap->entry == index)
+ return trap->name;
+
+ return ILLEGAL;
+}
+
+/* Given a register enum value, retrieve its name. */
+
+static char *
+getregname (reg r)
+{
+ const reg_entry *reg = cr16_regtab + r;
+
+ if (reg->type != CR16_R_REGTYPE)
+ return ILLEGAL;
+
+ return reg->name;
+}
+
+/* Given a register pair enum value, retrieve its name. */
+
+static char *
+getregpname (reg r)
+{
+ const reg_entry *reg = cr16_regptab + r;
+
+ if (reg->type != CR16_RP_REGTYPE)
+ return ILLEGAL;
+
+ return reg->name;
+}
+
+/* Given a index register pair enum value, retrieve its name. */
+
+static char *
+getidxregpname (reg r)
+{
+ const reg_entry *reg;
+
+ switch (r)
+ {
+ case 0: r = 0; break;
+ case 1: r = 2; break;
+ case 2: r = 4; break;
+ case 3: r = 6; break;
+ case 4: r = 8; break;
+ case 5: r = 10; break;
+ case 6: r = 3; break;
+ case 7: r = 5; break;
+ default:
+ break;
+ }
+
+ reg = cr16_regptab + r;
+
+ if (reg->type != CR16_RP_REGTYPE)
+ return ILLEGAL;
+
+ return reg->name;
+}
+
+/* Getting a processor register name. */
+
+static char *
+getprocregname (int index)
+{
+ const reg_entry *r;
+
+ for (r = cr16_pregtab; r < cr16_pregtab + NUMPREGS; r++)
+ if (r->image == index)
+ return r->name;
+
+ return "ILLEGAL REGISTER";
+}
+
+/* Getting a processor register name - 32 bit size. */
+
+static char *
+getprocpregname (int index)
+{
+ const reg_entry *r;
+
+ for (r = cr16_pregptab; r < cr16_pregptab + NUMPREGPS; r++)
+ if (r->image == index)
+ return r->name;
+
+ return "ILLEGAL REGISTER";
+}
+
+/* START and END are relating 'allWords' struct, which is 48 bits size.
+
+ START|--------|END
+ +---------+---------+---------+---------+
+ | | V | A | L |
+ +---------+---------+---------+---------+
+ 0 16 32 48
+ words [0] [1] [2] */
+
+static parameter
+makelongparameter (ULONGLONG val, int start, int end)
+{
+ parameter p;
+
+ p.val = (dwordU) EXTRACT (val, 48 - end, end - start);
+ p.nbits = end - start;
+ return p;
+}
+
+/* Build a mask of the instruction's 'constant' opcode,
+ based on the instruction's printing flags. */
+
+static unsigned long
+build_mask (void)
+{
+ unsigned long mask = SBM (instruction->match_bits);
+ return mask;
+}
+
+/* Search for a matching opcode. Return 1 for success, 0 for failure. */
+
+static int
+match_opcode (void)
+{
+ unsigned long mask;
+ /* The instruction 'constant' opcode doewsn't exceed 32 bits. */
+ unsigned long doubleWord = words[1] + (words[0] << 16);
+
+ /* Start searching from end of instruction table. */
+ instruction = &cr16_instruction[NUMOPCODES - 2];
+
+ /* Loop over instruction table until a full match is found. */
+ while (instruction >= cr16_instruction)
+ {
+ mask = build_mask ();
+ if ((doubleWord & mask) == BIN (instruction->match,
+ instruction->match_bits))
+ return 1;
+ else
+ instruction--;
+ }
+ return 0;
+}
+
+/* Set the proper parameter value for different type of arguments. */
+
+static void
+make_argument (argument * a, int start_bits)
+{
+ int inst_bit_size;
+ parameter p;
+
+ if ((instruction->size == 3) && a->size >= 16)
+ inst_bit_size = 48;
+ else
+ inst_bit_size = 32;
+
+ switch (a->type)
+ {
+ case arg_r:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->r = p.val;
+ break;
+
+ case arg_rp:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->rp = p.val;
+ break;
+
+ case arg_pr:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->pr = p.val;
+ break;
+
+ case arg_prp:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->prp = p.val;
+ break;
+
+ case arg_ic:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->constant = p.val;
+ break;
+
+ case arg_cc:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + a->size),
+ inst_bit_size - start_bits);
+
+ a->cc = p.val;
+ break;
+
+ case arg_idxr:
+ if ((IS_INSN_MNEMONIC ("cbitb"))
+ || (IS_INSN_MNEMONIC ("sbitb"))
+ || (IS_INSN_MNEMONIC ("tbitb")))
+ p = makelongparameter (allWords, 8, 9);
+ else
+ p = makelongparameter (allWords, 9, 10);
+ a->i_r = p.val;
+ p = makelongparameter (allWords, inst_bit_size - a->size, inst_bit_size);
+ a->constant = p.val;
+ break;
+
+ case arg_idxrp:
+ p = makelongparameter (allWords, start_bits + 12, start_bits + 13);
+ a->i_r = p.val;
+ p = makelongparameter (allWords, start_bits + 13, start_bits + 16);
+ a->rp = p.val;
+ if (inst_bit_size > 32)
+ {
+ p = makelongparameter (allWords, inst_bit_size - start_bits - 12,
+ inst_bit_size);
+ a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000));
+ }
+ else if (instruction->size == 2)
+ {
+ p = makelongparameter (allWords, inst_bit_size - 22, inst_bit_size);
+ a->constant = (p.val & 0xf) | (((p.val >>20) & 0x3) << 4)
+ | ((p.val >>14 & 0x3) << 6) | (((p.val >>7) & 0x1f) <<7);
+ }
+ else if (instruction->size == 1 && a->size == 0)
+ a->constant = 0;
+
+ break;
+
+ case arg_rbase:
+ p = makelongparameter (allWords, inst_bit_size, inst_bit_size);
+ a->constant = p.val;
+ p = makelongparameter (allWords, inst_bit_size - (start_bits + 4),
+ inst_bit_size - start_bits);
+ a->r = p.val;
+ break;
+
+ case arg_cr:
+ p = makelongparameter (allWords, start_bits + 12, start_bits + 16);
+ a->r = p.val;
+ p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size);
+ a->constant = p.val;
+ break;
+
+ case arg_crp:
+ if (instruction->size == 1)
+ p = makelongparameter (allWords, 12, 16);
+ else
+ p = makelongparameter (allWords, start_bits + 12, start_bits + 16);
+ a->rp = p.val;
+
+ if (inst_bit_size > 32)
+ {
+ p = makelongparameter (allWords, inst_bit_size - start_bits - 12,
+ inst_bit_size);
+ a->constant = ((p.val & 0xffff) | (p.val >> 8 & 0xf0000));
+ }
+ else if (instruction->size == 2)
+ {
+ p = makelongparameter (allWords, inst_bit_size - 16, inst_bit_size);
+ a->constant = p.val;
+ }
+ else if (instruction->size == 1 && a->size != 0)
+ {
+ p = makelongparameter (allWords, 4, 8);
+ if (IS_INSN_MNEMONIC ("loadw")
+ || IS_INSN_MNEMONIC ("loadd")
+ || IS_INSN_MNEMONIC ("storw")
+ || IS_INSN_MNEMONIC ("stord"))
+ a->constant = (p.val * 2);
+ else
+ a->constant = p.val;
+ }
+ else /* below case for 0x0(reg pair) */
+ a->constant = 0;
+
+ break;
+
+ case arg_c:
+
+ if ((IS_INSN_TYPE (BRANCH_INS))
+ || (IS_INSN_MNEMONIC ("bal"))
+ || (IS_INSN_TYPE (CSTBIT_INS))
+ || (IS_INSN_TYPE (LD_STOR_INS)))
+ {
+ switch (a->size)
+ {
+ case 8 :
+ p = makelongparameter (allWords, 0, start_bits);
+ a->constant = ((((p.val&0xf00)>>4)) | (p.val&0xf));
+ break;
+
+ case 24:
+ if (instruction->size == 3)
+ {
+ p = makelongparameter (allWords, 16, inst_bit_size);
+ a->constant = ((((p.val>>16)&0xf) << 20)
+ | (((p.val>>24)&0xf) << 16)
+ | (p.val & 0xffff));
+ }
+ else if (instruction->size == 2)
+ {
+ p = makelongparameter (allWords, 8, inst_bit_size);
+ a->constant = p.val;
+ }
+ break;
+
+ default:
+ p = makelongparameter (allWords, inst_bit_size - (start_bits +
+ a->size), inst_bit_size - start_bits);
+ a->constant = p.val;
+ break;
+ }
+ }
+ else
+ {
+ p = makelongparameter (allWords, inst_bit_size -
+ (start_bits + a->size),
+ inst_bit_size - start_bits);
+ a->constant = p.val;
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+/* Print a single argument. */
+
+static void
+print_arg (argument *a, bfd_vma memaddr, struct disassemble_info *info)
+{
+ LONGLONG longdisp, mask;
+ int sign_flag = 0;
+ int relative = 0;
+ bfd_vma number;
+ PTR stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ switch (a->type)
+ {
+ case arg_r:
+ func (stream, "%s", getregname (a->r));
+ break;
+
+ case arg_rp:
+ func (stream, "%s", getregpname (a->rp));
+ break;
+
+ case arg_pr:
+ func (stream, "%s", getprocregname (a->pr));
+ break;
+
+ case arg_prp:
+ func (stream, "%s", getprocpregname (a->prp));
+ break;
+
+ case arg_cc:
+ func (stream, "%s", getccstring (a->cc));
+ func (stream, "%s", "\t");
+ break;
+
+ case arg_ic:
+ if (IS_INSN_MNEMONIC ("excp"))
+ {
+ func (stream, "%s", gettrapstring (a->constant));
+ break;
+ }
+ else if ((IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS))
+ && ((instruction->size == 1) && (a->constant == 9)))
+ func (stream, "$%d", -1);
+ else if (INST_HAS_REG_LIST)
+ func (stream, "$0x%lx", a->constant +1);
+ else if (IS_INSN_TYPE (SHIFT_INS))
+ {
+ longdisp = a->constant;
+ mask = ((LONGLONG)1 << a->size) - 1;
+ if (longdisp & ((LONGLONG)1 << (a->size -1)))
+ {
+ sign_flag = 1;
+ longdisp = ~(longdisp) + 1;
+ }
+ a->constant = (unsigned long int) (longdisp & mask);
+ func (stream, "$%d", ((int)(sign_flag ? -a->constant :
+ a->constant)));
+ }
+ else
+ func (stream, "$0x%lx", a->constant);
+ switch (a->size)
+ {
+ case 4 : case 5 : case 6 : case 8 :
+ func (stream, "%s", ":s"); break;
+ case 16 : case 20 : func (stream, "%s", ":m"); break;
+ case 24 : case 32 : func (stream, "%s", ":l"); break;
+ default: break;
+ }
+ break;
+
+ case arg_idxr:
+ if (a->i_r == 0) func (stream, "[r12]");
+ if (a->i_r == 1) func (stream, "[r13]");
+ func (stream, "0x%lx", a->constant);
+ func (stream, "%s", print_exp_len (instruction->size * 16));
+ break;
+
+ case arg_idxrp:
+ if (a->i_r == 0) func (stream, "[r12]");
+ if (a->i_r == 1) func (stream, "[r13]");
+ func (stream, "0x%lx", a->constant);
+ func (stream, "%s", print_exp_len (instruction->size * 16));
+ func (stream, "%s", getidxregpname (a->rp));
+ break;
+
+ case arg_rbase:
+ func (stream, "(%s)", getregname (a->r));
+ break;
+
+ case arg_cr:
+ func (stream, "0x%lx", a->constant);
+ func (stream, "%s", print_exp_len (instruction->size * 16));
+ func (stream, "(%s)", getregname (a->r));
+ break;
+
+ case arg_crp:
+ func (stream, "0x%lx", a->constant);
+ func (stream, "%s", print_exp_len (instruction->size * 16));
+ func (stream, "%s", getregpname (a->rp));
+ break;
+
+ case arg_c:
+ /*Removed the *2 part as because implicit zeros are no more required.
+ Have to fix this as this needs a bit of extension in terms of branch
+ instructions. */
+ if (IS_INSN_TYPE (BRANCH_INS) || IS_INSN_MNEMONIC ("bal"))
+ {
+ relative = 1;
+ longdisp = a->constant;
+ /* REVISIT: To sync with WinIDEA and CR16 4.1tools, the below
+ line commented */
+ /* longdisp <<= 1; */
+ mask = ((LONGLONG)1 << a->size) - 1;
+ switch (a->size)
+ {
+ case 8 :
+ {
+ longdisp <<= 1;
+ if (longdisp & ((LONGLONG)1 << a->size))
+ {
+ sign_flag = 1;
+ longdisp = ~(longdisp) + 1;
+ }
+ break;
+ }
+ case 16 :
+ case 24 :
+ {
+ if (longdisp & 1)
+ {
+ sign_flag = 1;
+ longdisp = ~(longdisp) + 1;
+ }
+ break;
+ }
+ default:
+ func (stream, "Wrong offset used in branch/bal instruction");
+ break;
+ }
+ a->constant = (unsigned long int) (longdisp & mask);
+ }
+ /* For branch Neq instruction it is 2*offset + 2. */
+ else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
+ a->constant = 2 * a->constant + 2;
+
+ if ((!IS_INSN_TYPE (CSTBIT_INS)) && (!IS_INSN_TYPE (LD_STOR_INS)))
+ (sign_flag) ? func (stream, "%s", "*-"): func (stream, "%s","*+");
+
+ func (stream, "%s", "0x");
+ number = ((relative ? memaddr : 0) +
+ (sign_flag ? ((- a->constant) & 0xffffffe) : a->constant));
+
+ (*info->print_address_func) ((number & ((1 << 24) - 1)), info);
+
+ func (stream, "%s", print_exp_len (instruction->size * 16));
+ break;
+
+ default:
+ break;
+ }
+}
+
+/* Print all the arguments of CURRINSN instruction. */
+
+static void
+print_arguments (ins *currInsn, bfd_vma memaddr, struct disassemble_info *info)
+{
+ int i;
+
+ /* For "pop/push/popret RA instruction only. */
+ if ((IS_INSN_MNEMONIC ("pop")
+ || (IS_INSN_MNEMONIC ("popret")
+ || (IS_INSN_MNEMONIC ("push"))))
+ && currInsn->nargs == 1)
+ {
+ info->fprintf_func (info->stream, "RA");
+ return;
+ }
+
+ for (i = 0; i < currInsn->nargs; i++)
+ {
+ processing_argument_number = i;
+
+ /* For "bal (ra), disp17" instruction only. */
+ if ((IS_INSN_MNEMONIC ("bal")) && (i == 0) && instruction->size == 2)
+ {
+ info->fprintf_func (info->stream, "(ra),");
+ continue;
+ }
+
+ if ((INST_HAS_REG_LIST) && (i == 2))
+ info->fprintf_func (info->stream, "RA");
+ else
+ print_arg (&currInsn->arg[i], memaddr, info);
+
+ if ((i != currInsn->nargs - 1) && (!IS_INSN_MNEMONIC ("b")))
+ info->fprintf_func (info->stream, ",");
+ }
+}
+
+/* Build the instruction's arguments. */
+
+static void
+make_instruction (void)
+{
+ int i;
+ unsigned int shift;
+
+ for (i = 0; i < currInsn.nargs; i++)
+ {
+ argument a;
+
+ memset (&a, 0, sizeof (a));
+ a.type = getargtype (instruction->operands[i].op_type);
+ a.size = getbits (instruction->operands[i].op_type);
+ shift = instruction->operands[i].shift;
+
+ make_argument (&a, shift);
+ currInsn.arg[i] = a;
+ }
+
+ /* Calculate instruction size (in bytes). */
+ currInsn.size = instruction->size + (size_changed ? 1 : 0);
+ /* Now in bits. */
+ currInsn.size *= 2;
+}
+
+/* Retrieve a single word from a given memory address. */
+
+static wordU
+get_word_at_PC (bfd_vma memaddr, struct disassemble_info *info)
+{
+ bfd_byte buffer[4];
+ int status;
+ wordU insn = 0;
+
+ status = info->read_memory_func (memaddr, buffer, 2, info);
+
+ if (status == 0)
+ insn = (wordU) bfd_getl16 (buffer);
+
+ return insn;
+}
+
+/* Retrieve multiple words (3) from a given memory address. */
+
+static void
+get_words_at_PC (bfd_vma memaddr, struct disassemble_info *info)
+{
+ int i;
+ bfd_vma mem;
+
+ for (i = 0, mem = memaddr; i < 3; i++, mem += 2)
+ words[i] = get_word_at_PC (mem, info);
+
+ allWords =
+ ((ULONGLONG) words[0] << 32) + ((unsigned long) words[1] << 16) + words[2];
+}
+
+/* Prints the instruction by calling print_arguments after proper matching. */
+
+int
+print_insn_cr16 (bfd_vma memaddr, struct disassemble_info *info)
+{
+ int is_decoded; /* Nonzero means instruction has a match. */
+
+ /* Initialize global variables. */
+ imm4flag = 0;
+ size_changed = 0;
+
+ /* Retrieve the encoding from current memory location. */
+ get_words_at_PC (memaddr, info);
+ /* Find a matching opcode in table. */
+ is_decoded = match_opcode ();
+ /* If found, print the instruction's mnemonic and arguments. */
+ if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0)
+ {
+ if (strneq (instruction->mnemonic, "cinv", 4))
+ info->fprintf_func (info->stream,"%s", getcinvstring ((char *)instruction->mnemonic));
+ else
+ info->fprintf_func (info->stream, "%s", instruction->mnemonic);
+
+ if (((currInsn.nargs = get_number_of_operands ()) != 0)
+ && ! (IS_INSN_MNEMONIC ("b")))
+ info->fprintf_func (info->stream, "\t");
+ make_instruction ();
+ /* For push/pop/pushrtn with RA instructions. */
+ if ((INST_HAS_REG_LIST) && ((words[0] >> 7) & 0x1))
+ currInsn.nargs +=1;
+ print_arguments (&currInsn, memaddr, info);
+ return currInsn.size;
+ }
+
+ /* No match found. */
+ info->fprintf_func (info->stream,"%s ",ILLEGAL);
+ return 2;
+}
diff --git a/opcodes/cr16-opc.c b/opcodes/cr16-opc.c
new file mode 100644
index 0000000..8b8bf2f
--- /dev/null
+++ b/opcodes/cr16-opc.c
@@ -0,0 +1,611 @@
+/* cr16-opc.c -- Table of opcodes for the CR16 processor.
+ Copyright 2007 Free Software Foundation, Inc.
+ Contributed by M R Swami Reddy (MR.Swami.Reddy@nsc.com)
+
+ This file is part of GAS, GDB and the GNU binutils.
+
+ GAS, GDB, and GNU binutils is free software; you can redistribute it
+ and/or modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2, or (at your
+ option) any later version.
+
+ GAS, GDB, and GNU binutils are distributed in the hope that they will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#include <stdio.h>
+#include "libiberty.h"
+#include "symcat.h"
+#include "opcode/cr16.h"
+
+const inst cr16_instruction[] =
+{
+/* Create an arithmetic instruction - INST[bw]. */
+#define ARITH_BYTE_INST(NAME, OPC, OP1) \
+ /* opc8 imm4 r */ \
+ {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \
+ /* opc8 imm16 r */ \
+ {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \
+ /* opc8 r r */ \
+ {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
+
+/* for Logincal operations, allow unsinged imm16 also */
+#define ARITH1_BYTE_INST(NAME, OPC, OP1) \
+ /* opc8 imm16 r */ \
+ {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
+
+
+ ARITH_BYTE_INST ("andb", 0x20, uimm16),
+ ARITH1_BYTE_INST ("andb", 0x20, imm16),
+ ARITH_BYTE_INST ("andw", 0x22, uimm16),
+ ARITH1_BYTE_INST ("andw", 0x22, imm16),
+
+ ARITH_BYTE_INST ("orb", 0x24, uimm16),
+ ARITH1_BYTE_INST ("orb", 0x24, imm16),
+ ARITH_BYTE_INST ("orw", 0x26, uimm16),
+ ARITH1_BYTE_INST ("orw", 0x26, imm16),
+
+ ARITH_BYTE_INST ("xorb", 0x28, uimm16),
+ ARITH1_BYTE_INST ("xorb", 0x28, imm16),
+ ARITH_BYTE_INST ("xorw", 0x2A, uimm16),
+ ARITH1_BYTE_INST ("xorw", 0x2A, imm16),
+
+ ARITH_BYTE_INST ("addub", 0x2C, imm16),
+ ARITH_BYTE_INST ("adduw", 0x2E, imm16),
+ ARITH_BYTE_INST ("addb", 0x30, imm16),
+ ARITH_BYTE_INST ("addw", 0x32, imm16),
+ ARITH_BYTE_INST ("addcb", 0x34, imm16),
+ ARITH_BYTE_INST ("addcw", 0x36, imm16),
+
+ ARITH_BYTE_INST ("subb", 0x38, imm16),
+ ARITH_BYTE_INST ("subw", 0x3A, imm16),
+ ARITH_BYTE_INST ("subcb", 0x3C, imm16),
+ ARITH_BYTE_INST ("subcw", 0x3E, imm16),
+
+ ARITH_BYTE_INST ("cmpb", 0x50, imm16),
+ ARITH_BYTE_INST ("cmpw", 0x52, imm16),
+
+ ARITH_BYTE_INST ("movb", 0x58, imm16),
+ ARITH_BYTE_INST ("movw", 0x5A, imm16),
+
+ ARITH_BYTE_INST ("mulb", 0x64, imm16),
+ ARITH_BYTE_INST ("mulw", 0x66, imm16),
+
+#define ARITH_BYTE_INST1(NAME, OPC) \
+ /* opc8 r r */ \
+ {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
+
+ ARITH_BYTE_INST1 ("movxb", 0x5C),
+ ARITH_BYTE_INST1 ("movzb", 0x5D),
+ ARITH_BYTE_INST1 ("mulsb", 0x0B),
+
+#define ARITH_BYTE_INST2(NAME, OPC) \
+ /* opc8 r rp */ \
+ {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regp,16}}}
+
+ ARITH_BYTE_INST2 ("movxw", 0x5E),
+ ARITH_BYTE_INST2 ("movzw", 0x5F),
+ ARITH_BYTE_INST2 ("mulsw", 0x62),
+ ARITH_BYTE_INST2 ("muluw", 0x63),
+
+/* Create an arithmetic instruction - INST[d]- with 3 types. */
+#define ARITH_INST_D(NAME, OPC) \
+ /* opc8 imm4 rp */ \
+ {NAME, 1, OPC, 24, ARITH_INS, {{uimm4_1,20}, {regp,16}}}, \
+ /* opc8 imm16 rp */ \
+ {NAME, 2, (OPC<<4)+0xB, 20, ARITH_INS, {{imm16,0}, {regp,16}}}, \
+ /* opc8 rp rp */ \
+ {NAME, 1, OPC+1, 24, ARITH_INS, {{regp,20}, {regp,16}}}
+
+/* Create an arithmetic instruction - INST[d]-20 bit types. */
+#define ARITH_INST20(NAME, OPC) \
+ /* opc8 uimm20 rp */ \
+ {NAME, 2, OPC, 24, ARITH_INS, {{uimm20,0}, {regp,20}}}
+
+/* Create an arithmetic instruction - INST[d]-32 bit types. */
+#define ARITH_INST32(NAME, OPC, OP1) \
+ /* opc12 imm32 rp */ \
+ {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0}, {regp,16}}}
+
+/* Create an arithmetic instruction - INST[d]-32bit types(reg pairs).*/
+#define ARITH_INST32RP(NAME, OPC) \
+ /* opc24 rp rp */ \
+ {NAME, 2, OPC, 12, ARITH_INS, {{regp,4}, {regp,0}}}
+
+ ARITH_INST_D ("movd", 0x54),
+ ARITH_INST20 ("movd", 0x05),
+ ARITH_INST32 ("movd", 0x007, imm32),
+ ARITH_INST_D ("addd", 0x60),
+ ARITH_INST20 ("addd", 0x04),
+ ARITH_INST32 ("addd", 0x002, imm32),
+ ARITH_INST32 ("subd", 0x003, imm32),
+ ARITH_INST32RP ("subd", 0x0014C),
+ ARITH_INST_D ("cmpd", 0x56),
+ ARITH_INST32 ("cmpd", 0x009, imm32),
+ ARITH_INST32 ("andd", 0x004, uimm32),
+ ARITH_INST32RP ("andd", 0x0014B),
+ ARITH_INST32 ("ord", 0x005, uimm32),
+ ARITH_INST32RP ("ord", 0x00149),
+ ARITH_INST32 ("xord", 0x006, uimm32),
+ ARITH_INST32RP ("xord", 0x0014A),
+
+/* Create a shift instruction. */
+#define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
+ /* opc imm r */ \
+ {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
+ /* opc imm r */ \
+ {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
+ /* opc r r */ \
+ {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
+
+ SHIFT_INST_A("ashub", 0x80, 0x41, 23, imm4, regr),
+ SHIFT_INST_A("ashud", 0x26, 0x48, 25, imm6, regp),
+ SHIFT_INST_A("ashuw", 0x42, 0x45, 24, imm5, regr),
+
+#define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
+ /* opc imm r */ \
+ {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
+ /* opc r r */ \
+ {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {OP2,16}}}
+
+ SHIFT_INST_L("lshb", 0x13, 0x44, 23, imm4, regr),
+ SHIFT_INST_L("lshd", 0x25, 0x47, 25, imm6, regp),
+ SHIFT_INST_L("lshw", 0x49, 0x46, 24, imm5, regr),
+
+/* Create a conditional branch instruction. */
+#define BRANCH_INST(NAME, OPC) \
+ /* opc4 c4 dispe9 */ \
+ {NAME, 1, OPC, 28, BRANCH_INS, {{cc,20}, {dispe9,16}}}, \
+ /* opc4 c4 disps17 */ \
+ {NAME, 2, ((OPC<<4)+0x8), 24, BRANCH_INS, {{cc,20}, {disps17,0}}}, \
+ /* opc4 c4 disps25 */ \
+ {NAME, 3, (OPC<<4), 16 , BRANCH_INS, {{cc,4}, {disps25,16}}}
+
+ BRANCH_INST ("b", 0x1),
+
+/* Create a 'Branch if Equal to 0' instruction. */
+#define BRANCH_NEQ_INST(NAME, OPC) \
+ /* opc8 disps5 r */ \
+ {NAME, 1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {disps5,20}}}
+
+ BRANCH_NEQ_INST ("beq0b", 0x0C),
+ BRANCH_NEQ_INST ("bne0b", 0x0D),
+ BRANCH_NEQ_INST ("beq0w", 0x0E),
+ BRANCH_NEQ_INST ("bne0w", 0x0F),
+
+
+/* Create an instruction using a single register operand. */
+#define REG1_INST(NAME, OPC) \
+ /* opc8 c4 r */ \
+ {NAME, 1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
+
+#define REGP1_INST(NAME, OPC) \
+ /* opc8 c4 r */ \
+ {NAME, 1, OPC, 20, NO_TYPE_INS, {{regp,16}}}
+
+/* Same as REG1_INST, with additional FLAGS. */
+#define REG1_FLAG_INST(NAME, OPC, FLAGS) \
+ /* opc8 c4 r */ \
+ {NAME, 1, OPC, 20, NO_TYPE_INS | FLAGS, {{regp,16}}}
+
+ /* JCond instructions */
+ REGP1_INST ("jeq", 0x0A0),
+ REGP1_INST ("jne", 0x0A1),
+ REGP1_INST ("jcs", 0x0A2),
+ REGP1_INST ("jcc", 0x0A3),
+ REGP1_INST ("jhi", 0x0A4),
+ REGP1_INST ("jls", 0x0A5),
+ REGP1_INST ("jgt", 0x0A6),
+ REGP1_INST ("jle", 0x0A7),
+ REGP1_INST ("jfs", 0x0A8),
+ REGP1_INST ("jfc", 0x0A9),
+ REGP1_INST ("jlo", 0x0AA),
+ REGP1_INST ("jhs", 0x0AB),
+ REGP1_INST ("jlt", 0x0AC),
+ REGP1_INST ("jge", 0x0AD),
+ REGP1_INST ("jump", 0x0AE),
+ REGP1_INST ("jusr", 0x0AF),
+
+ /* SCond instructions */
+ REG1_INST ("seq", 0x080),
+ REG1_INST ("sne", 0x081),
+ REG1_INST ("scs", 0x082),
+ REG1_INST ("scc", 0x083),
+ REG1_INST ("shi", 0x084),
+ REG1_INST ("sls", 0x085),
+ REG1_INST ("sgt", 0x086),
+ REG1_INST ("sle", 0x087),
+ REG1_INST ("sfs", 0x088),
+ REG1_INST ("sfc", 0x089),
+ REG1_INST ("slo", 0x08A),
+ REG1_INST ("shs", 0x08B),
+ REG1_INST ("slt", 0x08C),
+ REG1_INST ("sge", 0x08D),
+
+
+/* Create an instruction using two register operands. */
+#define REG3_INST(NAME, OPC) \
+ /* opc24 r r rp */ \
+ {NAME, 2, OPC, 12, NO_TYPE_INS, {{regr,4}, {regr,0}, {regp,8}}}
+
+ /* MULTIPLY INSTRUCTIONS */
+ REG3_INST ("macqw", 0x0014d),
+ REG3_INST ("macuw", 0x0014e),
+ REG3_INST ("macsw", 0x0014f),
+
+/* Create a branch instruction. */
+#define BR_INST(NAME, OPC) \
+ /* opc12 ra disps25 */ \
+ {NAME, 2, OPC, 24, NO_TYPE_INS, {{rra,0}, {disps25,0}}}
+
+#define BR_INST_RP(NAME, OPC) \
+ /* opc8 rp disps25 */ \
+ {NAME, 3, OPC, 12, NO_TYPE_INS, {{regp,4}, {disps25,16}}}
+
+ BR_INST ("bal", 0xC0),
+ BR_INST_RP ("bal", 0x00102),
+
+#define REGPP2_INST(NAME, OPC) \
+ /* opc16 rp rp */ \
+ {NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}}
+ /* Jump and link instructions. */
+ REGP1_INST ("jal",0x00D),
+ REGPP2_INST ("jal",0x00148),
+
+
+/* Instructions including a register list (opcode is represented as a mask). */
+#define REGLIST_INST(NAME, OPC, TYPE) \
+ /* opc7 r count3 RA */ \
+ {NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \
+ /* opc8 r count3 */ \
+ {NAME, 1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}}, \
+ /* opc12 RA */ \
+ {NAME, 1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}}
+
+ REGLIST_INST ("push", 0x01, (NO_TYPE_INS | REG_LIST)),
+ REGLIST_INST ("pop", 0x02, (NO_TYPE_INS | REG_LIST)),
+ REGLIST_INST ("popret", 0x03, (NO_TYPE_INS | REG_LIST)),
+
+ {"loadm", 1, 0x14, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
+ {"loadmp", 1, 0x15, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
+ {"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
+ {"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
+
+ /* Processor Regsiter Manipulation instructions */
+ /* opc16 reg, preg */
+ {"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
+ /* opc16 regp, pregp */
+ {"lprd", 2, 0x00141, 12, NO_TYPE_INS, {{regp,0}, {pregrp,4}}},
+ /* opc16 preg, reg */
+ {"spr", 2, 0x00142, 12, NO_TYPE_INS, {{pregr,4}, {regr,0}}},
+ /* opc16 pregp, regp */
+ {"sprd", 2, 0x00143, 12, NO_TYPE_INS, {{pregrp,4}, {regp,0}}},
+
+ /* Miscellaneous. */
+ /* opc12 ui4 */
+ {"excp", 1, 0x00C, 20, NO_TYPE_INS, {{uimm4,16}}},
+
+/* Create a bit-b instruction. */
+#define CSTBIT_INST_B(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
+ /* opcNN iN abs20 */ \
+ {NAME, 2, (OPC3+1), 23, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
+ /* opcNN iN abs24 */ \
+ {NAME, 3, (OPC2+3), 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \
+ /* opcNN iN (Rindex)abs20 */ \
+ {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rindex7_abs20,0}}}, \
+ /* opcNN iN (prp) disps14(RPbase) */ \
+ {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \
+ /* opcNN iN disps20(Rbase) */ \
+ {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \
+ /* opcNN iN (rp) disps0(RPbase) */ \
+ {NAME, 1, OPC3-2, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \
+ /* opcNN iN (rp) disps16(RPBase) */ \
+ {NAME, 2, OPC3, 23, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \
+ /* opcNN iN (rp) disps20(RPBase) */ \
+ {NAME, 3, (OPC2+1), 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \
+ /* opcNN iN rrp (Rindex)disps20(RPbase) */ \
+ {NAME, 3, (OPC2+2), 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}}
+
+ CSTBIT_INST_B ("cbitb", uimm3, 0x68, 0x00104, 0xD6, 0x1AA),
+ CSTBIT_INST_B ("sbitb", uimm3, 0x70, 0x00108, 0xE6, 0x1CA),
+ CSTBIT_INST_B ("tbitb", uimm3, 0x78, 0x0010C, 0xF6, 0x1EA),
+
+/* Create a bit-w instruction. */
+#define CSTBIT_INST_W(NAME, OP, OPC1, OPC2, OPC3, OPC4) \
+ /* opcNN iN abs20 */ \
+ {NAME, 2, OPC1+6, 24, CSTBIT_INS, {{OP,20},{abs20,0}}}, \
+ /* opcNN iN abs24 */ \
+ {NAME, 3, OPC2+3, 12, CSTBIT_INS, {{OP,4},{abs24,16}}}, \
+ /* opcNN iN (Rindex)abs20 */ \
+ {NAME, 2, OPC3, 25, CSTBIT_INS, {{OP,20}, {rindex8_abs20,0}}}, \
+ /* opcNN iN (prp) disps14(RPbase) */ \
+ {NAME, 2, OPC4, 22, CSTBIT_INS, {{OP,4},{rpindex_disps14,0}}}, \
+ /* opcNN iN disps20(Rbase) */ \
+ {NAME, 3, OPC2, 12, CSTBIT_INS, {{OP,4}, {rbase_disps20,16}}}, \
+ /* opcNN iN (rp) disps0(RPbase) */ \
+ {NAME, 1, OPC1+5, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps0,16}}}, \
+ /* opcNN iN (rp) disps16(RPBase) */ \
+ {NAME, 2, OPC1, 24, CSTBIT_INS, {{OP,20}, {rpbase_disps16,0}}}, \
+ /* opcNN iN (rp) disps20(RPBase) */ \
+ {NAME, 3, OPC2+1, 12, CSTBIT_INS, {{OP,4}, {rpbase_disps20,16}}}, \
+ /* opcNN iN rrp (Rindex)disps20(RPbase) */ \
+ {NAME, 3, OPC2+2, 12, CSTBIT_INS, {{OP,4}, {rpindex_disps20,16}}}
+
+ CSTBIT_INST_W ("cbitw", uimm4, 0x69, 0x00114, 0x36, 0x1AB),
+ CSTBIT_INST_W ("sbitw", uimm4, 0x71, 0x00118, 0x3A, 0x1CB),
+ CSTBIT_INST_W ("tbitw", uimm4, 0x79, 0x0011C, 0x3E, 0x1EB),
+
+ /* tbit cnt */
+ {"tbit", 1, 0x06, 24, CSTBIT_INS, {{uimm4,20}, {regr,16}}},
+ /* tbit reg reg */
+ {"tbit", 1, 0x07, 24, CSTBIT_INS, {{regr,20}, {regr,16}}},
+
+
+/* Load instructions (from memory to register). */
+#define LD_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_S, OP_D) \
+ /* opc8 reg abs20 */ \
+ {NAME, 2, OPC3, 24, LD_STOR_INS, {{abs20,0}, {OP_D,20}}}, \
+ /* opc20 reg abs24 */ \
+ {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{abs24,16}, {OP_D,4}}}, \
+ /* opc7 reg rindex8_abs20 */ \
+ {NAME, 2, OPC5, 25, LD_STOR_INS, {{rindex8_abs20,0}, {OP_D,20}}}, \
+ /* opc4 reg disps4(RPbase) */ \
+ {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,24}, {OP_D,20}}}, \
+ /* opcNN reg disps0(RPbase) */ \
+ {NAME, 1, OPC2, 24, LD_STOR_INS, {{rpindex_disps0,0}, {OP_D,20}}}, \
+ /* opc reg disps14(RPbase) */ \
+ {NAME, 2, OPC4, 22, LD_STOR_INS, {{rpindex_disps14,0}, {OP_D,20}}}, \
+ /* opc reg -disps20(Rbase) */ \
+ {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{rbase_dispe20,16}, {OP_D,4}}}, \
+ /* opc reg disps20(Rbase) */ \
+ {NAME, 3, OPC1, 12, LD_STOR_INS, {{rbase_disps20,16}, {OP_D,4}}}, \
+ /* opc reg (rp) disps16(RPbase) */ \
+ {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{rpbase_disps16,0}, {OP_D,20}}}, \
+ /* opc16 reg (rp) disps20(RPbase) */ \
+ {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{rpbase_disps20,16}, {OP_D,4}}}, \
+ /* op reg (rp) -disps20(RPbase) */ \
+ {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{rpbase_dispe20,16}, {OP_D,4}}}, \
+ /* opc reg rrp (Rindex)disps20(RPbase) */ \
+ {NAME, 3, (OPC1+2), 12, LD_STOR_INS, {{rpindex_disps20,16}, {OP_D,4}}}
+
+ LD_REG_INST ("loadb", 0x00124, 0xBE, 0x88, 0x219, 0x45, rpbase_disps4, regr),
+ LD_REG_INST ("loadd", 0x00128, 0xAE, 0x87, 0x21A, 0x46, rpbase_dispe4, regp),
+ LD_REG_INST ("loadw", 0x0012C, 0x9E, 0x89, 0x21B, 0x47, rpbase_dispe4, regr),
+
+/* Store instructions (from reg to memory). */
+#define ST_REG_INST(NAME, OPC1, OPC2, OPC3, OPC4, OPC5, OP_D, OP_S) \
+ /* opc8 reg abs20 */ \
+ {NAME, 2, OPC3, 24, LD_STOR_INS, {{OP_S,20}, {abs20,0}}}, \
+ /* opc20 reg abs24 */ \
+ {NAME, 3, OPC1+3, 12, LD_STOR_INS, {{OP_S,4}, {abs24,16}}}, \
+ /* opc7 reg rindex8_abs20 */ \
+ {NAME, 2, OPC5, 25, LD_STOR_INS, {{OP_S,20}, {rindex8_abs20,0}}}, \
+ /* opc4 reg disps4(RPbase) */ \
+ {NAME, 1, (OPC2>>4), 28, LD_STOR_INS, {{OP_S,20}, {OP_D,24}}}, \
+ /* opcNN reg disps0(RPbase) */ \
+ {NAME, 1, OPC2, 24, LD_STOR_INS, {{OP_S,20}, {rpindex_disps0,0}}}, \
+ /* opc reg disps14(RPbase) */ \
+ {NAME, 2, OPC4, 22, LD_STOR_INS, {{OP_S,20}, {rpindex_disps14,0}}}, \
+ /* opc reg -disps20(Rbase) */ \
+ {NAME, 3, OPC1+0x60, 12, LD_STOR_INS, {{OP_S,4}, {rbase_dispe20,16}}}, \
+ /* opc reg disps20(Rbase) */ \
+ {NAME, 3, OPC1, 12, LD_STOR_INS, {{OP_S,4}, {rbase_disps20,16}}}, \
+ /* opc reg disps16(RPbase) */ \
+ {NAME, 2, OPC2+1, 24, LD_STOR_INS, {{OP_S,20}, {rpbase_disps16,0}}}, \
+ /* opc16 reg disps20(RPbase) */ \
+ {NAME, 3, OPC1+1, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_disps20,16}}}, \
+ /* op reg (rp) -disps20(RPbase) */ \
+ {NAME, 3, OPC1+0x61, 12, LD_STOR_INS, {{OP_S,4}, {rpbase_dispe20,16}}}, \
+ /* opc reg rrp (Rindex)disps20(RPbase) */ \
+ {NAME, 3, OPC1+2, 12, LD_STOR_INS, {{OP_S,4}, {rpindex_disps20,16}}}
+
+
+/* Store instructions (from imm to memory). */
+#define ST_IMM_INST(NAME, OPC1, OPC2, OPC3, OPC4) \
+ /* opcNN iN abs20 */ \
+ {NAME, 2, OPC1, 24, LD_STOR_INS, {{uimm4,20},{abs20,0}}}, \
+ /* opcNN iN abs24 */ \
+ {NAME, 3, OPC2+3, 12, LD_STOR_INS, {{uimm4,4},{abs24,16}}}, \
+ /* opcNN iN (Rindex)abs20 */ \
+ {NAME, 2, OPC3, 25, LD_STOR_INS, {{uimm4,20}, {rindex8_abs20,0}}}, \
+ /* opcNN iN (prp) disps14(RPbase) */ \
+ {NAME, 2, OPC4, 22, LD_STOR_INS, {{uimm4,4},{rpindex_disps14,0}}}, \
+ /* opcNN iN (rp) disps0(RPbase) */ \
+ {NAME, 1, OPC1+1, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps0,16}}}, \
+ /* opcNN iN disps20(Rbase) */ \
+ {NAME, 3, OPC2, 12, LD_STOR_INS, {{uimm4,4}, {rbase_disps20,16}}}, \
+ /* opcNN iN (rp) disps16(RPBase) */ \
+ {NAME, 2, OPC1+2, 24, LD_STOR_INS, {{uimm4,20}, {rpbase_disps16,0}}}, \
+ /* opcNN iN (rp) disps20(RPBase) */ \
+ {NAME, 3, OPC2+1, 12, LD_STOR_INS, {{uimm4,4}, {rpbase_disps20,16}}}, \
+ /* opcNN iN rrp (Rindex)disps20(RPbase) */ \
+ {NAME, 3, OPC2+2, 12, LD_STOR_INS, {{uimm4,4}, {rpindex_disps20,16}}}
+
+ ST_REG_INST ("storb", 0x00134, 0xFE, 0xC8, 0x319, 0x65, rpbase_disps4, regr),
+ ST_IMM_INST ("storb", 0x81, 0x00120, 0x42, 0x218),
+ ST_REG_INST ("stord", 0x00138, 0xEE, 0xC7, 0x31A, 0x66, rpbase_dispe4, regp),
+ ST_REG_INST ("storw", 0x0013C, 0xDE, 0xC9, 0x31B, 0x67, rpbase_dispe4, regr),
+ ST_IMM_INST ("storw", 0xC1, 0x00130, 0x62, 0x318),
+
+/* Create instruction with no operands. */
+#define NO_OP_INST(NAME, OPC) \
+ /* opc16 */ \
+ {NAME, 1, OPC, 16, 0, {{0, 0}}}
+
+ NO_OP_INST ("cinv[i]", 0x000A),
+ NO_OP_INST ("cinv[i,u]", 0x000B),
+ NO_OP_INST ("cinv[d]", 0x000C),
+ NO_OP_INST ("cinv[d,u]", 0x000D),
+ NO_OP_INST ("cinv[d,i]", 0x000E),
+ NO_OP_INST ("cinv[d,i,u]", 0x000F),
+ NO_OP_INST ("nop", 0x2C00),
+ NO_OP_INST ("retx", 0x0003),
+ NO_OP_INST ("di", 0x0004),
+ NO_OP_INST ("ei", 0x0005),
+ NO_OP_INST ("wait", 0x0006),
+ NO_OP_INST ("eiwait", 0x0007),
+
+ {NULL, 0, 0, 0, 0, {{0, 0}}}
+};
+
+const unsigned int cr16_num_opcodes = ARRAY_SIZE (cr16_instruction);
+
+/* Macro to build a reg_entry, which have an opcode image :
+ For example :
+ REG(u4, 0x84, CR16_U_REGTYPE)
+ is interpreted as :
+ {"u4", u4, 0x84, CR16_U_REGTYPE} */
+#define REG(NAME, N, TYPE) {STRINGX(NAME), {NAME}, N, TYPE}
+
+#define REGP(NAME, BNAME, N, TYPE) {STRINGX(NAME), {BNAME}, N, TYPE}
+
+const reg_entry cr16_regtab[] =
+{ /* Build a general purpose register r<N>. */
+#define REG_R(N) REG(CONCAT2(r,N), N, CR16_R_REGTYPE)
+
+ REG_R(0), REG_R(1), REG_R(2), REG_R(3),
+ REG_R(4), REG_R(5), REG_R(6), REG_R(7),
+ REG_R(8), REG_R(9), REG_R(10), REG_R(11),
+ REG_R(12), REG_R(13), REG_R(14), REG_R(15),
+ REG(r12_L, 12, CR16_R_REGTYPE),
+ REG(r13_L, 13, CR16_R_REGTYPE),
+ REG(ra, 0xe, CR16_R_REGTYPE),
+ REG(sp, 0xf, CR16_R_REGTYPE),
+ REG(sp_L, 0xf, CR16_R_REGTYPE),
+ REG(RA, 0xe, CR16_R_REGTYPE),
+};
+
+const reg_entry cr16_regptab[] =
+{ /* Build a general purpose register r<N>. */
+
+#define REG_RP(M,N) REGP((CONCAT2(r,M),CONCAT2(r,N)), CONCAT2(r,N), N, CR16_RP_REGTYPE)
+
+ REG_RP(1,0), REG_RP(2,1), REG_RP(3,2), REG_RP(4,3),
+ REG_RP(5,4), REG_RP(6,5), REG_RP(7,6), REG_RP(8,7),
+ REG_RP(9,8), REG_RP(10,9), REG_RP(11,10), REG_RP(12,11),
+ REG((r12), 0xc, CR16_RP_REGTYPE),
+ REG((r13), 0xd, CR16_RP_REGTYPE),
+ //REG((r14), 0xe, CR16_RP_REGTYPE),
+ REG((ra), 0xe, CR16_RP_REGTYPE),
+ REG((sp), 0xf, CR16_RP_REGTYPE),
+};
+
+
+const unsigned int cr16_num_regs = ARRAY_SIZE (cr16_regtab) ;
+const unsigned int cr16_num_regps = ARRAY_SIZE (cr16_regptab) ;
+
+const reg_entry cr16_pregtab[] =
+{
+/* Build a processor register. */
+ REG(dbs, 0x0, CR16_P_REGTYPE),
+ REG(dsr, 0x1, CR16_P_REGTYPE),
+ REG(dcrl, 0x2, CR16_P_REGTYPE),
+ REG(dcrh, 0x3, CR16_P_REGTYPE),
+ REG(car0l, 0x4, CR16_P_REGTYPE),
+ REG(car0h, 0x5, CR16_P_REGTYPE),
+ REG(car1l, 0x6, CR16_P_REGTYPE),
+ REG(car1h, 0x7, CR16_P_REGTYPE),
+ REG(cfg, 0x8, CR16_P_REGTYPE),
+ REG(psr, 0x9, CR16_P_REGTYPE),
+ REG(intbasel, 0xa, CR16_P_REGTYPE),
+ REG(intbaseh, 0xb, CR16_P_REGTYPE),
+ REG(ispl, 0xc, CR16_P_REGTYPE),
+ REG(isph, 0xd, CR16_P_REGTYPE),
+ REG(uspl, 0xe, CR16_P_REGTYPE),
+ REG(usph, 0xf, CR16_P_REGTYPE),
+};
+
+const reg_entry cr16_pregptab[] =
+{
+ REG(dbs, 0, CR16_P_REGTYPE),
+ REG(dsr, 1, CR16_P_REGTYPE),
+ REG(dcr, 2, CR16_P_REGTYPE),
+ REG(car0, 4, CR16_P_REGTYPE),
+ REG(car1, 6, CR16_P_REGTYPE),
+ REG(cfg, 8, CR16_P_REGTYPE),
+ REG(psr, 9, CR16_P_REGTYPE),
+ REG(intbase, 10, CR16_P_REGTYPE),
+ REG(isp, 12, CR16_P_REGTYPE),
+ REG(usp, 14, CR16_P_REGTYPE),
+};
+
+const unsigned int cr16_num_pregs = ARRAY_SIZE (cr16_pregtab);
+const unsigned int cr16_num_pregps = ARRAY_SIZE (cr16_pregptab);
+
+const char *cr16_b_cond_tab[]=
+{
+ "eq","ne","cs","cc","hi","ls","gt","le","fs","fc",
+ "lo","hs","lt","ge","r", "???"
+};
+
+const unsigned int cr16_num_cc = ARRAY_SIZE (cr16_b_cond_tab);
+
+/* CR16 operands table. */
+const operand_entry cr16_optab[] =
+{
+ /* Index 0 is dummy, so we can count the instruction's operands. */
+ {0, nullargs, 0}, /* dummy */
+ {3, arg_ic, OP_SIGNED}, /* imm3 */
+ {4, arg_ic, OP_SIGNED}, /* imm4 */
+ {5, arg_ic, OP_SIGNED}, /* imm5 */
+ {6, arg_ic, OP_SIGNED}, /* imm6 */
+ {16, arg_ic, OP_SIGNED}, /* imm16 */
+ {20, arg_ic, OP_SIGNED}, /* imm20 */
+ {32, arg_ic, OP_SIGNED}, /* imm32 */
+ {3, arg_ic, OP_UNSIGNED}, /* uimm3 */
+ {3, arg_ic, OP_UNSIGNED|OP_DEC}, /* uimm3_1 */
+ {4, arg_ic, OP_UNSIGNED}, /* uimm4 */
+ {4, arg_ic, OP_UNSIGNED|OP_ESC}, /* uimm4_1 */
+ {5, arg_ic, OP_UNSIGNED}, /* uimm5 */
+ {16, arg_ic, OP_UNSIGNED}, /* uimm16 */
+ {20, arg_ic, OP_UNSIGNED}, /* uimm20 */
+ {32, arg_ic, OP_UNSIGNED}, /* uimm32 */
+ {5, arg_c, OP_EVEN|OP_SHIFT_DEC|OP_SIGNED}, /* disps5 */
+ {16, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps17 */
+ {24, arg_c, OP_EVEN|OP_UNSIGNED}, /* disps25 */
+ {8, arg_c, OP_EVEN|OP_UNSIGNED}, /* dispe9 */
+ {20, arg_c, OP_UNSIGNED|OP_ABS20}, /* abs20 */
+ {24, arg_c, OP_UNSIGNED|OP_ABS24}, /* abs24 */
+ {4, arg_rp, 0}, /* rra */
+ {4, arg_rbase, 0}, /* rbase */
+ {20, arg_cr, OP_UNSIGNED}, /* rbase_disps20 */
+ {21, arg_cr, OP_NEG}, /* rbase_dispe20 */
+ {0, arg_crp, 0}, /* rpbase_disps0 */
+ {4, arg_crp, OP_EVEN|OP_SHIFT|OP_UNSIGNED|OP_ESC1},/* rpbase_dispe4 */
+ {4, arg_crp, OP_UNSIGNED|OP_ESC1}, /* rpbase_disps4 */
+ {16, arg_crp, OP_UNSIGNED}, /* rpbase_disps16 */
+ {20, arg_crp, OP_UNSIGNED}, /* rpbase_disps20 */
+ {21, arg_crp, OP_NEG}, /* rpbase_dispe20 */
+ {20, arg_idxr, OP_UNSIGNED}, /* rindex7_abs20 */
+ {20, arg_idxr, OP_UNSIGNED}, /* rindex8_abs20 */
+ {0, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps0 */
+ {14, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps14 */
+ {20, arg_idxrp, OP_UNSIGNED}, /* rpindex_disps20 */
+ {4, arg_r, 0}, /* regr */
+ {4, arg_rp, 0}, /* reg pair */
+ {4, arg_pr, 0}, /* proc reg */
+ {4, arg_prp, 0}, /* 32 bit proc reg */
+ {4, arg_cc, OP_UNSIGNED} /* cc - code */
+};
+
+
+/* CR16 traps/interrupts. */
+const trap_entry cr16_traps[] =
+{
+ {"svc", 5}, {"dvz", 6}, {"flg", 7}, {"bpt", 8}, {"trc", 9},
+ {"und", 10}, {"iad", 12}, {"dbg",14}, {"ise",15}
+};
+
+const unsigned int cr16_num_traps = ARRAY_SIZE (cr16_traps);
+
+/* CR16 instructions that don't have arguments. */
+const char * cr16_no_op_insn[] =
+{
+ "cinv[i]", "cinv[i,u]", "cinv[d]", "cinv[d,u]", "cinv[d,i]", "cinv[d,i,u]",
+ "di", "ei", "eiwait", "nop", "retx", "wait", NULL
+};
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index bd40dd6..df98dc2 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -25,6 +25,7 @@
#define ARCH_arm
#define ARCH_avr
#define ARCH_bfin
+#define ARCH_cr16
#define ARCH_cris
#define ARCH_crx
#define ARCH_d10v
@@ -129,6 +130,11 @@ disassembler (abfd)
disassemble = print_insn_bfin;
break;
#endif
+#ifdef ARCH_cr16
+ case bfd_arch_cr16:
+ disassemble = print_insn_cr16;
+ break;
+#endif
#ifdef ARCH_cris
case bfd_arch_cris:
disassemble = cris_get_disassembler (abfd);
generated by cgit v1.1 at 2024-11-27 23:18:08 +0000