diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/s390-opc.c | 19 | ||||
| -rw-r--r-- | opcodes/s390-opc.txt | 2 |
3 files changed, 19 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e364b4b..17c69d4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> + + * s390-opc.c (J12_12, J24_24): New macros. + (INSTR_MII_UPI): Rename to INSTR_MII_UPP. + (MASK_MII_UPI): Rename to MASK_MII_UPP. + * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction. + 2013-07-04 Alan Modra <amodra@gmail.com> * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu. diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index adfc5b4..70b99db 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -217,20 +217,23 @@ const struct s390_operand s390_operands[] = /* PC-relative address operands. */ -#define J12_12 69 /* PC relative offset at 12 */ +#define J12_12 69 /* 12 bit PC relative offset at 12 */ { 12, 12, S390_OPERAND_PCREL }, -#define J16_16 70 /* PC relative offset at 16 */ +#define J16_16 70 /* 16 bit PC relative offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J16_32 71 /* PC relative offset at 16 */ +#define J16_32 71 /* 16 bit PC relative offset at 32 */ { 16, 32, S390_OPERAND_PCREL }, -#define J32_16 72 /* PC relative offset at 16 */ +#define J24_24 72 /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +#define J32_16 73 /* 32 bit PC relative offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, + /* Conditional mask operands. */ -#define M_16OPT 73 /* 4 bit optional mask starting at 16 */ +#define M_16OPT 74 /* 4 bit optional mask starting at 16 */ { 4, 16, S390_OPERAND_OPTIONAL }, -#define M_20OPT 74 /* 4 bit optional mask starting at 20 */ +#define M_20OPT 75 /* 4 bit optional mask starting at 20 */ { 4, 20, S390_OPERAND_OPTIONAL }, }; @@ -284,7 +287,7 @@ const struct s390_operand s390_operands[] = #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ #define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ -#define INSTR_MII_UPI 6, { U4_8,J12_12,I24_24 } /* e.g. bprp */ +#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ @@ -446,7 +449,7 @@ const struct s390_operand s390_operands[] = #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } -#define MASK_MII_UPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt index 65068de..71369ec 100644 --- a/opcodes/s390-opc.txt +++ b/opcodes/s390-opc.txt @@ -1126,7 +1126,7 @@ e560 tbegin SIL_RDU "transaction begin" zEC12 zarch e561 tbeginc SIL_RDU "constrained transaction begin" zEC12 zarch b2f8 tend S_00 "transaction end" zEC12 zarch c7 bpp SMI_U0RDP "branch prediction preload" zEC12 zarch -c5 bprp MII_UPI "branch prediction relative preload" zEC12 zarch +c5 bprp MII_UPP "branch prediction relative preload" zEC12 zarch b2e8 ppa RRF_U0RR "perform processor assist" zEC12 zarch b2fa niai IE_UU "next instruction access intent" zEC12 zarch b98f crdte RRF_RMRR "compare and replace DAT table entry" zEC12 zarch |