diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/arc-dis.c | 1499 | ||||
| -rw-r--r-- | opcodes/arc-dis.h | 45 | ||||
| -rw-r--r-- | opcodes/arc-ext.c | 558 | ||||
| -rw-r--r-- | opcodes/arc-ext.h | 90 | ||||
| -rw-r--r-- | opcodes/arc-fxi.h | 1317 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 2661 | ||||
| -rw-r--r-- | opcodes/arc-regs.h | 403 | ||||
| -rw-r--r-- | opcodes/arc-tbl.h | 18198 |
9 files changed, 21958 insertions, 2824 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 124ead7..c9c576f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> + + * arc-dis.c: Revamped file for ARC support + * arc-dis.h: Likewise. + * arc-ext.c: Likewise. + * arc-ext.h: Likewise. + * arc-opc.c: Likewise. + * arc-fxi.h: New file. + * arc-regs.h: Likewise. + * arc-tbl.h: Likewise. + 2015-10-02 Yao Qi <yao.qi@linaro.org> * aarch64-dis.c (disas_aarch64_insn): Remove static. Change diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index 617511b..516fc22 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -1,6 +1,7 @@ /* Instruction printing code for the ARC. Copyright (C) 1994-2015 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) This file is part of libopcodes. @@ -20,1207 +21,539 @@ MA 02110-1301, USA. */ #include "sysdep.h" -#include "libiberty.h" +#include <stdio.h> +#include <assert.h> #include "dis-asm.h" #include "opcode/arc.h" -#include "elf-bfd.h" -#include "elf/arc.h" -#include "opintl.h" - -#include <stdarg.h> #include "arc-dis.h" #include "arc-ext.h" -#ifndef dbg -#define dbg (0) -#endif -/* Classification of the opcodes for the decoder to print - the instructions. */ +/* Globals variables. */ -typedef enum +static const char * const regnames[64] = { - CLASS_A4_ARITH, - CLASS_A4_OP3_GENERAL, - CLASS_A4_FLAG, - /* All branches other than JC. */ - CLASS_A4_BRANCH, - CLASS_A4_JC , - /* All loads other than immediate - indexed loads. */ - CLASS_A4_LD0, - CLASS_A4_LD1, - CLASS_A4_ST, - CLASS_A4_SR, - /* All single operand instructions. */ - CLASS_A4_OP3_SUBOPC3F, - CLASS_A4_LR -} a4_decoding_class; - -#define BIT(word,n) ((word) & (1 << n)) -#define BITS(word,s,e) (((word) >> s) & ((1 << (e + 1 - s)) - 1)) + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink", + + "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", + "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", + "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", + "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl" +}; + +/* Macros section. */ + +#ifdef DEBUG +# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args) +#else +# define pr_debug(fmt, args...) +#endif + +#define ARRANGE_ENDIAN(info, buf) \ + (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \ + : bfd_getb32 (buf)) + +#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \ + (s + (sizeof (word) * 8 - 1 - e))) #define OPCODE(word) (BITS ((word), 27, 31)) #define FIELDA(word) (BITS ((word), 21, 26)) #define FIELDB(word) (BITS ((word), 15, 20)) #define FIELDC(word) (BITS ((word), 9, 14)) -/* FIELD D is signed. */ -#define FIELDD(word) ((BITS ((word), 0, 8) ^ 0x100) - 0x100) - -#define PUT_NEXT_WORD_IN(a) \ - do \ - { \ - if (is_limm == 1 && !NEXT_WORD (1)) \ - mwerror (state, _("Illegal limm reference in last instruction!\n")); \ - a = state->words[1]; \ - } \ - while (0) - -#define CHECK_FLAG_COND_NULLIFY() \ - do \ - { \ - if (is_shimm == 0) \ - { \ - flag = BIT (state->words[0], 8); \ - state->nullifyMode = BITS (state->words[0], 5, 6); \ - cond = BITS (state->words[0], 0, 4); \ - } \ - } \ - while (0) - -#define CHECK_COND() \ - do \ - { \ - if (is_shimm == 0) \ - cond = BITS (state->words[0], 0, 4); \ - } \ - while (0) - -#define CHECK_FIELD(field) \ - do \ - { \ - if (field == 62) \ - { \ - is_limm++; \ - field##isReg = 0; \ - PUT_NEXT_WORD_IN (field); \ - limm_value = field; \ - } \ - else if (field > 60) \ - { \ - field##isReg = 0; \ - is_shimm++; \ - flag = (field == 61); \ - field = FIELDD (state->words[0]); \ - } \ - } \ - while (0) - -#define CHECK_FIELD_A() \ - do \ - { \ - fieldA = FIELDA (state->words[0]); \ - if (fieldA > 60) \ - { \ - fieldAisReg = 0; \ - fieldA = 0; \ - } \ - } \ - while (0) - -#define CHECK_FIELD_B() \ - do \ - { \ - fieldB = FIELDB (state->words[0]); \ - CHECK_FIELD (fieldB); \ - } \ - while (0) - -#define CHECK_FIELD_C() \ - do \ - { \ - fieldC = FIELDC (state->words[0]); \ - CHECK_FIELD (fieldC); \ - } \ - while (0) - -#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257)) -#define IS_REG(x) (field##x##isReg) -#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","") -#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[") -#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]") -#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]") -#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","") -#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",") -#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","") -#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \ - (IS_REG (x) ? cb1"%r"ca1 : \ - usesAuxReg ? cb"%a"ca : \ - IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) -#define WRITE_FORMAT_RB() strcat (formatString, "]") -#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) -#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); - -#define NEXT_WORD(x) (offset += 4, state->words[x]) - -#define add_target(x) (state->targets[state->tcnt++] = (x)) - -static char comment_prefix[] = "\t; "; - -static const char * -core_reg_name (struct arcDisState * state, int val) -{ - if (state->coreRegName) - return (*state->coreRegName)(state->_this, val); - return 0; -} +#define OPCODE_AC(word) (BITS ((word), 11, 15)) -static const char * -aux_reg_name (struct arcDisState * state, int val) -{ - if (state->auxRegName) - return (*state->auxRegName)(state->_this, val); - return 0; -} +/* Functions implementation. */ -static const char * -cond_code_name (struct arcDisState * state, int val) +static bfd_vma +bfd_getm32 (unsigned int data) { - if (state->condCodeName) - return (*state->condCodeName)(state->_this, val); - return 0; -} + bfd_vma value = 0; -static const char * -instruction_name (struct arcDisState * state, - int op1, - int op2, - int * flags) -{ - if (state->instName) - return (*state->instName)(state->_this, op1, op2, flags); - return 0; -} - -static void -mwerror (struct arcDisState * state, const char * msg) -{ - if (state->err != 0) - (*state->err)(state->_this, (msg)); + value = ((data & 0xff00) | (data & 0xff)) << 16; + value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16; + return value; } -static const char * -post_address (struct arcDisState * state, int addr) +static int +special_flag_p (const char *opname, + const char *flgname) { - static char id[3 * ARRAY_SIZE (state->addresses)]; - int j, i = state->acnt; + const struct arc_flag_special *flg_spec; + size_t len; + unsigned i, j, flgidx; - if (i < ((int) ARRAY_SIZE (state->addresses))) + for (i = 0; i < arc_num_flag_special; i++) { - state->addresses[i] = addr; - ++state->acnt; - j = i*3; - id[j+0] = '@'; - id[j+1] = '0'+i; - id[j+2] = 0; - - return id + j; - } - return ""; -} - -static void -arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...) -{ - char *bp; - const char *p; - int size, leading_zero, regMap[2]; - va_list ap; - - va_start (ap, format); - - bp = buf; - *bp = 0; - p = format; - regMap[0] = 0; - regMap[1] = 0; - - while (1) - switch (*p++) - { - case 0: - goto DOCOMM; /* (return) */ - default: - *bp++ = p[-1]; - break; - case '%': - size = 0; - leading_zero = 0; - RETRY: ; - switch (*p++) - { - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - /* size. */ - size = p[-1] - '0'; - if (size == 0) - leading_zero = 1; /* e.g. %08x */ - while (*p >= '0' && *p <= '9') - { - size = size * 10 + *p - '0'; - p++; - } - goto RETRY; - } -#define inc_bp() bp = bp + strlen (bp) - - case 'h': - { - unsigned u = va_arg (ap, int); - - /* Hex. We can change the format to 0x%08x in - one place, here, if we wish. - We add underscores for easy reading. */ - if (u > 65536) - sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); - else - sprintf (bp, "0x%x", u); - inc_bp (); - } - break; - case 'X': case 'x': - { - int val = va_arg (ap, int); - - if (size != 0) - if (leading_zero) - sprintf (bp, "%0*x", size, val); - else - sprintf (bp, "%*x", size, val); - else - sprintf (bp, "%x", val); - inc_bp (); - } - break; - case 'd': - { - int val = va_arg (ap, int); + flg_spec = &arc_flag_special_cases[i]; + len = strlen (flg_spec->name); - if (size != 0) - sprintf (bp, "%*d", size, val); - else - sprintf (bp, "%d", val); - inc_bp (); - } - break; - case 'r': - { - /* Register. */ - int val = va_arg (ap, int); - -#define REG2NAME(num, name) case num: sprintf (bp, ""name); \ - regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; + if (strncmp (opname, flg_spec->name, len) != 0) + continue; - switch (val) - { - REG2NAME (26, "gp"); - REG2NAME (27, "fp"); - REG2NAME (28, "sp"); - REG2NAME (29, "ilink1"); - REG2NAME (30, "ilink2"); - REG2NAME (31, "blink"); - REG2NAME (60, "lp_count"); - default: - { - const char * ext; - - ext = core_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - sprintf (bp,"r%d",val); - } - break; - } - inc_bp (); - } break; - - case 'a': - { - /* Aux Register. */ - int val = va_arg (ap, int); - -#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; - - switch (val) - { - AUXREG2NAME (0x0, "status"); - AUXREG2NAME (0x1, "semaphore"); - AUXREG2NAME (0x2, "lp_start"); - AUXREG2NAME (0x3, "lp_end"); - AUXREG2NAME (0x4, "identity"); - AUXREG2NAME (0x5, "debug"); - default: - { - const char *ext; - - ext = aux_reg_name (state, val); - if (ext) - sprintf (bp, "%s", ext); - else - arc_sprintf (state, bp, "%h", val); - } - break; - } - inc_bp (); - } - break; - - case 's': - { - sprintf (bp, "%s", va_arg (ap, char *)); - inc_bp (); - } - break; - - default: - fprintf (stderr, "?? format %c\n", p[-1]); - break; - } - } - - DOCOMM: *bp = 0; - va_end (ap); -} - -static void -write_comments_(struct arcDisState * state, - int shimm, - int is_limm, - long limm_value) -{ - if (state->commentBuffer != 0) - { - int i; - - if (is_limm) + /* Found potential special case instruction. */ + for (j=0;; ++j) { - const char *name = post_address (state, limm_value + shimm); + flgidx = flg_spec->flags[j]; + if (flgidx == 0) + break; /* End of the array. */ - if (*name != 0) - WRITE_COMMENT (name); - } - for (i = 0; i < state->commNum; i++) - { - if (i == 0) - strcpy (state->commentBuffer, comment_prefix); - else - strcat (state->commentBuffer, ", "); - strcat (state->commentBuffer, state->comm[i]); + if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0) + return 1; } } + return 0; } -#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value) -#define write_comments() write_comments2 (0) - -static const char *condName[] = -{ - /* 0..15. */ - "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , - "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" -}; +/* Disassemble ARC instructions. */ -static void -write_instr_name_(struct arcDisState * state, - const char * instrName, - int cond, - int condCodeIsPartOfName, - int flag, - int signExtend, - int addrWriteBack, - int directMem) +static int +print_insn_arc (bfd_vma memaddr, + struct disassemble_info *info) { - strcpy (state->instrBuffer, instrName); + bfd_byte buffer[4]; + unsigned int lowbyte, highbyte; + int status; + unsigned int i; + int insnLen = 0; + unsigned insn[2], isa_mask; + const unsigned char *opidx; + const unsigned char *flgidx; + const struct arc_opcode *opcode; + const char *instrName; + int flags; + bfd_boolean need_comma; + bfd_boolean open_braket; - if (cond > 0) - { - const char *cc = 0; - if (!condCodeIsPartOfName) - strcat (state->instrBuffer, "."); + lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0); + highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1); - if (cond < 16) - cc = condName[cond]; - else - cc = cond_code_name (state, cond); + switch (info->mach) + { + case bfd_mach_arc_arc700: + isa_mask = ARC_OPCODE_ARC700; + break; - if (!cc) - cc = "???"; + case bfd_mach_arc_arc600: + isa_mask = ARC_OPCODE_ARC600; + break; - strcat (state->instrBuffer, cc); + case bfd_mach_arc_arcv2: + default: + isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM; + break; } - if (flag) - strcat (state->instrBuffer, ".f"); - - switch (state->nullifyMode) + /* Read the insn into a host word. */ + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) { - case BR_exec_always: - strcat (state->instrBuffer, ".d"); - break; - case BR_exec_when_jump: - strcat (state->instrBuffer, ".jd"); - break; + (*info->memory_error_func) (status, memaddr, info); + return -1; } - if (signExtend) - strcat (state->instrBuffer, ".x"); - - if (addrWriteBack) - strcat (state->instrBuffer, ".a"); - - if (directMem) - strcat (state->instrBuffer, ".di"); -} - -#define write_instr_name() \ - do \ - { \ - write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \ - flag, signExtend, addrWriteBack, directMem); \ - formatString[0] = '\0'; \ - } \ - while (0) - -enum -{ - op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, - op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, - op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, - op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 -}; - -extern disassemble_info tm_print_insn_info; - -static int -dsmOneArcInst (bfd_vma addr, struct arcDisState * state) -{ - int condCodeIsPartOfName = 0; - a4_decoding_class decodingClass; - const char * instrName; - int repeatsOp = 0; - int fieldAisReg = 1; - int fieldBisReg = 1; - int fieldCisReg = 1; - int fieldA; - int fieldB; - int fieldC = 0; - int flag = 0; - int cond = 0; - int is_shimm = 0; - int is_limm = 0; - long limm_value = 0; - int signExtend = 0; - int addrWriteBack = 0; - int directMem = 0; - int is_linked = 0; - int offset = 0; - int usesAuxReg = 0; - int flags; - int ignoreFirstOpd; - char formatString[60]; - - state->instructionLen = 4; - state->nullifyMode = BR_exec_when_no_jump; - state->opWidth = 12; - state->isBranch = 0; - - state->_mem_load = 0; - state->_ea_present = 0; - state->_load_len = 0; - state->ea_reg1 = no_reg; - state->ea_reg2 = no_reg; - state->_offset = 0; - - if (! NEXT_WORD (0)) - return 0; - - state->_opcode = OPCODE (state->words[0]); - instrName = 0; - decodingClass = CLASS_A4_ARITH; /* default! */ - repeatsOp = 0; - condCodeIsPartOfName=0; - state->commNum = 0; - state->tcnt = 0; - state->acnt = 0; - state->flow = noflow; - ignoreFirstOpd = 0; - - if (state->commentBuffer) - state->commentBuffer[0] = '\0'; - - switch (state->_opcode) + if (info->section + && !(info->section->flags & SEC_CODE)) { - case op_LD0: - switch (BITS (state->words[0],1,2)) + /* Sort of data section, just print a 32 bit number. */ + insnLen = 4; + status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info); + if (status != 0) { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (0[3])"; - state->flow = invalid_instr; - break; + (*info->memory_error_func) (status, memaddr + 2, info); + return -1; } - decodingClass = CLASS_A4_LD0; - break; + insn[0] = ARRANGE_ENDIAN (info, buffer); + (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]); + return insnLen; + } - case op_LD1: - if (BIT (state->words[0],13)) - { - instrName = "lr"; - decodingClass = CLASS_A4_LR; - } - else + if ((((buffer[lowbyte] & 0xf8) > 0x38) + && ((buffer[lowbyte] & 0xf8) != 0x48)) + || ((info->mach == bfd_mach_arc_arcv2) + && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly. */ + ) + { + /* This is a short instruction. */ + insnLen = 2; + insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte]; + } + else + { + insnLen = 4; + + /* This is a long instruction: Read the remaning 2 bytes. */ + status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info); + if (status != 0) { - switch (BITS (state->words[0], 10, 11)) - { - case 0: - instrName = "ld"; - state->_load_len = 4; - break; - case 1: - instrName = "ldb"; - state->_load_len = 1; - break; - case 2: - instrName = "ldw"; - state->_load_len = 2; - break; - default: - instrName = "??? (1[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = CLASS_A4_LD1; + (*info->memory_error_func) (status, memaddr + 2, info); + return -1; } - break; + insn[0] = ARRANGE_ENDIAN (info, buffer); + } + + /* This variable may be set by the instruction decoder. It suggests + the number of bytes objdump should display on a single line. If + the instruction decoder sets this, it should always set it to + the same value in order to get reasonable looking output. */ + info->bytes_per_line = 8; + + /* The next two variables control the way objdump displays the raw data. + For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the + output will look like this: + 00: 00000000 00000000 + with the chunks displayed according to "display_endian". */ + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + + /* Set some defaults for the insn info. */ + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + /* FIXME to be moved in dissasemble_init_for_target. */ + info->disassembler_needs_relocs = TRUE; + + /* Find the first match in the opcode table. */ + for (i = 0; i < arc_num_opcodes; i++) + { + bfd_boolean invalid = FALSE; + + opcode = &arc_opcodes[i]; - case op_ST: - if (BIT (state->words[0], 25)) + if (ARC_SHORT (opcode->mask) && (insnLen == 2)) { - instrName = "sr"; - decodingClass = CLASS_A4_SR; + if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0])) + continue; } - else + else if (!ARC_SHORT (opcode->mask) && (insnLen == 4)) { - switch (BITS (state->words[0], 22, 23)) - { - case 0: - instrName = "st"; - break; - case 1: - instrName = "stb"; - break; - case 2: - instrName = "stw"; - break; - default: - instrName = "??? (2[3])"; - state->flow = invalid_instr; - break; - } - decodingClass = CLASS_A4_ST; + if (OPCODE (opcode->opcode) != OPCODE (insn[0])) + continue; } - break; + else + continue; + + if ((insn[0] ^ opcode->opcode) & opcode->mask) + continue; - case op_3: - decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */ - switch (FIELDC (state->words[0])) + if (!(opcode->cpu & isa_mask)) + continue; + + /* Possible candidate, check the operands. */ + for (opidx = opcode->operands; *opidx; opidx++) { - case 0: - instrName = "flag"; - decodingClass = CLASS_A4_FLAG; - break; - case 1: - instrName = "asr"; - break; - case 2: - instrName = "lsr"; - break; - case 3: - instrName = "ror"; - break; - case 4: - instrName = "rrc"; - break; - case 5: - instrName = "sexb"; - break; - case 6: - instrName = "sexw"; - break; - case 7: - instrName = "extb"; - break; - case 8: - instrName = "extw"; - break; - case 0x3f: - { - decodingClass = CLASS_A4_OP3_SUBOPC3F; - switch (FIELDD (state->words[0])) - { - case 0: - instrName = "brk"; - break; - case 1: - instrName = "sleep"; - break; - case 2: - instrName = "swi"; - break; - default: - instrName = "???"; - state->flow=invalid_instr; - break; - } - } - break; - - /* ARC Extension Library Instructions - NOTE: We assume that extension codes are these instrs. */ - default: - instrName = instruction_name (state, - state->_opcode, - FIELDC (state->words[0]), - &flags); - if (!instrName) + int value; + const struct arc_operand *operand = &arc_operands[*opidx]; + + if (operand->flags & ARC_OPERAND_FAKE) + continue; + + if (operand->extract) + value = (*operand->extract) (insn[0], &invalid); + else + value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); + + /* Check for LIMM indicator. If it is there, then make sure + we pick the right format. */ + if (operand->flags & ARC_OPERAND_IR + && !(operand->flags & ARC_OPERAND_LIMM)) { - instrName = "???"; - state->flow = invalid_instr; + if ((value == 0x3E && insnLen == 4) + || (value == 0x1E && insnLen == 2)) + { + invalid = TRUE; + break; + } } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; - break; } - break; - case op_BC: - instrName = "b"; - case op_BLC: - if (!instrName) - instrName = "bl"; - case op_LPC: - if (!instrName) - instrName = "lp"; - case op_JC: - if (!instrName) + /* Check the flags. */ + for (flgidx = opcode->flags; *flgidx; flgidx++) { - if (BITS (state->words[0],9,9)) + /* Get a valid flag class. */ + const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; + const unsigned *flgopridx; + int foundA = 0, foundB = 0; + + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { - instrName = "jl"; - is_linked = 1; + const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx]; + unsigned int value; + + value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1); + if (value == flg_operand->code) + foundA = 1; + if (value) + foundB = 1; } - else + if (!foundA && foundB) { - instrName = "j"; - is_linked = 0; + invalid = TRUE; + break; } } - condCodeIsPartOfName = 1; - decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH ); - state->isBranch = 1; - break; - case op_ADD: - case op_ADC: - case op_AND: - repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); + if (invalid) + continue; - switch (state->_opcode) - { - case op_ADD: - instrName = (repeatsOp ? "asl" : "add"); - break; - case op_ADC: - instrName = (repeatsOp ? "rlc" : "adc"); - break; - case op_AND: - instrName = (repeatsOp ? "mov" : "and"); - break; - } - break; + /* The instruction is valid. */ + goto found; + } - case op_SUB: instrName = "sub"; - break; - case op_SBC: instrName = "sbc"; - break; - case op_OR: instrName = "or"; - break; - case op_BIC: instrName = "bic"; - break; + /* No instruction found. Try the extenssions. */ + instrName = arcExtMap_instName (OPCODE (insn[0]), insn[0], &flags); + if (instrName) + { + opcode = &arc_opcodes[0]; + (*info->fprintf_func) (info->stream, "%s", instrName); + goto print_flags; + } - case op_XOR: - if (state->words[0] == 0x7fffffff) - { - /* NOP encoded as xor -1, -1, -1. */ - instrName = "nop"; - decodingClass = CLASS_A4_OP3_SUBOPC3F; - } + if (insnLen == 2) + (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]); + else + (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]); + + info->insn_type = dis_noninsn; + return insnLen; + + found: + /* Print the mnemonic. */ + (*info->fprintf_func) (info->stream, "%s", opcode->name); + + /* Preselect the insn class. */ + switch (opcode->class) + { + case BRANCH: + case JUMP: + if (!strncmp (opcode->name, "bl", 2) + || !strncmp (opcode->name, "jl", 2)) + info->insn_type = dis_jsr; else - instrName = "xor"; + info->insn_type = dis_branch; + break; + case MEMORY: + info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */ break; - default: - instrName = instruction_name (state,state->_opcode,0,&flags); - /* if (instrName) printf("FLAGS=0x%x\n", flags); */ - if (!instrName) - { - instrName = "???"; - state->flow=invalid_instr; - } - if (flags & IGNORE_FIRST_OPD) - ignoreFirstOpd = 1; + info->insn_type = dis_nonbranch; break; } - fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ - flag = cond = is_shimm = is_limm = 0; - state->nullifyMode = BR_exec_when_no_jump; /* 0 */ - signExtend = addrWriteBack = directMem = 0; - usesAuxReg = 0; + pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode); - switch (decodingClass) + print_flags: + /* Now extract and print the flags. */ + for (flgidx = opcode->flags; *flgidx; flgidx++) { - case CLASS_A4_ARITH: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - if (!repeatsOp) - CHECK_FIELD_C (); - CHECK_FLAG_COND_NULLIFY (); - - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - WRITE_NOP_COMMENT (); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - } - else - { - WRITE_FORMAT_x (B); - if (!repeatsOp) - WRITE_FORMAT_COMMA_x (C); - arc_sprintf (state, state->operandBuffer, formatString, - fieldB, fieldC); - } - write_comments (); - break; - - case CLASS_A4_OP3_GENERAL: - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); + /* Get a valid flag class. */ + const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx]; + const unsigned *flgopridx; - write_instr_name (); - if (!ignoreFirstOpd) - { - WRITE_FORMAT_x (A); - WRITE_FORMAT_COMMA_x (B); - WRITE_NOP_COMMENT (); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB); - } - else + for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx) { - WRITE_FORMAT_x (B); - arc_sprintf (state, state->operandBuffer, formatString, fieldB); - } - write_comments (); - break; + const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx]; + unsigned int value; - case CLASS_A4_FLAG: - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); - flag = 0; /* This is the FLAG instruction -- it's redundant. */ - - write_instr_name (); - WRITE_FORMAT_x (B); - arc_sprintf (state, state->operandBuffer, formatString, fieldB); - write_comments (); - break; + if (!flg_operand->favail) + continue; - case CLASS_A4_BRANCH: - fieldA = BITS (state->words[0],7,26) << 2; - fieldA = (fieldA << 10) >> 10; /* Make it signed. */ - fieldA += addr + 4; - CHECK_FLAG_COND_NULLIFY (); - flag = 0; + value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1); + if (value == flg_operand->code) + { + /* FIXME!: print correctly nt/t flag. */ + if (!special_flag_p (opcode->name, flg_operand->name)) + (*info->fprintf_func) (info->stream, "."); + else if (info->insn_type == dis_dref) + { + switch (flg_operand->name[0]) + { + case 'b': + info->data_size = 1; + break; + case 'h': + case 'w': + info->data_size = 2; + break; + default: + info->data_size = 4; + break; + } + } + (*info->fprintf_func) (info->stream, "%s", flg_operand->name); + } - write_instr_name (); - /* This address could be a label we know. Convert it. */ - if (state->_opcode != op_LPC /* LP */) - { - add_target (fieldA); /* For debugger. */ - state->flow = state->_opcode == op_BLC /* BL */ - ? direct_call - : direct_jump; - /* indirect calls are achieved by "lr blink,[status]; - lr dest<- func addr; j [dest]" */ + if (flg_operand->name[0] == 'd' + && flg_operand->name[1] == 0) + info->branch_delay_insns = 1; } + } - strcat (formatString, "%s"); /* Address/label name. */ - arc_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldA)); - write_comments (); - break; + if (opcode->operands[0] != 0) + (*info->fprintf_func) (info->stream, "\t"); - case CLASS_A4_JC: - /* For op_JC -- jump to address specified. - Also covers jump and link--bit 9 of the instr. word - selects whether linked, thus "is_linked" is set above. */ - fieldA = 0; - CHECK_FIELD_B (); - CHECK_FLAG_COND_NULLIFY (); + need_comma = FALSE; + open_braket = FALSE; - if (!fieldBisReg) - { - fieldAisReg = 0; - fieldA = (fieldB >> 25) & 0x7F; /* Flags. */ - fieldB = (fieldB & 0xFFFFFF) << 2; - state->flow = is_linked ? direct_call : direct_jump; - add_target (fieldB); - /* Screwy JLcc requires .jd mode to execute correctly - but we pretend it is .nd (no delay slot). */ - if (is_linked && state->nullifyMode == BR_exec_when_jump) - state->nullifyMode = BR_exec_when_no_jump; - } - else - { - state->flow = is_linked ? indirect_call : indirect_jump; - /* We should also treat this as indirect call if NOT linked - but the preceding instruction was a "lr blink,[status]" - and we have a delay slot with "add blink,blink,2". - For now we can't detect such. */ - state->register_for_indirect_jump = fieldB; - } + /* Now extract and print the operands. */ + for (opidx = opcode->operands; *opidx; opidx++) + { + const struct arc_operand *operand = &arc_operands[*opidx]; + int value; - write_instr_name (); - strcat (formatString, - IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */ - if (fieldA != 0) + if (open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x (A); + (*info->fprintf_func) (info->stream, "]"); + open_braket = FALSE; + continue; } - if (IS_REG (B)) - arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); - else - arc_sprintf (state, state->operandBuffer, formatString, - post_address (state, fieldB), fieldA); - write_comments (); - break; - - case CLASS_A4_LD0: - /* LD instruction. - B and C can be regs, or one (both?) can be limm. */ - CHECK_FIELD_A (); - CHECK_FIELD_B (); - CHECK_FIELD_C (); - if (dbg) - printf ("5:b reg %d %d c reg %d %d \n", - fieldBisReg,fieldB,fieldCisReg,fieldC); - state->_offset = 0; - state->_ea_present = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - else - state->_offset += fieldB; - if (fieldCisReg) - state->ea_reg2 = fieldC; - else - state->_offset += fieldC; - state->_mem_load = 1; - - directMem = BIT (state->words[0], 5); - addrWriteBack = BIT (state->words[0], 3); - signExtend = BIT (state->words[0], 0); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(A); - if (fieldBisReg || fieldB != 0) - WRITE_FORMAT_x_COMMA (B); - else - fieldB = fieldC; - WRITE_FORMAT_x_RB (C); - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; + /* Only take input from real operands. */ + if ((operand->flags & ARC_OPERAND_FAKE) + && !(operand->flags & ARC_OPERAND_BRAKET)) + continue; - case CLASS_A4_LD1: - /* LD instruction. */ - CHECK_FIELD_B (); - CHECK_FIELD_A (); - fieldC = FIELDD (state->words[0]); - - if (dbg) - printf ("6:b reg %d %d c 0x%x \n", - fieldBisReg, fieldB, fieldC); - state->_ea_present = 1; - state->_offset = fieldC; - state->_mem_load = 1; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldC) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. */ + if (operand->extract) + value = (*operand->extract) (insn[0], (int *) NULL); else - state->_offset += fieldB, state->_ea_present = 0; - - directMem = BIT (state->words[0],14); - addrWriteBack = BIT (state->words[0],12); - signExtend = BIT (state->words[0],9); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB (A); - if (!fieldBisReg) { - fieldB = state->_offset; - WRITE_FORMAT_x_RB (B); - } - else - { - WRITE_FORMAT_x (B); - if (fieldC != 0 && !BIT (state->words[0],13)) + if (operand->flags & ARC_OPERAND_ALIGNED32) { - fieldCisReg = 0; - WRITE_FORMAT_COMMA_x_RB (C); + value = (insn[0] >> operand->shift) + & ((1 << (operand->bits - 2)) - 1); + value = value << 2; } else - WRITE_FORMAT_RB (); + { + value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); + } + if (operand->flags & ARC_OPERAND_SIGNED) + { + int signbit = 1 << (operand->bits - 1); + value = (value ^ signbit) - signbit; + } } - arc_sprintf (state, state->operandBuffer, formatString, - fieldA, fieldB, fieldC); - write_comments (); - break; - case CLASS_A4_ST: - /* ST instruction. */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - fieldA = FIELDD(state->words[0]); /* shimm */ - - /* [B,A offset] */ - if (dbg) printf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); - state->_ea_present = 1; - state->_offset = fieldA; - if (fieldBisReg) - state->ea_reg1 = fieldB; - /* Field B is either a shimm (same as fieldA) or limm (different!) - Say ea is not present, so only one of us will do the name lookup. - (for is_limm we do the name translation here). */ - else - state->_offset += fieldB, state->_ea_present = 0; + if (operand->flags & ARC_OPERAND_IGNORE + && (operand->flags & ARC_OPERAND_IR + && value == -1)) + continue; - directMem = BIT (state->words[0], 26); - addrWriteBack = BIT (state->words[0], 24); + if (need_comma) + (*info->fprintf_func) (info->stream, ","); - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(C); - - if (!fieldBisReg) + if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET)) { - fieldB = state->_offset; - WRITE_FORMAT_x_RB (B); + (*info->fprintf_func) (info->stream, "["); + open_braket = TRUE; + need_comma = FALSE; + continue; } - else + + /* Read the limm operand, if required. */ + if (operand->flags & ARC_OPERAND_LIMM + && !(operand->flags & ARC_OPERAND_DUPLICATE)) { - WRITE_FORMAT_x (B); - if (fieldBisReg && fieldA != 0) + status = (*info->read_memory_func) (memaddr + insnLen, buffer, + 4, info); + if (status != 0) { - fieldAisReg = 0; - WRITE_FORMAT_COMMA_x_RB(A); + (*info->memory_error_func) (status, memaddr + insnLen, info); + return -1; } - else - WRITE_FORMAT_RB(); + insn[1] = ARRANGE_ENDIAN (info, buffer); } - arc_sprintf (state, state->operandBuffer, formatString, - fieldC, fieldB, fieldA); - write_comments2 (fieldA); - break; - - case CLASS_A4_SR: - /* SR instruction */ - CHECK_FIELD_B(); - CHECK_FIELD_C(); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB(C); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x (B); - WRITE_FORMAT_RB (); - arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); - write_comments (); - break; - case CLASS_A4_OP3_SUBOPC3F: - write_instr_name (); - state->operandBuffer[0] = '\0'; - break; - - case CLASS_A4_LR: - /* LR instruction */ - CHECK_FIELD_A (); - CHECK_FIELD_B (); - - write_instr_name (); - WRITE_FORMAT_x_COMMA_LB (A); - /* Try to print B as an aux reg if it is not a core reg. */ - usesAuxReg = 1; - WRITE_FORMAT_x (B); - WRITE_FORMAT_RB (); - arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); - write_comments (); - break; + /* Print the operand as directed by the flags. */ + if (operand->flags & ARC_OPERAND_IR) + { + assert (value >=0 && value < 64); + (*info->fprintf_func) (info->stream, "%s", regnames[value]); + if (operand->flags & ARC_OPERAND_TRUNCATE) + (*info->fprintf_func) (info->stream, "%s", regnames[value+1]); + } + else if (operand->flags & ARC_OPERAND_LIMM) + { + (*info->fprintf_func) (info->stream, "%#x", insn[1]); + if (info->insn_type == dis_branch + || info->insn_type == dis_jsr) + info->target = (bfd_vma) insn[1]; + } + else if (operand->flags & ARC_OPERAND_PCREL) + { + /* PCL relative. */ + if (info->flags & INSN_HAS_RELOC) + memaddr = 0; + (*info->print_address_func) ((memaddr & ~3) + value, info); - default: - mwerror (state, "Bad decoding class in ARC disassembler"); - break; + info->target = (bfd_vma) (memaddr & ~3) + value; + } + else if (operand->flags & ARC_OPERAND_SIGNED) + (*info->fprintf_func) (info->stream, "%d", value); + else + if (operand->flags & ARC_OPERAND_TRUNCATE + && !(operand->flags & ARC_OPERAND_ALIGNED32) + && !(operand->flags & ARC_OPERAND_ALIGNED16) + && value > 0 && value <= 14) + (*info->fprintf_func) (info->stream, "r13-%s", + regnames[13 + value - 1]); + else + (*info->fprintf_func) (info->stream, "%#x", value); + + need_comma = TRUE; + + /* Adjust insn len. */ + if (operand->flags & ARC_OPERAND_LIMM + && !(operand->flags & ARC_OPERAND_DUPLICATE)) + insnLen += 4; } - state->_cond = cond; - return state->instructionLen = offset; -} - - -/* Returns the name the user specified core extension register. */ - -static const char * -_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_coreRegName (regval); + return insnLen; } -/* Returns the name the user specified AUX extension register. */ -static const char * -_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) -{ - return arcExtMap_auxRegName(regval); -} - -/* Returns the name the user specified condition code name. */ - -static const char * -_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) +disassembler_ftype +arc_get_disassembler (bfd *abfd) { - return arcExtMap_condCodeName(regval); -} + /* Read the extenssion insns and registers, if any. */ + build_ARC_extmap (abfd); + dump_ARC_extmap (); -/* Returns the name the user specified extension instruction. */ - -static const char * -_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) -{ - return arcExtMap_instName(majop, minop, flags); + return print_insn_arc; } -/* Decode an instruction returning the size of the instruction - in bytes or zero if unrecognized. */ +/* Disassemble ARC instructions. Used by debugger. */ -static int -decodeInstr (bfd_vma address, /* Address of this instruction. */ - disassemble_info * info) +struct arcDisState +arcAnalyzeInstr (bfd_vma memaddr, + struct disassemble_info *info) { - int status; - bfd_byte buffer[4]; - struct arcDisState s; /* ARC Disassembler state. */ - void *stream = info->stream; /* Output stream. */ - fprintf_ftype func = info->fprintf_func; - - memset (&s, 0, sizeof(struct arcDisState)); - - /* read first instruction */ - status = (*info->read_memory_func) (address, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, address, info); - return 0; - } - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[0] = bfd_getl32(buffer); - else - s.words[0] = bfd_getb32(buffer); - /* Always read second word in case of limm. */ - - /* We ignore the result since last insn may not have a limm. */ - status = (*info->read_memory_func) (address + 4, buffer, 4, info); - if (info->endian == BFD_ENDIAN_LITTLE) - s.words[1] = bfd_getl32(buffer); - else - s.words[1] = bfd_getb32(buffer); - - s._this = &s; - s.coreRegName = _coreRegName; - s.auxRegName = _auxRegName; - s.condCodeName = _condCodeName; - s.instName = _instName; - - /* Disassemble. */ - dsmOneArcInst (address, & s); - - /* Display the disassembly instruction. */ - (*func) (stream, "%08lx ", s.words[0]); - (*func) (stream, " "); - (*func) (stream, "%-10s ", s.instrBuffer); - - if (__TRANSLATION_REQUIRED (s)) - { - bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; - - (*info->print_address_func) ((bfd_vma) addr, info); - (*func) (stream, "\n"); - } - else - (*func) (stream, "%s",s.operandBuffer); + struct arcDisState ret; + memset (&ret, 0, sizeof (struct arcDisState)); + + ret.instructionLen = print_insn_arc (memaddr, info); + +#if 0 + ret.words[0] = insn[0]; + ret.words[1] = insn[1]; + ret._this = &ret; + ret.coreRegName = _coreRegName; + ret.auxRegName = _auxRegName; + ret.condCodeName = _condCodeName; + ret.instName = _instName; +#endif - return s.instructionLen; + return ret; } -/* Return the print_insn function to use. - Side effect: load (possibly empty) extension section */ - -disassembler_ftype -arc_get_disassembler (void *ptr) -{ - if (ptr) - build_ARC_extmap ((struct bfd *) ptr); - return decodeInstr; -} +/* Local variables: + eval: (c-set-style "gnu") + indent-tabs-mode: t + End: */ diff --git a/opcodes/arc-dis.h b/opcodes/arc-dis.h index dc73322..bcb88e5 100644 --- a/opcodes/arc-dis.h +++ b/opcodes/arc-dis.h @@ -1,6 +1,7 @@ /* Disassembler structures definitions for the ARC. Copyright (C) 1994-2015 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) This file is part of libopcodes. @@ -21,11 +22,15 @@ #ifndef ARCDIS_H #define ARCDIS_H -enum +enum ARC_Debugger_OperandType { - BR_exec_when_no_jump, - BR_exec_always, - BR_exec_when_jump + ARC_UNDEFINED, + ARC_LIMM, + ARC_SHIMM, + ARC_REGISTER, + ARCOMPACT_REGISTER /* Valid only for the + registers allowed in + 16 bit mode. */ }; enum Flow @@ -38,7 +43,13 @@ enum Flow invalid_instr }; -enum { no_reg = 99 }; +enum NullifyMode +{ + BR_exec_when_no_jump, + BR_exec_always, + BR_exec_when_jump +}; + enum { allOperandsSize = 256 }; struct arcDisState @@ -53,10 +64,21 @@ struct arcDisState unsigned char* instruction; unsigned index; - const char *comm[6]; /* instr name, cond, NOP, 3 operands */ + const char *comm[6]; /* Instr name, cond, NOP, 3 operands. */ + + union + { + unsigned int registerNum; + unsigned int shortimm; + unsigned int longimm; + } source_operand; + enum ARC_Debugger_OperandType sourceType; + int opWidth; int targets[4]; - int addresses[4]; + /* START ARC LOCAL. */ + unsigned int addresses[4]; + /* END ARC LOCAL. */ /* Set as a side-effect of calling the disassembler. Used only by the debugger. */ enum Flow flow; @@ -68,15 +90,16 @@ struct arcDisState char instrBuffer[40]; char operandBuffer[allOperandsSize]; char _ea_present; + char _addrWriteBack; /* Address writeback. */ char _mem_load; char _load_len; - char nullifyMode; + enum NullifyMode nullifyMode; unsigned char commNum; unsigned char isBranch; unsigned char tcnt; unsigned char acnt; }; -#define __TRANSLATION_REQUIRED(state) ((state).acnt != 0) - +struct arcDisState +arcAnalyzeInstr (bfd_vma memaddr, struct disassemble_info *); #endif diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c index d2b3f12..3267fb5 100644 --- a/opcodes/arc-ext.c +++ b/opcodes/arc-ext.c @@ -1,4 +1,4 @@ -/* ARC target-dependent stuff. Extension structure access functions +/* ARC target-dependent stuff. Extension structure access functions Copyright (C) 1995-2015 Free Software Foundation, Inc. This file is part of libopcodes. @@ -21,137 +21,88 @@ #include "sysdep.h" #include <stdlib.h> #include <stdio.h> + #include "bfd.h" #include "arc-ext.h" +#include "elf/arc.h" #include "libiberty.h" -/* Extension structure */ -static struct arcExtMap arc_extension_map; -/* Get the name of an extension instruction. */ +/* This module provides support for extensions to the ARC processor + architecture. */ -const char * -arcExtMap_instName(int opcode, int minor, int *flags) -{ - if (opcode == 3) - { - /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ - if (minor < 0x09 || minor == 0x3f) - return 0; - else - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - } - else - if (opcode < 0x10) - return 0; - else - opcode -= 0x10; - if (!arc_extension_map.instructions[opcode]) - return 0; - *flags = arc_extension_map.instructions[opcode]->flags; - return arc_extension_map.instructions[opcode]->name; -} -/* Get the name of an extension core register. */ +/* Local constants. */ -const char * -arcExtMap_coreRegName(int value) -{ - if (value < 32) - return 0; - return arc_extension_map.coreRegisters[value-32]; -} +#define FIRST_EXTENSION_CORE_REGISTER 32 +#define LAST_EXTENSION_CORE_REGISTER 59 +#define FIRST_EXTENSION_CONDITION_CODE 0x10 +#define LAST_EXTENSION_CONDITION_CODE 0x1f -/* Get the name of an extension condition code. */ +#define NUM_EXT_CORE \ + (LAST_EXTENSION_CORE_REGISTER - FIRST_EXTENSION_CORE_REGISTER + 1) +#define NUM_EXT_COND \ + (LAST_EXTENSION_CONDITION_CODE - FIRST_EXTENSION_CONDITION_CODE + 1) +#define INST_HASH_BITS 6 +#define INST_HASH_SIZE (1 << INST_HASH_BITS) +#define INST_HASH_MASK (INST_HASH_SIZE - 1) -const char * -arcExtMap_condCodeName(int value) -{ - if (value < 16) - return 0; - return arc_extension_map.condCodes[value-16]; -} -/* Get the name of an extension aux register. */ +/* Local types. */ -const char * -arcExtMap_auxRegName(long address) -{ - /* walk the list of aux reg names and find the name */ - struct ExtAuxRegister *r; +/* These types define the information stored in the table. */ - for (r = arc_extension_map.auxRegisters; r; r = r->next) { - if (r->address == address) - return (const char *) r->name; - } - return 0; -} +struct ExtInstruction +{ + char major; + char minor; + char flags; + char* name; + struct ExtInstruction* next; +}; + +struct ExtAuxRegister +{ + long address; + char* name; + struct ExtAuxRegister* next; +}; -/* Recursively free auxilliary register strcture pointers until - the list is empty. */ +struct ExtCoreRegister +{ + short number; + enum ExtReadWrite rw; + char* name; +}; -static void -clean_aux_registers(struct ExtAuxRegister *r) +struct arcExtMap { - if (r -> next) - { - clean_aux_registers( r->next); - free(r -> name); - free(r -> next); - r ->next = NULL; - } - else - free(r -> name); -} + struct ExtAuxRegister* auxRegisters; + struct ExtInstruction* instructions[INST_HASH_SIZE]; + struct ExtCoreRegister coreRegisters[NUM_EXT_CORE]; + char* condCodes[NUM_EXT_COND]; +}; -/* Free memory that has been allocated for the extensions. */ -static void -cleanup_ext_map(void) -{ - struct ExtAuxRegister *r; - struct ExtInstruction *insn; - int i; +/* Local data. */ - /* clean aux reg structure */ - r = arc_extension_map.auxRegisters; - if (r) - { - (clean_aux_registers(r)); - free(r); - } +/* Extension table. */ +static struct arcExtMap arc_extension_map; - /* clean instructions */ - for (i = 0; i < NUM_EXT_INST; i++) - { - insn = arc_extension_map.instructions[i]; - if (insn) - free(insn->name); - } - /* clean core reg struct */ - for (i = 0; i < NUM_EXT_CORE; i++) - { - if (arc_extension_map.coreRegisters[i]) - free(arc_extension_map.coreRegisters[i]); - } +/* Local macros. */ - for (i = 0; i < NUM_EXT_COND; i++) { - if (arc_extension_map.condCodes[i]) - free(arc_extension_map.condCodes[i]); - } +/* A hash function used to map instructions into the table. */ +#define INST_HASH(MAJOR, MINOR) ((((MAJOR) << 3) ^ (MINOR)) & INST_HASH_MASK) - memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); -} -int -arcExtMap_add(void *base, unsigned long length) -{ - unsigned char *block = (unsigned char *) base; - unsigned char *p = (unsigned char *) block; +/* Local functions. */ - /* Clean up and reset everything if needed. */ - cleanup_ext_map(); +static void +create_map (unsigned char *block, + unsigned long length) +{ + unsigned char *p = block; while (p && p < (block + length)) { @@ -165,97 +116,384 @@ arcExtMap_add(void *base, unsigned long length) For core regs and condition codes: p[2] = value p[3]+ = name - For aux regs: + For auxiliary regs: p[2..5] = value p[6]+ = name - (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]) */ + (value is p[2]<<24|p[3]<<16|p[4]<<8|p[5]). */ + /* The sequence of records is temrinated by an "empty" + record. */ if (p[0] == 0) - return -1; + break; switch (p[1]) { case EXT_INSTRUCTION: { - char opcode = p[2]; - char minor = p[3]; - char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); - struct ExtInstruction * insn = - (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); - - if (opcode==3) - opcode = 0x1f - 0x10 + minor - 0x09 + 1; - else - opcode -= 0x10; - insn -> flags = (char) *(p+4); - strcpy (insn_name, (char *) (p+5)); - insn -> name = insn_name; - arc_extension_map.instructions[(int) opcode] = insn; + struct ExtInstruction *insn = XNEW (struct ExtInstruction); + int major = p[2]; + int minor = p[3]; + struct ExtInstruction **bucket = + &arc_extension_map.instructions[INST_HASH (major, minor)]; + + insn->name = xstrdup ((char *) (p + 5)); + insn->major = major; + insn->minor = minor; + insn->flags = p[4]; + insn->next = *bucket; + *bucket = insn; + break; } - break; case EXT_CORE_REGISTER: { - char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); + unsigned char number = p[2]; + char* name = (char *) (p + 3); + + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number + = number; + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw + = REG_READWRITE; + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name + = xstrdup (name); + break; + } - strcpy(core_name, (char *) (p+3)); - arc_extension_map.coreRegisters[p[2]-32] = core_name; + case EXT_LONG_CORE_REGISTER: + { + unsigned char number = p[2]; + char* name = (char *) (p + 7); + enum ExtReadWrite rw = p[6]; + + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].number + = number; + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].rw + = rw; + arc_extension_map. + coreRegisters[number - FIRST_EXTENSION_CORE_REGISTER].name + = xstrdup (name); } - break; case EXT_COND_CODE: { - char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); - strcpy(cc_name, (char *) (p+3)); - arc_extension_map.condCodes[p[2]-16] = cc_name; + char *cc_name = xstrdup ((char *) (p + 3)); + + arc_extension_map. + condCodes[p[2] - FIRST_EXTENSION_CONDITION_CODE] + = cc_name; + break; } - break; case EXT_AUX_REGISTER: { - /* trickier -- need to store linked list to these */ - struct ExtAuxRegister *newAuxRegister = - (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); - char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); + /* Trickier -- need to store linked list of these. */ + struct ExtAuxRegister *newAuxRegister + = XNEW (struct ExtAuxRegister); + char *aux_name = xstrdup ((char *) (p + 6)); - strcpy (aux_name, (char *) (p+6)); newAuxRegister->name = aux_name; - newAuxRegister->address = p[2]<<24 | p[3]<<16 | p[4]<<8 | p[5]; + newAuxRegister->address = (p[2] << 24) | (p[3] << 16) + | (p[4] << 8) | p[5]; newAuxRegister->next = arc_extension_map.auxRegisters; arc_extension_map.auxRegisters = newAuxRegister; + break; } - break; default: - return -1; + break; + } + + p += p[0]; /* Move on to next record. */ + } +} + + +/* Free memory that has been allocated for the extensions. */ + +static void +destroy_map (void) +{ + struct ExtAuxRegister *r; + unsigned int i; + + /* Free auxiliary registers. */ + r = arc_extension_map.auxRegisters; + while (r) + { + /* N.B. after r has been freed, r->next is invalid! */ + struct ExtAuxRegister* next = r->next; + + free (r->name); + free (r); + r = next; + } + + /* Free instructions. */ + for (i = 0; i < INST_HASH_SIZE; i++) + { + struct ExtInstruction *insn = arc_extension_map.instructions[i]; + + while (insn) + { + /* N.B. after insn has been freed, insn->next is invalid! */ + struct ExtInstruction *next = insn->next; + + free (insn->name); + free (insn); + insn = next; + } + } + + /* Free core registers. */ + for (i = 0; i < NUM_EXT_CORE; i++) + { + if (arc_extension_map.coreRegisters[i].name) + free (arc_extension_map.coreRegisters[i].name); + } + /* Free condition codes. */ + for (i = 0; i < NUM_EXT_COND; i++) + { + if (arc_extension_map.condCodes[i]) + free (arc_extension_map.condCodes[i]); + } + + memset (&arc_extension_map, 0, sizeof (arc_extension_map)); +} + + +static const char * +ExtReadWrite_image (enum ExtReadWrite val) +{ + switch (val) + { + case REG_INVALID : return "INVALID"; + case REG_READ : return "RO"; + case REG_WRITE : return "WO"; + case REG_READWRITE: return "R/W"; + default : return "???"; + } +} + + +/* Externally visible functions. */ + +/* Get the name of an extension instruction. */ + +const char * +arcExtMap_instName (int opcode, + int insn, + int *flags) +{ + /* Here the following tasks need to be done. First of all, the + opcode stored in the Extension Map is the real opcode. However, + the subopcode stored in the instruction to be disassembled is + mangled. We pass (in minor opcode), the instruction word. Here + we will un-mangle it and get the real subopcode which we can look + for in the Extension Map. This function is used both for the + ARCTangent and the ARCompact, so we would also need some sort of + a way to distinguish between the two architectures. This is + because the ARCTangent does not do any of this mangling so we + have no issues there. */ + + /* If P[22:23] is 0 or 2 then un-mangle using iiiiiI. If it is 1 + then use iiiiIi. Now, if P is 3 then check M[5:5] and if it is 0 + then un-mangle using iiiiiI else iiiiii. */ + + unsigned char minor; + struct ExtInstruction *temp; + + /* 16-bit instructions. */ + if (0x08 <= opcode && opcode <= 0x0b) + { + unsigned char b, c, i; + + b = (insn & 0x0700) >> 8; + c = (insn & 0x00e0) >> 5; + i = (insn & 0x001f); + + if (i) + minor = i; + else + minor = (c == 0x07) ? b : c; + } + /* 32-bit instructions. */ + else + { + unsigned char I, A, B; + + I = (insn & 0x003f0000) >> 16; + A = (insn & 0x0000003f); + B = ((insn & 0x07000000) >> 24) | ((insn & 0x00007000) >> 9); + + if (I != 0x2f) + { +#ifndef UNMANGLED + switch (P) + { + case 3: + if (M) + { + minor = I; + break; + } + case 0: + case 2: + minor = (I >> 1) | ((I & 0x1) << 5); + break; + case 1: + minor = (I >> 1) | (I & 0x1) | ((I & 0x2) << 4); + } +#else + minor = I; +#endif + } + else + { + if (A != 0x3f) + minor = A; + else + minor = B; + } + } + + temp = arc_extension_map.instructions[INST_HASH (opcode, minor)]; + while (temp) + { + if ((temp->major == opcode) && (temp->minor == minor)) + { + *flags = temp->flags; + return temp->name; } - p += p[0]; /* move to next record */ + temp = temp->next; } - return 0; + return NULL; } -/* Load hw extension descibed in .extArcMap ELF section. */ +/* Get the name of an extension core register. */ -void -build_ARC_extmap (text_bfd) - bfd *text_bfd; +const char * +arcExtMap_coreRegName (int regnum) +{ + if (regnum < FIRST_EXTENSION_CORE_REGISTER + || regnum > LAST_EXTENSION_CONDITION_CODE) + return NULL; + return arc_extension_map. + coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].name; +} + +/* Get the access mode of an extension core register. */ + +enum ExtReadWrite +arcExtMap_coreReadWrite (int regnum) { - char *arcExtMap; - bfd_size_type count; - asection *p; + if (regnum < FIRST_EXTENSION_CORE_REGISTER + || regnum > LAST_EXTENSION_CONDITION_CODE) + return REG_INVALID; + return arc_extension_map. + coreRegisters[regnum - FIRST_EXTENSION_CORE_REGISTER].rw; +} + +/* Get the name of an extension condition code. */ + +const char * +arcExtMap_condCodeName (int code) +{ + if (code < FIRST_EXTENSION_CONDITION_CODE + || code > LAST_EXTENSION_CONDITION_CODE) + return NULL; + return arc_extension_map. + condCodes[code - FIRST_EXTENSION_CONDITION_CODE]; +} + +/* Get the name of an extension auxiliary register. */ + +const char * +arcExtMap_auxRegName (long address) +{ + /* Walk the list of auxiliary register names and find the name. */ + struct ExtAuxRegister *r; + + for (r = arc_extension_map.auxRegisters; r; r = r->next) + { + if (r->address == address) + return (const char *)r->name; + } + return NULL; +} + +/* Load extensions described in .arcextmap and + .gnu.linkonce.arcextmap.* ELF section. */ - for (p = text_bfd->sections; p != NULL; p = p->next) - if (!strcmp (p->name, ".arcextmap")) +void +build_ARC_extmap (bfd *text_bfd) +{ + asection *sect; + + /* The map is built each time gdb loads an executable file - so free + any existing map, as the map defined by the new file may differ + from the old. */ + destroy_map (); + + for (sect = text_bfd->sections; sect != NULL; sect = sect->next) + if (!strncmp (sect->name, + ".gnu.linkonce.arcextmap.", + sizeof (".gnu.linkonce.arcextmap.") - 1) + || !strcmp (sect->name,".arcextmap")) { - count = bfd_get_section_size (p); - arcExtMap = (char *) xmalloc (count); - if (bfd_get_section_contents (text_bfd, p, (PTR) arcExtMap, 0, count)) - { - arcExtMap_add ((PTR) arcExtMap, count); - break; - } - free ((PTR) arcExtMap); + bfd_size_type count = bfd_get_section_size (sect); + unsigned char* buffer = xmalloc (count); + + if (buffer) + { + if (bfd_get_section_contents (text_bfd, sect, buffer, 0, count)) + create_map (buffer, count); + free (buffer); + } } } + + +void +dump_ARC_extmap (void) +{ + struct ExtAuxRegister *r; + int i; + + r = arc_extension_map.auxRegisters; + + while (r) + { + printf ("AUX : %s %ld\n", r->name, r->address); + r = r->next; + } + + for (i = 0; i < INST_HASH_SIZE; i++) + { + struct ExtInstruction *insn; + + for (insn = arc_extension_map.instructions[i]; + insn != NULL; insn = insn->next) + printf ("INST: %d %d %x %s\n", insn->major, insn->minor, + insn->flags, insn->name); + } + + for (i = 0; i < NUM_EXT_CORE; i++) + { + struct ExtCoreRegister reg = arc_extension_map.coreRegisters[i]; + + if (reg.name) + printf ("CORE: %s %d %s\n", reg.name, reg.number, + ExtReadWrite_image (reg.rw)); + } + + for (i = 0; i < NUM_EXT_COND; i++) + if (arc_extension_map.condCodes[i]) + printf ("COND: %s\n", arc_extension_map.condCodes[i]); +} diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h index 8a7d7c4..9eb46ae 100644 --- a/opcodes/arc-ext.h +++ b/opcodes/arc-ext.h @@ -1,4 +1,4 @@ -/* ARC target-dependent stuff. Extension data structures. +/* ARC target-dependent stuff. Extension data structures. Copyright (C) 1995-2015 Free Software Foundation, Inc. This file is part of libopcodes. @@ -18,46 +18,72 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ -#ifndef ARCEXT_H -#define ARCEXT_H +/*This header file defines a table of extensions to the ARC processor + architecture. These extensions are read from the '.arcextmap' or + '.gnu.linkonce.arcextmap.<type>.<N>' sections in the ELF file which + is identified by the bfd parameter to the build_ARC_extmap function. -enum {EXT_INSTRUCTION = 0, - EXT_CORE_REGISTER = 1, - EXT_AUX_REGISTER = 2, - EXT_COND_CODE = 3}; + These extensions may include: + core registers + auxiliary registers + instructions + condition codes -enum {NUM_EXT_INST = (0x1f-0x10+1) + (0x3f-0x09+1)}; -enum {NUM_EXT_CORE = 59-32+1}; -enum {NUM_EXT_COND = 0x1f-0x10+1}; + Once the table has been constructed, accessor functions may be used + to retrieve information from it. -struct ExtInstruction -{ - char flags; - char *name; -}; + The build_ARC_extmap constructor function build_ARC_extmap may be + called as many times as required; it will re-initialize the table + each time. */ + +#ifndef ARC_EXTENSIONS_H +#define ARC_EXTENSIONS_H + +#define IGNORE_FIRST_OPD 1 + +/* Define this if we do not want to encode instructions based on the + ARCompact Programmer's Reference. */ +#define UNMANGLED -struct ExtAuxRegister + +/* This defines the kinds of extensions which may be read from the + ections in the executable files. */ +enum ExtOperType { - long address; - char *name; - struct ExtAuxRegister *next; + EXT_INSTRUCTION = 0, + EXT_CORE_REGISTER = 1, + EXT_AUX_REGISTER = 2, + EXT_COND_CODE = 3, + EXT_INSTRUCTION32 = 4, + EXT_AC_INSTRUCTION = 4, + EXT_REMOVE_CORE_REG = 5, + EXT_LONG_CORE_REGISTER = 6, + EXT_AUX_REGISTER_EXTENDED = 7, + EXT_INSTRUCTION32_EXTENDED = 8, + EXT_CORE_REGISTER_CLASS = 9 }; -struct arcExtMap + +enum ExtReadWrite { - struct ExtAuxRegister *auxRegisters; - struct ExtInstruction *instructions[NUM_EXT_INST]; - char *coreRegisters[NUM_EXT_CORE]; - char *condCodes[NUM_EXT_COND]; + REG_INVALID, + REG_READ, + REG_WRITE, + REG_READWRITE }; -extern int arcExtMap_add(void*, unsigned long); -extern const char *arcExtMap_coreRegName(int); -extern const char *arcExtMap_auxRegName(long); -extern const char *arcExtMap_condCodeName(int); -extern const char *arcExtMap_instName(int, int, int*); -extern void build_ARC_extmap(bfd *); -#define IGNORE_FIRST_OPD 1 +/* Constructor function. */ +extern void build_ARC_extmap (bfd *); + +/* Accessor functions. */ +extern enum ExtReadWrite arcExtMap_coreReadWrite (int); +extern const char * arcExtMap_coreRegName (int); +extern const char * arcExtMap_auxRegName (long); +extern const char * arcExtMap_condCodeName (int); +extern const char * arcExtMap_instName (int, int, int *); + +/* Dump function (for debugging). */ +extern void dump_ARC_extmap (void); -#endif +#endif /* ARC_EXTENSIONS_H */ diff --git a/opcodes/arc-fxi.h b/opcodes/arc-fxi.h new file mode 100644 index 0000000..5f36982 --- /dev/null +++ b/opcodes/arc-fxi.h @@ -0,0 +1,1317 @@ +/* Insert/extract functions for the ARC opcodes. + Copyright 2015 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef INSERT_LIMM +#define INSERT_LIMM +/* mask = 00000000000000000000000000000000 + insn = 00100bbb00101111FBBB111110001001. */ +static unsigned +insert_limm (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED) +{ + + return insn; +} +#endif /* INSERT_LIMM */ + +#ifndef EXTRACT_LIMM +#define EXTRACT_LIMM +/* mask = 00000000000000000000000000000000. */ +static ATTRIBUTE_UNUSED int +extract_limm (unsigned insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} +#endif /* EXTRACT_LIMM */ + +#ifndef INSERT_UIMM6_20 +#define INSERT_UIMM6_20 +/* mask = 00000000000000000000111111000000 + insn = 00100bbb01101111FBBBuuuuuu001001. */ +static unsigned +insert_uimm6_20 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x003f) << 6; + + return insn; +} +#endif /* INSERT_UIMM6_20 */ + +#ifndef EXTRACT_UIMM6_20 +#define EXTRACT_UIMM6_20 +/* mask = 00000000000000000000111111000000. */ +static int +extract_uimm6_20 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + return value; +} +#endif /* EXTRACT_UIMM6_20 */ + +#ifndef INSERT_SIMM12_20 +#define INSERT_SIMM12_20 +/* mask = 00000000000000000000111111222222 + insn = 00110bbb10101000FBBBssssssSSSSSS. */ +static unsigned +insert_simm12_20 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x003f) << 6; + insn |= ((value >> 6) & 0x003f) << 0; + + return insn; +} +#endif /* INSERT_SIMM12_20 */ + +#ifndef EXTRACT_SIMM12_20 +#define EXTRACT_SIMM12_20 +/* mask = 00000000000000000000111111222222. */ +static int +extract_simm12_20 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + value |= ((insn >> 0) & 0x003f) << 6; + + /* Extend the sign. */ + int signbit = 1 << (12 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM12_20 */ + +#ifndef INSERT_SIMM3_5_S +#define INSERT_SIMM3_5_S +/* mask = 0000011100000000 + insn = 01110ssshhh001HH. */ +static ATTRIBUTE_UNUSED unsigned +insert_simm3_5_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x0007) << 8; + + return insn; +} +#endif /* INSERT_SIMM3_5_S */ + +#ifndef EXTRACT_SIMM3_5_S +#define EXTRACT_SIMM3_5_S +/* mask = 0000011100000000. */ +static ATTRIBUTE_UNUSED int +extract_simm3_5_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 8) & 0x0007) << 0; + + /* Extend the sign. */ + int signbit = 1 << (3 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM3_5_S */ + +#ifndef INSERT_LIMM_S +#define INSERT_LIMM_S +/* mask = 0000000000000000 + insn = 01110sss11000111. */ +static ATTRIBUTE_UNUSED unsigned +insert_limm_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + return insn; +} +#endif /* INSERT_LIMM_S */ + +#ifndef EXTRACT_LIMM_S +#define EXTRACT_LIMM_S +/* mask = 0000000000000000. */ +static ATTRIBUTE_UNUSED int +extract_limm_s (unsigned insn ATTRIBUTE_UNUSED, bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} +#endif /* EXTRACT_LIMM_S */ + +#ifndef INSERT_UIMM7_A32_11_S +#define INSERT_UIMM7_A32_11_S +/* mask = 0000000000011111 + insn = 11000bbb100uuuuu. */ +static unsigned +insert_uimm7_a32_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x001f) << 0; + + return insn; +} +#endif /* INSERT_UIMM7_A32_11_S */ + +#ifndef EXTRACT_UIMM7_A32_11_S +#define EXTRACT_UIMM7_A32_11_S +/* mask = 0000000000011111. */ +static int +extract_uimm7_a32_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 2; + + return value; +} +#endif /* EXTRACT_UIMM7_A32_11_S */ + +#ifndef INSERT_UIMM7_9_S +#define INSERT_UIMM7_9_S +/* mask = 0000000001111111 + insn = 11100bbb0uuuuuuu. */ +static unsigned +insert_uimm7_9_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x007f) << 0; + + return insn; +} +#endif /* INSERT_UIMM7_9_S */ + +#ifndef EXTRACT_UIMM7_9_S +#define EXTRACT_UIMM7_9_S +/* mask = 0000000001111111. */ +static int +extract_uimm7_9_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x007f) << 0; + + return value; +} +#endif /* EXTRACT_UIMM7_9_S */ + +#ifndef INSERT_UIMM3_13_S +#define INSERT_UIMM3_13_S +/* mask = 0000000000000111 + insn = 01101bbbccc00uuu. */ +static unsigned +insert_uimm3_13_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x0007) << 0; + + return insn; +} +#endif /* INSERT_UIMM3_13_S */ + +#ifndef EXTRACT_UIMM3_13_S +#define EXTRACT_UIMM3_13_S +/* mask = 0000000000000111. */ +static int +extract_uimm3_13_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + + return value; +} +#endif /* EXTRACT_UIMM3_13_S */ + +#ifndef INSERT_SIMM11_A32_7_S +#define INSERT_SIMM11_A32_7_S +/* mask = 0000000111111111 + insn = 1100111sssssssss. */ +static unsigned +insert_simm11_a32_7_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x01ff) << 0; + + return insn; +} +#endif /* INSERT_SIMM11_A32_7_S */ + +#ifndef EXTRACT_SIMM11_A32_7_S +#define EXTRACT_SIMM11_A32_7_S +/* mask = 0000000111111111. */ +static int +extract_simm11_a32_7_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 2; + + /* Extend the sign. */ + int signbit = 1 << (11 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM11_A32_7_S */ + +#ifndef INSERT_UIMM6_13_S +#define INSERT_UIMM6_13_S +/* mask = 0000000002220111 + insn = 01001bbb0UUU1uuu. */ +static unsigned +insert_uimm6_13_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x0007) << 0; + insn |= ((value >> 3) & 0x0007) << 4; + + return insn; +} +#endif /* INSERT_UIMM6_13_S */ + +#ifndef EXTRACT_UIMM6_13_S +#define EXTRACT_UIMM6_13_S +/* mask = 0000000002220111. */ +static int +extract_uimm6_13_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + value |= ((insn >> 4) & 0x0007) << 3; + + return value; +} +#endif /* EXTRACT_UIMM6_13_S */ + +#ifndef INSERT_UIMM5_11_S +#define INSERT_UIMM5_11_S +/* mask = 0000000000011111 + insn = 10111bbb000uuuuu. */ +static unsigned +insert_uimm5_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x001f) << 0; + + return insn; +} +#endif /* INSERT_UIMM5_11_S */ + +#ifndef EXTRACT_UIMM5_11_S +#define EXTRACT_UIMM5_11_S +/* mask = 0000000000011111. */ +static int +extract_uimm5_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 0; + + return value; +} +#endif /* EXTRACT_UIMM5_11_S */ + +#ifndef INSERT_SIMM9_A16_8 +#define INSERT_SIMM9_A16_8 +/* mask = 00000000111111102000000000000000 + insn = 00001bbbsssssss1SBBBCCCCCCN01110. */ +static unsigned +insert_simm9_a16_8 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x007f) << 17; + insn |= ((value >> 8) & 0x0001) << 15; + + return insn; +} +#endif /* INSERT_SIMM9_A16_8 */ + +#ifndef EXTRACT_SIMM9_A16_8 +#define EXTRACT_SIMM9_A16_8 +/* mask = 00000000111111102000000000000000. */ +static int +extract_simm9_a16_8 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x007f) << 1; + value |= ((insn >> 15) & 0x0001) << 8; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM9_A16_8 */ + +#ifndef INSERT_UIMM6_8 +#define INSERT_UIMM6_8 +/* mask = 00000000000000000000111111000000 + insn = 00001bbbsssssss1SBBBuuuuuuN11110. */ +static unsigned +insert_uimm6_8 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x003f) << 6; + + return insn; +} +#endif /* INSERT_UIMM6_8 */ + +#ifndef EXTRACT_UIMM6_8 +#define EXTRACT_UIMM6_8 +/* mask = 00000000000000000000111111000000. */ +static int +extract_uimm6_8 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 0; + + return value; +} +#endif /* EXTRACT_UIMM6_8 */ + +#ifndef INSERT_SIMM21_A16_5 +#define INSERT_SIMM21_A16_5 +/* mask = 00000111111111102222222222000000 + insn = 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ +static unsigned +insert_simm21_a16_5 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x03ff) << 17; + insn |= ((value >> 11) & 0x03ff) << 6; + + return insn; +} +#endif /* INSERT_SIMM21_A16_5 */ + +#ifndef EXTRACT_SIMM21_A16_5 +#define EXTRACT_SIMM21_A16_5 +/* mask = 00000111111111102222222222000000. */ +static int +extract_simm21_a16_5 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x03ff) << 1; + value |= ((insn >> 6) & 0x03ff) << 11; + + /* Extend the sign. */ + int signbit = 1 << (21 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM21_A16_5 */ + +#ifndef INSERT_SIMM25_A16_5 +#define INSERT_SIMM25_A16_5 +/* mask = 00000111111111102222222222003333 + insn = 00000ssssssssss1SSSSSSSSSSNRtttt. */ +static unsigned +insert_simm25_a16_5 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x03ff) << 17; + insn |= ((value >> 11) & 0x03ff) << 6; + insn |= ((value >> 21) & 0x000f) << 0; + + return insn; +} +#endif /* INSERT_SIMM25_A16_5 */ + +#ifndef EXTRACT_SIMM25_A16_5 +#define EXTRACT_SIMM25_A16_5 +/* mask = 00000111111111102222222222003333. */ +static int +extract_simm25_a16_5 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 17) & 0x03ff) << 1; + value |= ((insn >> 6) & 0x03ff) << 11; + value |= ((insn >> 0) & 0x000f) << 21; + + /* Extend the sign. */ + int signbit = 1 << (25 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM25_A16_5 */ + +#ifndef INSERT_SIMM10_A16_7_S +#define INSERT_SIMM10_A16_7_S +/* mask = 0000000111111111 + insn = 1111001sssssssss. */ +static unsigned +insert_simm10_a16_7_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x01ff) << 0; + + return insn; +} +#endif /* INSERT_SIMM10_A16_7_S */ + +#ifndef EXTRACT_SIMM10_A16_7_S +#define EXTRACT_SIMM10_A16_7_S +/* mask = 0000000111111111. */ +static int +extract_simm10_a16_7_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 1; + + /* Extend the sign. */ + int signbit = 1 << (10 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM10_A16_7_S */ + +#ifndef INSERT_SIMM7_A16_10_S +#define INSERT_SIMM7_A16_10_S +/* mask = 0000000000111111 + insn = 1111011000ssssss. */ +static unsigned +insert_simm7_a16_10_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x003f) << 0; + + return insn; +} +#endif /* INSERT_SIMM7_A16_10_S */ + +#ifndef EXTRACT_SIMM7_A16_10_S +#define EXTRACT_SIMM7_A16_10_S +/* mask = 0000000000111111. */ +static int +extract_simm7_a16_10_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x003f) << 1; + + /* Extend the sign. */ + int signbit = 1 << (7 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM7_A16_10_S */ + +#ifndef INSERT_SIMM21_A32_5 +#define INSERT_SIMM21_A32_5 +/* mask = 00000111111111002222222222000000 + insn = 00001sssssssss00SSSSSSSSSSNQQQQQ. */ +static unsigned +insert_simm21_a32_5 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x01ff) << 18; + insn |= ((value >> 11) & 0x03ff) << 6; + + return insn; +} +#endif /* INSERT_SIMM21_A32_5 */ + +#ifndef EXTRACT_SIMM21_A32_5 +#define EXTRACT_SIMM21_A32_5 +/* mask = 00000111111111002222222222000000. */ +static int +extract_simm21_a32_5 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 18) & 0x01ff) << 2; + value |= ((insn >> 6) & 0x03ff) << 11; + + /* Extend the sign. */ + int signbit = 1 << (21 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM21_A32_5 */ + +#ifndef INSERT_SIMM25_A32_5 +#define INSERT_SIMM25_A32_5 +/* mask = 00000111111111002222222222003333 + insn = 00001sssssssss10SSSSSSSSSSNRtttt. */ +static unsigned +insert_simm25_a32_5 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x01ff) << 18; + insn |= ((value >> 11) & 0x03ff) << 6; + insn |= ((value >> 21) & 0x000f) << 0; + + return insn; +} +#endif /* INSERT_SIMM25_A32_5 */ + +#ifndef EXTRACT_SIMM25_A32_5 +#define EXTRACT_SIMM25_A32_5 +/* mask = 00000111111111002222222222003333. */ +static int +extract_simm25_a32_5 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 18) & 0x01ff) << 2; + value |= ((insn >> 6) & 0x03ff) << 11; + value |= ((insn >> 0) & 0x000f) << 21; + + /* Extend the sign. */ + int signbit = 1 << (25 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM25_A32_5 */ + +#ifndef INSERT_SIMM13_A32_5_S +#define INSERT_SIMM13_A32_5_S +/* mask = 0000011111111111 + insn = 11111sssssssssss. */ +static unsigned +insert_simm13_a32_5_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x07ff) << 0; + + return insn; +} +#endif /* INSERT_SIMM13_A32_5_S */ + +#ifndef EXTRACT_SIMM13_A32_5_S +#define EXTRACT_SIMM13_A32_5_S +/* mask = 0000011111111111. */ +static int +extract_simm13_a32_5_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x07ff) << 2; + + /* Extend the sign. */ + int signbit = 1 << (13 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM13_A32_5_S */ + +#ifndef INSERT_SIMM8_A16_9_S +#define INSERT_SIMM8_A16_9_S +/* mask = 0000000001111111 + insn = 11101bbb1sssssss. */ +static unsigned +insert_simm8_a16_9_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x007f) << 0; + + return insn; +} +#endif /* INSERT_SIMM8_A16_9_S */ + +#ifndef EXTRACT_SIMM8_A16_9_S +#define EXTRACT_SIMM8_A16_9_S +/* mask = 0000000001111111. */ +static int +extract_simm8_a16_9_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x007f) << 1; + + /* Extend the sign. */ + int signbit = 1 << (8 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM8_A16_9_S */ + +#ifndef INSERT_UIMM3_23 +#define INSERT_UIMM3_23 +/* mask = 00000000000000000000000111000000 + insn = 00100011011011110001RRRuuu111111. */ +static unsigned +insert_uimm3_23 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x0007) << 6; + + return insn; +} +#endif /* INSERT_UIMM3_23 */ + +#ifndef EXTRACT_UIMM3_23 +#define EXTRACT_UIMM3_23 +/* mask = 00000000000000000000000111000000. */ +static int +extract_uimm3_23 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x0007) << 0; + + return value; +} +#endif /* EXTRACT_UIMM3_23 */ + +#ifndef INSERT_UIMM10_6_S +#define INSERT_UIMM10_6_S +/* mask = 0000001111111111 + insn = 010111uuuuuuuuuu. */ +static unsigned +insert_uimm10_6_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x03ff) << 0; + + return insn; +} +#endif /* INSERT_UIMM10_6_S */ + +#ifndef EXTRACT_UIMM10_6_S +#define EXTRACT_UIMM10_6_S +/* mask = 0000001111111111. */ +static int +extract_uimm10_6_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x03ff) << 0; + + return value; +} +#endif /* EXTRACT_UIMM10_6_S */ + +#ifndef INSERT_UIMM6_11_S +#define INSERT_UIMM6_11_S +/* mask = 0000002200011110 + insn = 110000UU111uuuu0. */ +static unsigned +insert_uimm6_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x000f) << 1; + insn |= ((value >> 4) & 0x0003) << 8; + + return insn; +} +#endif /* INSERT_UIMM6_11_S */ + +#ifndef EXTRACT_UIMM6_11_S +#define EXTRACT_UIMM6_11_S +/* mask = 0000002200011110. */ +static int +extract_uimm6_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 1) & 0x000f) << 0; + value |= ((insn >> 8) & 0x0003) << 4; + + return value; +} +#endif /* EXTRACT_UIMM6_11_S */ + +#ifndef INSERT_SIMM9_8 +#define INSERT_SIMM9_8 +/* mask = 00000000111111112000000000000000 + insn = 00010bbbssssssssSBBBDaaZZXAAAAAA. */ +static unsigned +insert_simm9_8 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x00ff) << 16; + insn |= ((value >> 8) & 0x0001) << 15; + + return insn; +} +#endif /* INSERT_SIMM9_8 */ + +#ifndef EXTRACT_SIMM9_8 +#define EXTRACT_SIMM9_8 +/* mask = 00000000111111112000000000000000. */ +static int +extract_simm9_8 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 16) & 0x00ff) << 0; + value |= ((insn >> 15) & 0x0001) << 8; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM9_8 */ + +#ifndef INSERT_UIMM10_A32_8_S +#define INSERT_UIMM10_A32_8_S +/* mask = 0000000011111111 + insn = 11010bbbuuuuuuuu. */ +static unsigned +insert_uimm10_a32_8_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x00ff) << 0; + + return insn; +} +#endif /* INSERT_UIMM10_A32_8_S */ + +#ifndef EXTRACT_UIMM10_A32_8_S +#define EXTRACT_UIMM10_A32_8_S +/* mask = 0000000011111111. */ +static int +extract_uimm10_a32_8_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x00ff) << 2; + + return value; +} +#endif /* EXTRACT_UIMM10_A32_8_S */ + +#ifndef INSERT_SIMM9_7_S +#define INSERT_SIMM9_7_S +/* mask = 0000000111111111 + insn = 1100101sssssssss. */ +static unsigned +insert_simm9_7_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x01ff) << 0; + + return insn; +} +#endif /* INSERT_SIMM9_7_S */ + +#ifndef EXTRACT_SIMM9_7_S +#define EXTRACT_SIMM9_7_S +/* mask = 0000000111111111. */ +static int +extract_simm9_7_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x01ff) << 0; + + /* Extend the sign. */ + int signbit = 1 << (9 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM9_7_S */ + +#ifndef INSERT_UIMM6_A16_11_S +#define INSERT_UIMM6_A16_11_S +/* mask = 0000000000011111 + insn = 10010bbbcccuuuuu. */ +static unsigned +insert_uimm6_a16_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x001f) << 0; + + return insn; +} +#endif /* INSERT_UIMM6_A16_11_S */ + +#ifndef EXTRACT_UIMM6_A16_11_S +#define EXTRACT_UIMM6_A16_11_S +/* mask = 0000000000011111. */ +static int +extract_uimm6_a16_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x001f) << 1; + + return value; +} +#endif /* EXTRACT_UIMM6_A16_11_S */ + +#ifndef INSERT_UIMM5_A32_11_S +#define INSERT_UIMM5_A32_11_S +/* mask = 0000020000011000 + insn = 01000U00hhhuu1HH. */ +static unsigned +insert_uimm5_a32_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x0003) << 3; + insn |= ((value >> 4) & 0x0001) << 10; + + return insn; +} +#endif /* INSERT_UIMM5_A32_11_S */ + +#ifndef EXTRACT_UIMM5_A32_11_S +#define EXTRACT_UIMM5_A32_11_S +/* mask = 0000020000011000. */ +static int +extract_uimm5_a32_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 3) & 0x0003) << 2; + value |= ((insn >> 10) & 0x0001) << 4; + + return value; +} +#endif /* EXTRACT_UIMM5_A32_11_S */ + +#ifndef INSERT_SIMM11_A32_13_S +#define INSERT_SIMM11_A32_13_S +/* mask = 0000022222200111 + insn = 01010SSSSSS00sss. */ +static unsigned +insert_simm11_a32_13_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x03) + *errmsg = _("Target address is not 32bit aligned."); + + insn |= ((value >> 2) & 0x0007) << 0; + insn |= ((value >> 5) & 0x003f) << 5; + + return insn; +} +#endif /* INSERT_SIMM11_A32_13_S */ + +#ifndef EXTRACT_SIMM11_A32_13_S +#define EXTRACT_SIMM11_A32_13_S +/* mask = 0000022222200111. */ +static int +extract_simm11_a32_13_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 0) & 0x0007) << 2; + value |= ((insn >> 5) & 0x003f) << 5; + + /* Extend the sign. */ + int signbit = 1 << (11 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM11_A32_13_S */ + +#ifndef INSERT_UIMM7_13_S +#define INSERT_UIMM7_13_S +/* mask = 0000000022220111 + insn = 01010bbbUUUU1uuu. */ +static unsigned +insert_uimm7_13_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x0007) << 0; + insn |= ((value >> 3) & 0x000f) << 4; + + return insn; +} +#endif /* INSERT_UIMM7_13_S */ + +#ifndef EXTRACT_UIMM7_13_S +#define EXTRACT_UIMM7_13_S +/* mask = 0000000022220111. */ +static int +extract_uimm7_13_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x0007) << 0; + value |= ((insn >> 4) & 0x000f) << 3; + + return value; +} +#endif /* EXTRACT_UIMM7_13_S */ + +#ifndef INSERT_UIMM6_A16_21 +#define INSERT_UIMM6_A16_21 +/* mask = 00000000000000000000011111000000 + insn = 00101bbb01001100RBBBRuuuuuAAAAAA. */ +static unsigned +insert_uimm6_a16_21 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x001f) << 6; + + return insn; +} +#endif /* INSERT_UIMM6_A16_21 */ + +#ifndef EXTRACT_UIMM6_A16_21 +#define EXTRACT_UIMM6_A16_21 +/* mask = 00000000000000000000011111000000. */ +static int +extract_uimm6_a16_21 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x001f) << 1; + + return value; +} +#endif /* EXTRACT_UIMM6_A16_21 */ + +#ifndef INSERT_UIMM7_11_S +#define INSERT_UIMM7_11_S +/* mask = 0000022200011110 + insn = 11000UUU110uuuu0. */ +static unsigned +insert_uimm7_11_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x000f) << 1; + insn |= ((value >> 4) & 0x0007) << 8; + + return insn; +} +#endif /* INSERT_UIMM7_11_S */ + +#ifndef EXTRACT_UIMM7_11_S +#define EXTRACT_UIMM7_11_S +/* mask = 0000022200011110. */ +static int +extract_uimm7_11_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 1) & 0x000f) << 0; + value |= ((insn >> 8) & 0x0007) << 4; + + return value; +} +#endif /* EXTRACT_UIMM7_11_S */ + +#ifndef INSERT_UIMM7_A16_20 +#define INSERT_UIMM7_A16_20 +/* mask = 00000000000000000000111111000000 + insn = 00100RRR111010000RRRuuuuuu1QQQQQ. */ +static unsigned +insert_uimm7_a16_20 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x003f) << 6; + + return insn; +} +#endif /* INSERT_UIMM7_A16_20 */ + +#ifndef EXTRACT_UIMM7_A16_20 +#define EXTRACT_UIMM7_A16_20 +/* mask = 00000000000000000000111111000000. */ +static int +extract_uimm7_a16_20 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 6) & 0x003f) << 1; + + return value; +} +#endif /* EXTRACT_UIMM7_A16_20 */ + +#ifndef INSERT_SIMM13_A16_20 +#define INSERT_SIMM13_A16_20 +/* mask = 00000000000000000000111111222222 + insn = 00100RRR101010000RRRssssssSSSSSS. */ +static unsigned +insert_simm13_a16_20 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Target address is not 16bit aligned."); + + insn |= ((value >> 1) & 0x003f) << 6; + insn |= ((value >> 7) & 0x003f) << 0; + + return insn; +} +#endif /* INSERT_SIMM13_A16_20 */ + +#ifndef EXTRACT_SIMM13_A16_20 +#define EXTRACT_SIMM13_A16_20 +/* mask = 00000000000000000000111111222222. */ +static int +extract_simm13_a16_20 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; + + value |= ((insn >> 6) & 0x003f) << 1; + value |= ((insn >> 0) & 0x003f) << 7; + + /* Extend the sign. */ + int signbit = 1 << (13 - 1); + value = (value ^ signbit) - signbit; + + return value; +} +#endif /* EXTRACT_SIMM13_A16_20 */ + +#ifndef INSERT_UIMM8_8_S +#define INSERT_UIMM8_8_S +/* mask = 0000000011111111 + insn = 11011bbbuuuuuuuu. */ +static unsigned +insert_uimm8_8_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x00ff) << 0; + + return insn; +} +#endif /* INSERT_UIMM8_8_S */ + +#ifndef EXTRACT_UIMM8_8_S +#define EXTRACT_UIMM8_8_S +/* mask = 0000000011111111. */ +static int +extract_uimm8_8_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 0) & 0x00ff) << 0; + + return value; +} +#endif /* EXTRACT_UIMM8_8_S */ + +#ifndef INSERT_UIMM6_5_S +#define INSERT_UIMM6_5_S +/* mask = 0000011111100000 + insn = 01111uuuuuu11111. */ +static unsigned +insert_uimm6_5_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + + insn |= ((value >> 0) & 0x003f) << 5; + + return insn; +} +#endif /* INSERT_UIMM6_5_S */ + +#ifndef EXTRACT_UIMM6_5_S +#define EXTRACT_UIMM6_5_S +/* mask = 0000011111100000. */ +static int +extract_uimm6_5_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + value |= ((insn >> 5) & 0x003f) << 0; + + return value; +} +#endif /* EXTRACT_UIMM6_5_S */ + +#ifndef INSERT_UIMM6_AXX_ +#define INSERT_UIMM6_AXX_ +/* mask = 00000000000000000000000000000000 + insn = 00110bbb11100001100001100001QQQQ. */ +static ATTRIBUTE_UNUSED unsigned +insert_uimm6_axx_ (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x3f) + *errmsg = _("Target address is not 512bit aligned."); + + return insn; +} +#endif /* INSERT_UIMM6_AXX_ */ + +#ifndef EXTRACT_UIMM6_AXX_ +#define EXTRACT_UIMM6_AXX_ +/* mask = 00000000000000000000000000000000. */ +static ATTRIBUTE_UNUSED int +extract_uimm6_axx_ (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + unsigned value = 0; + + return value; +} +#endif /* EXTRACT_UIMM6_AXX_ */ diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 309bb0c..db11a1f 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1,6 +1,7 @@ /* Opcode table for the ARC. Copyright (C) 1994-2015 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) This file is part of libopcodes. @@ -20,1743 +21,1327 @@ #include "sysdep.h" #include <stdio.h> -#include "ansidecl.h" #include "bfd.h" #include "opcode/arc.h" #include "opintl.h" +#include "libiberty.h" -enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; - -#define OPERANDS 3 - -enum operand ls_operand[OPERANDS]; - -struct arc_opcode *arc_ext_opcodes; -struct arc_ext_operand_value *arc_ext_operands; - -#define LS_VALUE 0 -#define LS_DEST 0 -#define LS_BASE 1 -#define LS_OFFSET 2 - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'a' suffix (address writeback). */ -static int addrwb_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a nullify condition. */ -static int nullify_p; - -/* The value of the a nullify condition we inserted. */ -static int nullify; - -/* Nonzero if we've inserted jumpflags. */ -static int jumpflags_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times). */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -#define INSERT_FN(fn) \ -static arc_insn fn (arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **) - -#define EXTRACT_FN(fn) \ -static long fn (arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_offset); -INSERT_FN (insert_base); -INSERT_FN (insert_st_syntax); -INSERT_FN (insert_ld_syntax); -INSERT_FN (insert_addr_wb); -INSERT_FN (insert_flag); -INSERT_FN (insert_nullify); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_jumpflags); -INSERT_FN (insert_unopmacro); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_ld_offset); -EXTRACT_FN (extract_ld_syntax); -EXTRACT_FN (extract_st_offset); -EXTRACT_FN (extract_st_syntax); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_jumpflags); -EXTRACT_FN (extract_unopmacro); - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'o' OFFSET offset in st insns - 'O' OFFSET offset in ld insns - '0' SYNTAX_ST_NE enforce store insn syntax, no errors - '1' SYNTAX_LD_NE enforce load insn syntax, no errors - '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only - '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only - 's' BASE base in st insn - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'j' JUMPFLAGS optional high order bits of 'J' - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */ - -const struct arc_operand arc_operands[] = +/* Insert RB register into a 32-bit opcode. */ +static unsigned +insert_rb (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { -/* Place holder (??? not sure if needed). */ -#define UNUSED 0 - { 0, 0, 0, 0, 0, 0 }, - -/* Register A or shimm/limm indicator. */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Register B or shimm/limm indicator. */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Register C or shimm/limm indicator. */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg }, - -/* Fake operand used to insert shimm value into most instructions. */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* Fake operand used to insert limm value into most instructions. */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* Shimm operand when there is no reg indicator (st). */ -#define ST_OFFSET (LIMMFINISH + 1) - { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset }, + return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12); +} -/* Shimm operand when there is no reg indicator (ld). */ -#define LD_OFFSET (ST_OFFSET + 1) - { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset }, +static int +extract_rb (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07); -/* Operand for base. */ -#define BASE (LD_OFFSET + 1) - { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg}, + if (value == 0x3e && invalid) + *invalid = TRUE; /* A limm operand, it should be extracted in a + different way. */ -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST_NE (BASE + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax }, + return value; +} -/* 1 enforce syntax for ld insns. */ -#define SYNTAX_LD_NE (SYNTAX_ST_NE + 1) - { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax }, +static unsigned +insert_rad (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Improper register value."); -/* 0 enforce syntax for st insns. */ -#define SYNTAX_ST (SYNTAX_LD_NE + 1) - { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax }, + return insn | (value & 0x3F); +} -/* 0 enforce syntax for ld insns. */ -#define SYNTAX_LD (SYNTAX_ST + 1) - { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax }, +static unsigned +insert_rcd (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value & 0x01) + *errmsg = _("Improper register value."); -/* Flag update bit (insertion is defered until we know how). */ -#define FLAG (SYNTAX_LD + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, + return insn | ((value & 0x3F) << 6); +} -/* Fake utility operand to finish 'f' suffix handling. */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, +/* Dummy insert ZERO operand function. */ -/* Fake utility operand to set the 'f' flag for the "flag" insn. */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, +static unsigned +insert_za (unsigned insn, + int value, + const char **errmsg) +{ + if (value) + *errmsg = _("operand is not zero"); + return insn; +} -/* Branch delay types. */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 }, +/* Insert Y-bit in bbit/br instructions. This function is called only + when solving fixups. */ -/* Conditions. */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, +static unsigned +insert_Ybit (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value > 0) + insn |= 0x08; -/* Set `cond_p' to 1 to ensure a constant is treated as a limm. */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 }, + return insn; +} -/* Branch address; b, bl, and lp insns. */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr }, +/* Insert Y-bit in bbit/br instructions. This function is called only + when solving fixups. */ -/* Jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2). */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 }, +static unsigned +insert_NYbit (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 0) + insn |= 0x08; -/* Jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */ -#define JUMPFLAGS (JUMP + 1) - { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags }, + return insn; +} -/* Size field, stored in bit 1,2. */ -#define SIZE1 (JUMPFLAGS + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 }, +/* Insert H register into a 16-bit opcode. */ -/* Size field, stored in bit 10,11. */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 }, +static unsigned +insert_rhv1 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07); +} -/* Size field, stored in bit 22,23. */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 }, +static int +extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; -/* Sign extend field, stored in bit 0. */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Sign extend field, stored in bit 9. */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Address write back, stored in bit 3. */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Address write back, stored in bit 12. */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Address write back, stored in bit 24. */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0}, - -/* Cache bypass, stored in bit 5. */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Cache bypass, stored in bit 14. */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Cache bypass, stored in bit 26. */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 }, - -/* Unop macro, used to copy REGB to REGC. */ -#define UNOPMACRO (CACHEBYPASS26 + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT, 0, 0 }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG, 0, 0 }, + return value; +} -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 }, +/* Insert H register into a 16-bit opcode. */ -/* End of list place holder. */ - { 0, 0, 0, 0, 0, 0 } -}; - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) +static unsigned +insert_rhv2 (unsigned insn, + int value, + const char **errmsg) { - static char buf[100]; - enum operand op_type = OP_NONE; + if (value == 0x1E) + *errmsg = + _("Register R30 is a limm indicator for this type of instruction."); + return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03); +} - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker; - - op_type = OP_SHIMM; - /* Forget about shimm as dest mlm. */ - - if ('a' != operand->fmt) - { - shimm_p = 1; - shimm = value; - flagshimm_handled_p = 1; - marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - } - else - { - /* Don't request flag setting on shimm as dest. */ - marker = ARC_REG_SHIMM; - } - insn |= marker << operand->shift; - /* insn |= value & 511; - done later. */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - op_type = OP_LIMM; - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - *errmsg = _("unable to fit different valued constants into instruction"); - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); - else - { - if ((insn & I(-1)) == I(2)) /* Check for use validity. */ - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } - else - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); - } - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* check for use validity. */ - if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) - { - if (reg->flags & ARC_REGISTER_READONLY) - *errmsg = _("attempt to set readonly register"); - } - if ('a' != operand->fmt) - { - if (reg->flags & ARC_REGISTER_WRITEONLY) - *errmsg = _("attempt to read writeonly register"); - } - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - sprintf (buf, _("invalid register number `%d'"), reg->value); - *errmsg = buf; - } - insn |= reg->value << operand->shift; - op_type = OP_REG; - } - } +static int +extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3); - switch (operand->fmt) - { - case 'a': - ls_operand[LS_DEST] = op_type; - break; - case 's': - ls_operand[LS_BASE] = op_type; - break; - case 'c': - if ((insn & I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; - break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; - break; - } + return value; +} +static unsigned +insert_r0 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value != 0) + *errmsg = _("Register must be R0."); return insn; } -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static int +extract_r0 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - return insn; + return 0; } -/* Called when we see an nullify condition. */ -static arc_insn -insert_nullify (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg ATTRIBUTE_UNUSED) +static unsigned +insert_r1 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - nullify_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - nullify = value; + if (value != 1) + *errmsg = _("Register must be R1."); return insn; } -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static int +extract_r1 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; + return 1; } -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg ATTRIBUTE_UNUSED) +static unsigned +insert_r2 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; + if (value != 2) + *errmsg = _("Register must be R2."); return insn; } -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static int +extract_r2 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - cond_p = 1; - return insn; + return 2; } -static arc_insn -insert_addr_wb (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static unsigned +insert_r3 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - addrwb_p = 1 << operand->shift; + if (value != 3) + *errmsg = _("Register must be R3."); return insn; } -static arc_insn -insert_base (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) +static int +extract_r3 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift; - insn |= B(myinsn); - ls_operand[LS_BASE] = OP_REG; - } - else if (ARC_SHIMM_CONST_P (value) && !cond_p) - { - if (shimm_p && value != shimm) - { - /* Convert the previous shimm operand to a limm. */ - limm_p = 1; - limm = shimm; - insn &= ~C(-1); /* We know where the value is in insn. */ - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - insn |= ARC_REG_SHIMM << operand->shift; - shimm_p = 1; - shimm = value; - ls_operand[LS_BASE] = OP_SHIMM; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - else - { - if (limm_p && value != limm) - { - *errmsg = _("too many long constants"); - return insn; - } - limm_p = 1; - limm = value; - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - - return insn; + return 3; } -/* Used in ld/st insns to handle the offset field. We don't try to - match operand syntax here. we catch bad combinations later. */ - -static arc_insn -insert_offset (arc_insn insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value *reg, - long value, - const char **errmsg) +static unsigned +insert_sp (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - long minval, maxval; - - if (reg != NULL) - { - arc_insn myinsn; - myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift; - ls_operand[LS_OFFSET] = OP_REG; - if (operand->flags & ARC_OPERAND_LOAD) /* Not if store, catch it later. */ - if ((insn & I(-1)) != I(1)) /* Not if opcode == 1, catch it later. */ - insn |= C (myinsn); - } - else - { - /* This is *way* more general than necessary, but maybe some day it'll - be useful. */ - if (operand->flags & ARC_OPERAND_SIGNED) - { - minval = -(1 << (operand->bits - 1)); - maxval = (1 << (operand->bits - 1)) - 1; - } - else - { - minval = 0; - maxval = (1 << operand->bits) - 1; - } - if ((cond_p && !limm_p) || (value < minval || value > maxval)) - { - if (limm_p && value != limm) - *errmsg = _("too many long constants"); - - else - { - limm_p = 1; - limm = value; - if (operand->flags & ARC_OPERAND_STORE) - insn |= B(ARC_REG_LIMM); - if (operand->flags & ARC_OPERAND_LOAD) - insn |= C(ARC_REG_LIMM); - ls_operand[LS_OFFSET] = OP_LIMM; - } - } - else - { - if ((value < minval || value > maxval)) - *errmsg = "need too many limms"; - else if (shimm_p && value != shimm) - { - /* Check for bad operand combinations - before we lose info about them. */ - if ((insn & I(-1)) == I(1)) - { - *errmsg = _("too many shimms in load"); - goto out; - } - if (limm_p && operand->flags & ARC_OPERAND_LOAD) - { - *errmsg = _("too many long constants"); - goto out; - } - /* Convert what we thought was a shimm to a limm. */ - limm_p = 1; - limm = shimm; - if (ls_operand[LS_VALUE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~C(-1); - insn |= C(ARC_REG_LIMM); - ls_operand[LS_VALUE] = OP_LIMM; - } - if (ls_operand[LS_BASE] == OP_SHIMM - && operand->flags & ARC_OPERAND_STORE) - { - insn &= ~B(-1); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - } - shimm = value; - shimm_p = 1; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - out: + if (value != 28) + *errmsg = _("Register must be SP."); return insn; } -/* Used in st insns to do final disasemble syntax check. */ - -static long -extract_st_syntax (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static int +extract_sp (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { -#define ST_SYNTAX(V,B,O) \ -((ls_operand[LS_VALUE] == (V) && \ - ls_operand[LS_BASE] == (B) && \ - ls_operand[LS_OFFSET] == (O))) - - if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) - || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0) - || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE) - || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM))) - *invalid = 1; - return 0; + return 28; } -int -arc_limm_fixup_adjust (arc_insn insn) +static unsigned +insert_gp (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - int retval = 0; - - /* Check for st shimm,[limm]. */ - if ((insn & (I(-1) | C(-1) | B(-1))) == - (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM))) - { - retval = insn & 0x1ff; - if (retval & 0x100) /* Sign extend 9 bit offset. */ - retval |= ~0x1ff; - } - return -retval; /* Negate offset for return. */ + if (value != 26) + *errmsg = _("Register must be GP."); + return insn; } -/* Used in st insns to do final syntax check. */ - -static arc_insn -insert_st_syntax (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) +static int +extract_gp (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - if (ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) && shimm != 0) - { - /* Change an illegal insn into a legal one, it's easier to - do it here than to try to handle it during operand scan. */ - limm_p = 1; - limm = shimm; - shimm_p = 0; - shimm = 0; - insn = insn & ~(C(-1) | 511); - insn |= ARC_REG_LIMM << ARC_SHIFT_REGC; - ls_operand[LS_VALUE] = OP_LIMM; - } - - if (ST_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) - || ST_SYNTAX (OP_LIMM, OP_SHIMM, OP_NONE)) - { - /* Try to salvage this syntax. */ - if (shimm & 0x1) /* Odd shimms won't work. */ - { - if (limm_p) /* Do we have a limm already? */ - *errmsg = _("impossible store"); - - limm_p = 1; - limm = shimm; - shimm = 0; - shimm_p = 0; - insn = insn & ~(B(-1) | 511); - insn |= B(ARC_REG_LIMM); - ls_operand[LS_BASE] = OP_LIMM; - } - else - { - shimm >>= 1; - insn = insn & ~511; - insn |= shimm; - ls_operand[LS_OFFSET] = OP_SHIMM; - } - } - if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)) - limm += arc_limm_fixup_adjust(insn); - - if (! (ST_SYNTAX (OP_REG,OP_REG,OP_NONE) - || ST_SYNTAX (OP_REG,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_REG,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_REG,OP_SHIMM,OP_SHIMM) - || (ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0)) - || ST_SYNTAX (OP_SHIMM,OP_LIMM,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_SHIMM,OP_REG,OP_SHIMM) - || ST_SYNTAX (OP_SHIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_SHIMM,OP_SHIMM) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_NONE) - || ST_SYNTAX (OP_LIMM,OP_REG,OP_SHIMM))) - *errmsg = _("st operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; - } - if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm) - *errmsg = _("store value must be zero"); - return insn; + return 26; } -/* Used in ld insns to do final syntax check. */ - -static arc_insn -insert_ld_syntax (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) +static unsigned +insert_pcl (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { -#define LD_SYNTAX(D, B, O) \ - ( (ls_operand[LS_DEST] == (D) \ - && ls_operand[LS_BASE] == (B) \ - && ls_operand[LS_OFFSET] == (O))) - - int test = insn & I (-1); - - if (!(test == I (1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *errmsg = _("invalid load/shimm insn"); - } - if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE) - || LD_SYNTAX(OP_REG,OP_REG,OP_REG) - || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1))) - || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1))) - || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM) - || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1))))) - *errmsg = _("ld operand error"); - if (addrwb_p) - { - if (ls_operand[LS_BASE] != OP_REG) - *errmsg = _("address writeback not allowed"); - insn |= addrwb_p; - } + if (value != 63) + *errmsg = _("Register must be PCL."); return insn; } -/* Used in ld insns to do final syntax check. */ - -static long -extract_ld_syntax (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static int +extract_pcl (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int test = insn[0] & I(-1); - - if (!(test == I(1))) - { - if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM - || ls_operand[LS_OFFSET] == OP_SHIMM)) - *invalid = 1; - } - if (!( (LD_SYNTAX (OP_REG, OP_REG, OP_NONE) && (test == I(1))) - || LD_SYNTAX (OP_REG, OP_REG, OP_REG) - || LD_SYNTAX (OP_REG, OP_REG, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_REG, OP_LIMM) && !(test == I(1))) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_REG) && !(test == I(1))) - || (LD_SYNTAX (OP_REG, OP_SHIMM, OP_NONE) && (shimm == 0)) - || LD_SYNTAX (OP_REG, OP_SHIMM, OP_SHIMM) - || (LD_SYNTAX (OP_REG, OP_LIMM, OP_NONE) && (test == I(1))))) - *invalid = 1; - return 0; + return 63; } -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ - -static arc_insn -insert_shimmfinish (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static unsigned +insert_blink (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; + if (value != 31) + *errmsg = _("Register must be BLINK."); return insn; } -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static int +extract_blink (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - return insn; + return 31; } -static arc_insn -insert_jumpflags (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg) +static unsigned +insert_ilink1 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - if (!flag_p) - *errmsg = _("jump flags, but no .f seen"); - - else if (!limm_p) - *errmsg = _("jump flags, but no limm addr"); - - else if (limm & 0xfc000000) - *errmsg = _("flag bits of jump address limm lost"); - - else if (limm & 0x03000000) - *errmsg = _("attempt to set HR bits"); - - else if ((value & ((1 << operand->bits) - 1)) != value) - *errmsg = _("bad jump flags value"); - - jumpflags_p = 1; - limm = ((limm & ((1 << operand->shift) - 1)) - | ((value & ((1 << operand->bits) - 1)) << operand->shift)); + if (value != 29) + *errmsg = _("Register must be ILINK1."); return insn; } -/* Called at the end of unary operand macros to copy the B field to C. */ - -static arc_insn -insert_unopmacro (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg ATTRIBUTE_UNUSED) +static int +extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; + return 29; } -/* Insert a relative address for a branch insn (b, bl, or lp). */ - -static arc_insn -insert_reladdr (arc_insn insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value, - const char **errmsg) +static unsigned +insert_ilink2 (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; + if (value != 30) + *errmsg = _("Register must be ILINK2."); return insn; } -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's little for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. - - We do check for correct usage of the nullify suffix, or we - set the default correctly, though. */ +static int +extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return 30; +} -static arc_insn -insert_absaddr (arc_insn insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value *reg ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - const char **errmsg) +static unsigned +insert_ras (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - if (limm_p) + switch (value) { - /* If it is a jump and link, .jd must be specified. */ - if (insn & R (-1, 9, 1)) - { - if (!nullify_p) - insn |= 0x02 << 5; /* Default nullify to .jd. */ - - else if (nullify != 0x02) - *errmsg = _("must specify .jd or no nullify suffix"); - } + case 0: + case 1: + case 2: + case 3: + insn |= value; + break; + case 12: + case 13: + case 14: + case 15: + insn |= (value - 8); + break; + default: + *errmsg = _("Register must be either r0-r3 or r12-r15."); + break; } return insn; } - -/* Extraction functions. - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ - -/* Called by the disassembler before printing an instruction. */ - -void -arc_opcode_init_extract (void) +static int +extract_ras (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - arc_opcode_init_insert (); + int value = insn & 0x07; + if (value > 3) + return (value + 8); + else + return value; } -static const struct arc_operand_value * -lookup_register (int type, long regno) +static unsigned +insert_rbs (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - const struct arc_operand_value *r,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; - - while (ext_oper) + switch (value) { - if (ext_oper->operand.type == type && ext_oper->operand.value == regno) - return (&ext_oper->operand); - ext_oper = ext_oper->next; + case 0: + case 1: + case 2: + case 3: + insn |= value << 8; + break; + case 12: + case 13: + case 14: + case 15: + insn |= ((value - 8)) << 8; + break; + default: + *errmsg = _("Register must be either r0-r3 or r12-r15."); + break; } - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; + return insn; } -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. - - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ - -static long -extract_reg (arc_insn *insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) +static int +extract_rbs (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int regno; - long value; - enum operand op_type; - - /* Get the register number. */ - regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1); + int value = (insn >> 8) & 0x07; + if (value > 3) + return (value + 8); + else + return value; +} - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - op_type = OP_SHIMM; - /* Always return zero if dest is a shimm mlm. */ - - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - if (!flagshimm_handled_p) - flag_p = 0; - flagshimm_handled_p = 1; - } - else - value = 0; - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - op_type = OP_SHIMM; - - /* Always return zero if dest is a shimm mlm. */ - if ('a' != operand->fmt) - { - value = *insn & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - } - else - value = 0; - - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) +static unsigned +insert_rcs (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + switch (value) { - op_type = OP_LIMM; - value = insn[1]; - limm_p = 1; - - /* If this is a jump instruction (j,jl), show new pc correctly. */ - if (0x07 == ((*insn & I(-1)) >> 27)) - value = (value & 0xffffff); + case 0: + case 1: + case 2: + case 3: + insn |= value << 5; + break; + case 12: + case 13: + case 14: + case 15: + insn |= ((value - 8)) << 5; + break; + default: + *errmsg = _("Register must be either r0-r3 or r12-r15."); + break; } + return insn; +} - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ +static int +extract_rcs (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 5) & 0x07; + if (value > 3) + return (value + 8); else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); - - op_type = OP_REG; - - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } - - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); - - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } + return value; +} - switch(operand->fmt) +static unsigned +insert_simm3s (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + int tmp = 0; + switch (value) { - case 'a': - ls_operand[LS_DEST] = op_type; + case -1: + tmp = 0x07; break; - case 's': - ls_operand[LS_BASE] = op_type; + case 0: + tmp = 0x00; + break; + case 1: + tmp = 0x01; break; - case 'c': - if ((insn[0]& I(-1)) == I(2)) - ls_operand[LS_VALUE] = op_type; - else - ls_operand[LS_OFFSET] = op_type; + case 2: + tmp = 0x02; break; - case 'o': case 'O': - ls_operand[LS_OFFSET] = op_type; + case 3: + tmp = 0x03; + break; + case 4: + tmp = 0x04; + break; + case 5: + tmp = 0x05; + break; + case 6: + tmp = 0x06; + break; + default: + *errmsg = _("Accepted values are from -1 to 6."); break; } - return value; + insn |= tmp << 8; + return insn; } -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ - -static long -extract_flag (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) +static int +extract_simm3s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int f; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - f = flag_p != 0; + int value = (insn >> 8) & 0x07; + if (value == 7) + return -1; else - f = (*insn & (1 << operand->shift)) != 0; - - /* There is no text for zero values. */ - if (f == 0) - return 0; - flag_p = 1; - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; + return value; } -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval, - int *invalid ATTRIBUTE_UNUSED) +static unsigned +insert_rrange (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - long cond; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - return 0; - - cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); - - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; + int reg1 = (value >> 16) & 0xFFFF; + int reg2 = value & 0xFFFF; + if (reg1 != 13) + { + *errmsg = _("First register of the range should be r13."); + return insn; + } + if (reg2 < 13 || reg2 > 26) + { + *errmsg = _("Last register of the range doesn't fit."); + return insn; + } + insn |= ((reg2 - 12) & 0x0F) << 1; + return insn; } -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ +static int +extract_rrange (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 1) & 0x0F; +} -static long -extract_reladdr (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid ATTRIBUTE_UNUSED) +static unsigned +insert_fpel (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - long addr; + if (value != 27) + { + *errmsg = _("Invalid register number, should be fp."); + return insn; + } - addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - return addr << 2; + insn |= 0x0100; + return insn; } -/* Extract the flags bits from a j or jl long immediate. */ - -static long -extract_jumpflags (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static int +extract_fpel (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - if (!flag_p || !limm_p) - *invalid = 1; - return ((flag_p && limm_p) - ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0); + return (insn & 0x0100) ? 27 : -1; } -/* Extract st insn's offset. */ - -static long -extract_st_offset (arc_insn *insn, - const struct arc_operand *operand, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static unsigned +insert_blinkel (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) { - int value = 0; - - if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM) + if (value != 31) { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; + *errmsg = _("Invalid register number, should be blink."); + return insn; } - else - *invalid = 1; - return value; + insn |= 0x0200; + return insn; } -/* Extract ld insn's offset. */ - -static long -extract_ld_offset (arc_insn *insn, - const struct arc_operand *operand, - int mods, - const struct arc_operand_value **opval, - int *invalid) +static int +extract_blinkel (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - int test = insn[0] & I(-1); - int value; + return (insn & 0x0200) ? 31 : -1; +} - if (test) +static unsigned +insert_pclel (unsigned insn, + int value, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value != 63) { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256)) - value -= 512; - if (value) - ls_operand[LS_OFFSET] = OP_SHIMM; - - return value; + *errmsg = _("Invalid register number, should be pcl."); + return insn; } - /* If it isn't in the insn, it's concealed behind reg 'c'. */ - return extract_reg (insn, &arc_operands[arc_operand_map['c']], - mods, opval, invalid); -} -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ + insn |= 0x0400; + return insn; +} -static long -extract_unopmacro (arc_insn *insn, - const struct arc_operand *operand ATTRIBUTE_UNUSED, - int mods ATTRIBUTE_UNUSED, - const struct arc_operand_value **opval ATTRIBUTE_UNUSED, - int *invalid) +static int +extract_pclel (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - return 0; + return (insn & 0x0400) ? 63 : -1; } - -/* ARC instructions. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. - - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. */ -struct arc_opcode arc_opcodes[] = +#define INSERT_W6 +/* mask = 00000000000000000000111111000000 + insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */ +static unsigned +insert_w6 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - /* Base case instruction set (core versions 5-8). */ - - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 }, - /* "nop" is really an "xor". */ - { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 }, - { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 }, - { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 }, - { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 }, - { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 }, - { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 }, - /* %Q: force cond_p=1 -> no shimm values. This insn allows an - optional flags spec. */ - { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* This insn allows an optional flags spec. */ - { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. - "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 }, - { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 }, - { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 }, - { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 }, - { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 }, - /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */ - { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 } -}; + insn |= ((value >> 0) & 0x003f) << 6; -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); + return insn; +} -const struct arc_operand_value arc_reg_names[] = +#define EXTRACT_W6 +/* mask = 00000000000000000000111111000000. */ +static int +extract_w6 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) { - /* Core register set r0-r63. */ - - /* r0-r28 - general purpose registers. */ - { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 }, - { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 }, - { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 }, - { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 }, - { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 }, - { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 }, - { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 }, - { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 }, - { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 }, - { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink1", 29, REG, 0 }, - /* Maskable interrupt link register. */ - { "ilink2", 30, REG, 0 }, - /* Branch-link register. */ - { "blink", 31, REG, 0 }, - - /* r32-r59 reserved for extensions. */ - { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 }, - { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 }, - { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 }, - { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 }, - { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 }, - { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 }, - { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 }, - { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 }, - { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 }, - { "r59", 59, REG, 0 }, - - /* Loop count register (24 bits). */ - { "lp_count", 60, REG, 0 }, - /* Short immediate data indicator setting flags. */ - { "r61", 61, REG, ARC_REGISTER_READONLY }, - /* Long immediate data indicator setting flags. */ - { "r62", 62, REG, ARC_REGISTER_READONLY }, - /* Short immediate data indicator not setting flags. */ - { "r63", 63, REG, ARC_REGISTER_READONLY }, - - /* Small-data base register. */ - { "gp", 26, REG, 0 }, - /* Frame pointer. */ - { "fp", 27, REG, 0 }, - /* Stack pointer. */ - { "sp", 28, REG, 0 }, - - { "r29", 29, REG, 0 }, - { "r30", 30, REG, 0 }, - { "r31", 31, REG, 0 }, - { "r60", 60, REG, 0 }, - - /* Auxiliary register set. */ - - /* Auxiliary register address map: - 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation - 0xfffffeff-0x80000000 - customer limm allocation - 0x7fffffff-0x00000100 - ARC limm allocation - 0x000000ff-0x00000000 - ARC shimm allocation */ - - /* Base case auxiliary registers (shimm address). */ - { "status", 0x00, AUXREG, 0 }, - { "semaphore", 0x01, AUXREG, 0 }, - { "lp_start", 0x02, AUXREG, 0 }, - { "lp_end", 0x03, AUXREG, 0 }, - { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY }, - { "debug", 0x05, AUXREG, 0 }, -}; + unsigned value = 0; -const int arc_reg_names_count = - sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); + value |= ((insn >> 6) & 0x003f) << 0; -/* The suffix table. - Operands with the same name must be stored together. */ + return value; +} -const struct arc_operand_value arc_suffixes[] = +#define INSERT_G_S +/* mask = 0000011100022000 + insn = 01000ggghhhGG0HH. */ +static unsigned +insert_g_s (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1, 0 }, - - /* Base case condition codes. */ - { "al", 0, COND, 0 }, - { "ra", 0, COND, 0 }, - { "eq", 1, COND, 0 }, - { "z", 1, COND, 0 }, - { "ne", 2, COND, 0 }, - { "nz", 2, COND, 0 }, - { "pl", 3, COND, 0 }, - { "p", 3, COND, 0 }, - { "mi", 4, COND, 0 }, - { "n", 4, COND, 0 }, - { "cs", 5, COND, 0 }, - { "c", 5, COND, 0 }, - { "lo", 5, COND, 0 }, - { "cc", 6, COND, 0 }, - { "nc", 6, COND, 0 }, - { "hs", 6, COND, 0 }, - { "vs", 7, COND, 0 }, - { "v", 7, COND, 0 }, - { "vc", 8, COND, 0 }, - { "nv", 8, COND, 0 }, - { "gt", 9, COND, 0 }, - { "ge", 10, COND, 0 }, - { "lt", 11, COND, 0 }, - { "le", 12, COND, 0 }, - { "hi", 13, COND, 0 }, - { "ls", 14, COND, 0 }, - { "pnz", 15, COND, 0 }, - - /* Condition codes 16-31 reserved for extensions. */ - - { "f", 1, FLAG, 0 }, - - { "nd", ARC_DELAY_NONE, DELAY, 0 }, - { "d", ARC_DELAY_NORMAL, DELAY, 0 }, - { "jd", ARC_DELAY_JUMP, DELAY, 0 }, - - { "b", 1, SIZE1, 0 }, - { "b", 1, SIZE10, 0 }, - { "b", 1, SIZE22, 0 }, - { "w", 2, SIZE1, 0 }, - { "w", 2, SIZE10, 0 }, - { "w", 2, SIZE22, 0 }, - { "x", 1, SIGN0, 0 }, - { "x", 1, SIGN9, 0 }, - { "a", 1, ADDRESS3, 0 }, - { "a", 1, ADDRESS12, 0 }, - { "a", 1, ADDRESS24, 0 }, - - { "di", 1, CACHEBYPASS5, 0 }, - { "di", 1, CACHEBYPASS14, 0 }, - { "di", 1, CACHEBYPASS26, 0 }, -}; + insn |= ((value >> 0) & 0x0007) << 8; + insn |= ((value >> 3) & 0x0003) << 3; -const int arc_suffixes_count = - sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; + return insn; +} -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ +#define EXTRACT_G_S +/* mask = 0000011100022000. */ +static int +extract_g_s (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = 0; -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; + value |= ((insn >> 8) & 0x0007) << 0; + value |= ((insn >> 3) & 0x0003) << 3; -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ + /* Extend the sign. */ + int signbit = 1 << (6 - 1); + value = (value ^ signbit) - signbit; -int -arc_get_opcode_mach (int bfd_mach, int big_p) -{ - static int mach_type_map[] = - { - ARC_MACH_5, - ARC_MACH_6, - ARC_MACH_7, - ARC_MACH_8 - }; - return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); + return value; } -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). +/* Include the generic extract/insert functions. Order is important + as some of the functions present in the .h may be disabled via + defines. */ +#include "arc-fxi.h" - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ +/* Abbreviations for instruction subsets. */ +#define BASE ARC_OPCODE_BASE -void -arc_opcode_init_tables (int flags) -{ - static int init_p = 0; +/* The flag operands table. - cpu_type = flags; + The format of the table is + NAME CODE BITS SHIFT FAVAIL. */ +const struct arc_flag_operand arc_flag_operands[] = +{ +#define F_NULL 0 + { 0, 0, 0, 0, 0}, +#define F_ALWAYS (F_NULL + 1) + { "al", 0, 0, 0, 0 }, +#define F_RA (F_ALWAYS + 1) + { "ra", 0, 0, 0, 0 }, +#define F_EQUAL (F_RA + 1) + { "eq", 1, 5, 0, 1 }, +#define F_ZERO (F_EQUAL + 1) + { "z", 1, 5, 0, 0 }, +#define F_NOTEQUAL (F_ZERO + 1) + { "ne", 2, 5, 0, 1 }, +#define F_NOTZERO (F_NOTEQUAL + 1) + { "nz", 2, 5, 0, 0 }, +#define F_POZITIVE (F_NOTZERO + 1) + { "p", 3, 5, 0, 1 }, +#define F_PL (F_POZITIVE + 1) + { "pl", 3, 5, 0, 0 }, +#define F_NEGATIVE (F_PL + 1) + { "n", 4, 5, 0, 1 }, +#define F_MINUS (F_NEGATIVE + 1) + { "mi", 4, 5, 0, 0 }, +#define F_CARRY (F_MINUS + 1) + { "c", 5, 5, 0, 1 }, +#define F_CARRYSET (F_CARRY + 1) + { "cs", 5, 5, 0, 0 }, +#define F_LOWER (F_CARRYSET + 1) + { "lo", 5, 5, 0, 0 }, +#define F_CARRYCLR (F_LOWER + 1) + { "cc", 6, 5, 0, 0 }, +#define F_NOTCARRY (F_CARRYCLR + 1) + { "nc", 6, 5, 0, 1 }, +#define F_HIGHER (F_NOTCARRY + 1) + { "hs", 6, 5, 0, 0 }, +#define F_OVERFLOWSET (F_HIGHER + 1) + { "vs", 7, 5, 0, 0 }, +#define F_OVERFLOW (F_OVERFLOWSET + 1) + { "v", 7, 5, 0, 1 }, +#define F_NOTOVERFLOW (F_OVERFLOW + 1) + { "nv", 8, 5, 0, 1 }, +#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1) + { "vc", 8, 5, 0, 0 }, +#define F_GT (F_OVERFLOWCLR + 1) + { "gt", 9, 5, 0, 1 }, +#define F_GE (F_GT + 1) + { "ge", 10, 5, 0, 1 }, +#define F_LT (F_GE + 1) + { "lt", 11, 5, 0, 1 }, +#define F_LE (F_LT + 1) + { "le", 12, 5, 0, 1 }, +#define F_HI (F_LE + 1) + { "hi", 13, 5, 0, 1 }, +#define F_LS (F_HI + 1) + { "ls", 14, 5, 0, 1 }, +#define F_PNZ (F_LS + 1) + { "pnz", 15, 5, 0, 1 }, + + /* FLAG. */ +#define F_FLAG (F_PNZ + 1) + { "f", 1, 1, 15, 1 }, +#define F_FFAKE (F_FLAG + 1) + { "f", 0, 0, 0, 1 }, + + /* Delay slot. */ +#define F_ND (F_FFAKE + 1) + { "nd", 0, 1, 5, 0 }, +#define F_D (F_ND + 1) + { "d", 1, 1, 5, 1 }, +#define F_DFAKE (F_D + 1) + { "d", 0, 0, 0, 1 }, + + /* Data size. */ +#define F_SIZEB1 (F_DFAKE + 1) + { "b", 1, 2, 1, 1 }, +#define F_SIZEB7 (F_SIZEB1 + 1) + { "b", 1, 2, 7, 1 }, +#define F_SIZEB17 (F_SIZEB7 + 1) + { "b", 1, 2, 17, 1 }, +#define F_SIZEW1 (F_SIZEB17 + 1) + { "w", 2, 2, 1, 0 }, +#define F_SIZEW7 (F_SIZEW1 + 1) + { "w", 2, 2, 7, 0 }, +#define F_SIZEW17 (F_SIZEW7 + 1) + { "w", 2, 2, 17, 0 }, + + /* Sign extension. */ +#define F_SIGN6 (F_SIZEW17 + 1) + { "x", 1, 1, 6, 1 }, +#define F_SIGN16 (F_SIGN6 + 1) + { "x", 1, 1, 16, 1 }, +#define F_SIGNX (F_SIGN16 + 1) + { "x", 0, 0, 0, 1 }, + + /* Address write-back modes. */ +#define F_A3 (F_SIGNX + 1) + { "a", 1, 2, 3, 0 }, +#define F_A9 (F_A3 + 1) + { "a", 1, 2, 9, 0 }, +#define F_A22 (F_A9 + 1) + { "a", 1, 2, 22, 0 }, +#define F_AW3 (F_A22 + 1) + { "aw", 1, 2, 3, 1 }, +#define F_AW9 (F_AW3 + 1) + { "aw", 1, 2, 9, 1 }, +#define F_AW22 (F_AW9 + 1) + { "aw", 1, 2, 22, 1 }, +#define F_AB3 (F_AW22 + 1) + { "ab", 2, 2, 3, 1 }, +#define F_AB9 (F_AB3 + 1) + { "ab", 2, 2, 9, 1 }, +#define F_AB22 (F_AB9 + 1) + { "ab", 2, 2, 22, 1 }, +#define F_AS3 (F_AB22 + 1) + { "as", 3, 2, 3, 1 }, +#define F_AS9 (F_AS3 + 1) + { "as", 3, 2, 9, 1 }, +#define F_AS22 (F_AS9 + 1) + { "as", 3, 2, 22, 1 }, +#define F_ASFAKE (F_AS22 + 1) + { "as", 0, 0, 0, 1 }, + + /* Cache bypass. */ +#define F_DI5 (F_ASFAKE + 1) + { "di", 1, 1, 5, 1 }, +#define F_DI11 (F_DI5 + 1) + { "di", 1, 1, 11, 1 }, +#define F_DI15 (F_DI11 + 1) + { "di", 1, 1, 15, 1 }, + + /* ARCv2 specific. */ +#define F_NT (F_DI15 + 1) + { "nt", 0, 1, 3, 1}, +#define F_T (F_NT + 1) + { "t", 1, 1, 3, 1}, +#define F_H1 (F_T + 1) + { "h", 2, 2, 1, 1 }, +#define F_H7 (F_H1 + 1) + { "h", 2, 2, 7, 1 }, +#define F_H17 (F_H7 + 1) + { "h", 2, 2, 17, 1 }, + + /* Fake Flags. */ +#define F_NE (F_H17 + 1) + { "ne", 0, 0, 0, 1 }, +}; - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - if (!init_p) - { - int i,n; +const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; +/* Table of the flag classes. - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); + The format of the table is + CLASS {FLAG_CODE}. */ +const struct arc_flag_class arc_flag_classes[] = +{ +#define C_EMPTY 0 + { FNONE, { F_NULL } }, + +#define C_CC (C_EMPTY + 1) + { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, + F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, + F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, + F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + +#define C_AA_ADDR3 (C_CC + 1) +#define C_AA27 (C_CC + 1) + { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } }, +#define C_AA_ADDR9 (C_AA_ADDR3 + 1) +#define C_AA21 (C_AA_ADDR3 + 1) + { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } }, +#define C_AA_ADDR22 (C_AA_ADDR9 + 1) +#define C_AA8 (C_AA_ADDR9 + 1) + { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } }, + +#define C_F (C_AA_ADDR22 + 1) + { FLG, { F_FLAG, F_NULL } }, +#define C_FHARD (C_F + 1) + { FLG, { F_FFAKE, F_NULL } }, + +#define C_T (C_FHARD + 1) + { SBP, { F_NT, F_T, F_NULL } }, +#define C_D (C_T + 1) + { DLY, { F_ND, F_D, F_NULL } }, + +#define C_DHARD (C_D + 1) + { DLY, { F_DFAKE, F_NULL } }, + +#define C_DI20 (C_DHARD + 1) + { DIF, { F_DI11, F_NULL }}, +#define C_DI16 (C_DI20 + 1) + { DIF, { F_DI15, F_NULL }}, +#define C_DI26 (C_DI16 + 1) + { DIF, { F_DI5, F_NULL }}, + +#define C_X25 (C_DI26 + 1) + { SGX, { F_SIGN6, F_NULL }}, +#define C_X15 (C_X25 + 1) + { SGX, { F_SIGN16, F_NULL }}, +#define C_XHARD (C_X15 + 1) +#define C_X (C_X15 + 1) + { SGX, { F_SIGNX, F_NULL }}, + +#define C_ZZ13 (C_X + 1) + { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}}, +#define C_ZZ23 (C_ZZ13 + 1) + { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}}, +#define C_ZZ29 (C_ZZ23 + 1) + { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}}, + +#define C_AS (C_ZZ29 + 1) + { SZM, { F_ASFAKE, F_NULL}}, + +#define C_NE (C_AS + 1) + { CND, { F_NE, F_NULL}}, +}; - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; +/* The operands table. - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } + The format of the operands table is: - init_p = 1; - } -} - -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (const struct arc_opcode *opcode) + BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */ +const struct arc_operand arc_operands[] = { - if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type) - return 1; - return 0; -} - -/* Return the first insn in the chain for assembling INSN. */ + /* The fields are bits, shift, insert, extract, flags. The zero + index is used to indicate end-of-list. */ +#define UNUSED 0 + { 0, 0, 0, 0, 0, 0 }, + /* The plain integer register fields. Used by 32 bit + instructions. */ +#define RA (UNUSED + 1) + { 6, 0, 0, ARC_OPERAND_IR, 0, 0 }, +#define RB (RA + 1) + { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb }, +#define RC (RB + 1) + { 6, 6, 0, ARC_OPERAND_IR, 0, 0 }, +#define RBdup (RC + 1) + { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb }, + +#define RAD (RBdup + 1) + { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 }, +#define RCD (RAD + 1) + { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 }, + + /* The plain integer register fields. Used by short + instructions. */ +#define RA16 (RCD + 1) +#define RA_S (RCD + 1) + { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras }, +#define RB16 (RA16 + 1) +#define RB_S (RA16 + 1) + { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs }, +#define RB16dup (RB16 + 1) +#define RB_Sdup (RB16 + 1) + { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs }, +#define RC16 (RB16dup + 1) +#define RC_S (RB16dup + 1) + { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs }, +#define R6H (RC16 + 1) /* 6bit register field 'h' used + by V1 cpus. */ + { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 }, +#define R5H (R6H + 1) /* 5bit register field 'h' used + by V2 cpus. */ +#define RH_S (R6H + 1) /* 5bit register field 'h' used + by V2 cpus. */ + { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 }, +#define R5Hdup (R5H + 1) +#define RH_Sdup (R5H + 1) + { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, + insert_rhv2, extract_rhv2 }, + +#define RG (R5Hdup + 1) +#define G_S (R5Hdup + 1) + { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s }, + + /* Fix registers. */ +#define R0 (RG + 1) +#define R0_S (RG + 1) + { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 }, +#define R1 (R0 + 1) +#define R1_S (R0 + 1) + { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 }, +#define R2 (R1 + 1) +#define R2_S (R1 + 1) + { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 }, +#define R3 (R2 + 1) +#define R3_S (R2 + 1) + { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 }, +#define SP (R3 + 1) +#define SP_S (R3 + 1) + { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp }, +#define SPdup (SP + 1) +#define SP_Sdup (SP + 1) + { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp }, +#define GP (SPdup + 1) +#define GP_S (SPdup + 1) + { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp }, + +#define PCL_S (GP + 1) + { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl }, + +#define BLINK (PCL_S + 1) +#define BLINK_S (PCL_S + 1) + { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink }, + +#define ILINK1 (BLINK + 1) + { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 }, +#define ILINK2 (ILINK1 + 1) + { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 }, + + /* Long immediate. */ +#define LIMM (ILINK2 + 1) +#define LIMM_S (ILINK2 + 1) + { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 }, +#define LIMMdup (LIMM + 1) + { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 }, + + /* Special operands. */ +#define ZA (LIMMdup + 1) +#define ZB (LIMMdup + 1) +#define ZA_S (LIMMdup + 1) +#define ZB_S (LIMMdup + 1) +#define ZC_S (LIMMdup + 1) + { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 }, + +#define RRANGE_EL (ZA + 1) + { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE, + insert_rrange, extract_rrange}, +#define FP_EL (RRANGE_EL + 1) + { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, + insert_fpel, extract_fpel }, +#define BLINK_EL (FP_EL + 1) + { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, + insert_blinkel, extract_blinkel }, +#define PCL_EL (BLINK_EL + 1) + { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK, + insert_pclel, extract_pclel }, + + /* Fake operand to handle the T flag. */ +#define BRAKET (PCL_EL + 1) +#define BRAKETdup (PCL_EL + 1) + { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 }, + + /* Fake operand to handle the T flag. */ +#define FKT_T (BRAKET + 1) + { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 }, + /* Fake operand to handle the T flag. */ +#define FKT_NT (FKT_T + 1) + { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 }, + + /* UIMM6_20 mask = 00000000000000000000111111000000. */ +#define UIMM6_20 (FKT_NT + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20}, + + /* SIMM12_20 mask = 00000000000000000000111111222222. */ +#define SIMM12_20 (UIMM6_20 + 1) + {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20}, + + /* SIMM3_5_S mask = 0000011100000000. */ +#define SIMM3_5_S (SIMM12_20 + 1) + {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK, + insert_simm3s, extract_simm3s}, + + /* UIMM7_A32_11_S mask = 0000000000011111. */ +#define UIMM7_A32_11_S (SIMM3_5_S + 1) + {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s, + extract_uimm7_a32_11_s}, + + /* UIMM7_9_S mask = 0000000001111111. */ +#define UIMM7_9_S (UIMM7_A32_11_S + 1) + {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s}, + + /* UIMM3_13_S mask = 0000000000000111. */ +#define UIMM3_13_S (UIMM7_9_S + 1) + {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s}, + + /* SIMM11_A32_7_S mask = 0000000111111111. */ +#define SIMM11_A32_7_S (UIMM3_13_S + 1) + {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s}, + + /* UIMM6_13_S mask = 0000000002220111. */ +#define UIMM6_13_S (SIMM11_A32_7_S + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s}, + /* UIMM5_11_S mask = 0000000000011111. */ +#define UIMM5_11_S (UIMM6_13_S + 1) + {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s, + extract_uimm5_11_s}, + + /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */ +#define SIMM9_A16_8 (UIMM5_11_S + 1) + {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8, + extract_simm9_a16_8}, + + /* UIMM6_8 mask = 00000000000000000000111111000000. */ +#define UIMM6_8 (SIMM9_A16_8 + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8}, + + /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */ +#define SIMM21_A16_5 (UIMM6_8 + 1) + {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED + | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE, + insert_simm21_a16_5, extract_simm21_a16_5}, + + /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */ +#define SIMM25_A16_5 (SIMM21_A16_5 + 1) + {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED + | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, + insert_simm25_a16_5, extract_simm25_a16_5}, + + /* SIMM10_A16_7_S mask = 0000000111111111. */ +#define SIMM10_A16_7_S (SIMM25_A16_5 + 1) + {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s, + extract_simm10_a16_7_s}, + +#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1) + {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s}, + + /* SIMM7_A16_10_S mask = 0000000000111111. */ +#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1) + {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s, + extract_simm7_a16_10_s}, + + /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */ +#define SIMM21_A32_5 (SIMM7_A16_10_S + 1) + {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5, + extract_simm21_a32_5}, + + /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */ +#define SIMM25_A32_5 (SIMM21_A32_5 + 1) + {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5, + extract_simm25_a32_5}, + + /* SIMM13_A32_5_S mask = 0000011111111111. */ +#define SIMM13_A32_5_S (SIMM25_A32_5 + 1) + {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s, + extract_simm13_a32_5_s}, + + /* SIMM8_A16_9_S mask = 0000000001111111. */ +#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1) + {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s, + extract_simm8_a16_9_s}, + + /* UIMM3_23 mask = 00000000000000000000000111000000. */ +#define UIMM3_23 (SIMM8_A16_9_S + 1) + {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23}, + + /* UIMM10_6_S mask = 0000001111111111. */ +#define UIMM10_6_S (UIMM3_23 + 1) + {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s}, + + /* UIMM6_11_S mask = 0000002200011110. */ +#define UIMM6_11_S (UIMM10_6_S + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s}, + + /* SIMM9_8 mask = 00000000111111112000000000000000. */ +#define SIMM9_8 (UIMM6_11_S + 1) + {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE, + insert_simm9_8, extract_simm9_8}, + + /* UIMM10_A32_8_S mask = 0000000011111111. */ +#define UIMM10_A32_8_S (SIMM9_8 + 1) + {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s, + extract_uimm10_a32_8_s}, + + /* SIMM9_7_S mask = 0000000111111111. */ +#define SIMM9_7_S (UIMM10_A32_8_S + 1) + {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s, + extract_simm9_7_s}, + + /* UIMM6_A16_11_S mask = 0000000000011111. */ +#define UIMM6_A16_11_S (SIMM9_7_S + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s, + extract_uimm6_a16_11_s}, + + /* UIMM5_A32_11_S mask = 0000020000011000. */ +#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1) + {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s, + extract_uimm5_a32_11_s}, + + /* SIMM11_A32_13_S mask = 0000022222200111. */ +#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1) + {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32 + | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s}, + + /* UIMM7_13_S mask = 0000000022220111. */ +#define UIMM7_13_S (SIMM11_A32_13_S + 1) + {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s}, + + /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */ +#define UIMM6_A16_21 (UIMM7_13_S + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21}, + + /* UIMM7_11_S mask = 0000022200011110. */ +#define UIMM7_11_S (UIMM6_A16_21 + 1) + {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s}, + + /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */ +#define UIMM7_A16_20 (UIMM7_11_S + 1) + {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20, + extract_uimm7_a16_20}, + + /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */ +#define SIMM13_A16_20 (UIMM7_A16_20 + 1) + {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16 + | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20, + extract_simm13_a16_20}, + + /* UIMM8_8_S mask = 0000000011111111. */ +#define UIMM8_8_S (SIMM13_A16_20 + 1) + {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s}, + + /* W6 mask = 00000000000000000000111111000000. */ +#define W6 (UIMM8_8_S + 1) + {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6}, + + /* UIMM6_5_S mask = 0000011111100000. */ +#define UIMM6_5_S (W6 + 1) + {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, +}; -const struct arc_opcode * -arc_opcode_lookup_asm (const char *insn) -{ - return opcode_map[ARC_HASH_OPCODE (insn)]; -} +const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); -/* Return the first insn in the chain for disassembling INSN. */ +const unsigned arc_Toperand = FKT_T; +const unsigned arc_NToperand = FKT_NT; -const struct arc_opcode * -arc_opcode_lookup_dis (unsigned int insn) -{ - return icode_map[ARC_HASH_ICODE (insn)]; -} +/* The opcode table. -/* Called by the assembler before parsing an instruction. */ + The format of the opcode table is: -void -arc_opcode_init_insert (void) + NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */ +const struct arc_opcode arc_opcodes[] = { - int i; - - for(i = 0; i < OPERANDS; i++) - ls_operand[i] = OP_NONE; - - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - addrwb_p = 0; - shimm_p = 0; - limm_p = 0; - jumpflags_p = 0; - nullify_p = 0; - nullify = 0; /* The default is important. */ -} +#include "arc-tbl.h" +}; -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ +const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes); -int -arc_opcode_limm_p (long *limmp) +/* List with special cases instructions and the applicable flags. */ +const struct arc_flag_special arc_flag_special_cases[] = { - if (limmp) - *limmp = limm; - return limm_p; -} + { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE, + F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW, + F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } }, + { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } } +}; -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ +const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases); -const struct arc_operand_value * -arc_opcode_lookup_suffix (const struct arc_operand *type, int value) -{ - const struct arc_operand_value *v,*end; - struct arc_ext_operand_value *ext_oper = arc_ext_operands; +/* Relocations. */ +#undef DEF +#define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2) \ + { #NAME, EXC1, EXC2, RELOC1, RELOC2} - while (ext_oper) - { - if (type == &arc_operands[ext_oper->operand.type] - && value == ext_oper->operand.value) - return (&ext_oper->operand); - ext_oper = ext_oper->next; - } +const struct arc_reloc_equiv_tab arc_reloc_equiv[] = +{ + DEF (sda, "ld", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2), + DEF (sda, "st", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2), + DEF (sda, "ldw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1), + DEF (sda, "ldh", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1), + DEF (sda, "stw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1), + DEF (sda, "sth", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1), + + /* Short instructions. */ + DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD), + DEF (sda, 0, F_NULL, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1), + DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2), + DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2), + + DEF (sda, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME), + DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST), + + DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25H_PCREL, + BFD_RELOC_ARC_S25H_PCREL_PLT), + DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21H_PCREL, + BFD_RELOC_ARC_S21H_PCREL_PLT), + DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25W_PCREL, + BFD_RELOC_ARC_S25W_PCREL_PLT), + DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21W_PCREL, + BFD_RELOC_ARC_S21W_PCREL_PLT), + + DEF (plt, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32), +}; - /* ??? This is a little slow and can be speeded up. */ - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} +const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv); -int -arc_insn_is_j (arc_insn insn) +const struct arc_pseudo_insn arc_pseudo_insns[] = { - return (insn & (I(-1))) == I(0x7); -} + { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 }, + { BRAKETdup, 1, 0, 4} } }, + { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 }, + { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 }, + { BRAKETdup, 1, 0, 4} } }, + + { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + + { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 }, + { SIMM9_A16_8, 0, 0, 2 } } }, + { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 }, + { SIMM9_A16_8, 0, 0, 2 } } }, +}; -int -arc_insn_not_jl (arc_insn insn) -{ - return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1))) - != (I(0x7) | R(-1,9,1))); -} +const unsigned arc_num_pseudo_insn = + sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns); -int -arc_operand_type (int opertype) +const struct arc_aux_reg arc_aux_regs[] = { - switch (opertype) - { - case 0: - return COND; - break; - case 1: - return REG; - break; - case 2: - return AUXREG; - break; - } - return -1; -} +#undef DEF +#define DEF(ADDR, NAME) \ + { ADDR, #NAME, sizeof (#NAME)-1 }, -struct arc_operand_value * -get_ext_suffix (char *s) -{ - struct arc_ext_operand_value *suffix = arc_ext_operands; +#include "arc-regs.h" - while (suffix) - { - if ((COND == suffix->operand.type) - && !strcmp(s,suffix->operand.name)) - return(&suffix->operand); - suffix = suffix->next; - } - return NULL; -} +#undef DEF +}; -int -arc_get_noshortcut_flag (void) -{ - return ARC_REGISTER_NOSHORT_CUT; -} +const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs); diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h new file mode 100644 index 0000000..b2060c8 --- /dev/null +++ b/opcodes/arc-regs.h @@ -0,0 +1,403 @@ +/* ARC Auxiliary register definitions + Copyright (C) 2015 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +DEF (0x0, STATUS) +DEF (0x1, SEMAPHORE) +DEF (0x2, LP_START) +DEF (0x3, LP_END) +DEF (0x4, IDENTITY) +DEF (0x5, DEBUG) +DEF (0x6, PC) +DEF (0x7, ADCR) +DEF (0x8, APCR) +DEF (0x9, ACR) +DEF (0xA, STATUS32) +DEF (0xB, STATUS32_L1) +DEF (0xC, STATUS32_L2) +DEF (0xF, BPU_FLUSH) +DEF (0x10, IVIC) +DEF (0x10, IC_IVIC) +DEF (0x11, CHE_MODE) +DEF (0x11, IC_CTRL) +DEF (0x12, MULHI) +DEF (0x13, LOCKLINE) +DEF (0x13, IC_LIL) +DEF (0x14, DMC_CODE_RAM) +DEF (0x15, TAG_ADDR_MASK) +DEF (0x16, TAG_DATA_MASK) +DEF (0x17, LINE_LENGTH_MASK) +DEF (0x18, AUX_LDST_RAM) +DEF (0x18, AUX_DCCM) +DEF (0x19, UNLOCKLINE) +DEF (0x19, IC_IVIL) +DEF (0x1A, IC_RAM_ADDRESS) +DEF (0x1A, IC_RAM_ADDRESS) +DEF (0x1B, IC_TAG) +DEF (0x1B, IC_TAG) +DEF (0x1C, IC_WP) +DEF (0x1C, IC_WP) +DEF (0x1D, IC_DATA) +DEF (0x1D, IC_DATA) +DEF (0x20, SRAM_SEQ) +DEF (0x21, COUNT0) +DEF (0x22, CONTROL0) +DEF (0x22, CONTROL0) +DEF (0x23, LIMIT0) +DEF (0x24, PCPORT) +DEF (0x25, INT_VECTOR_BASE) +DEF (0x26, AUX_VBFDW_MODE) +DEF (0x26, JLI_BASE) +DEF (0x27, AUX_VBFDW_BM0) +DEF (0x28, AUX_VBFDW_BM1) +DEF (0x29, AUX_VBFDW_ACCU) +DEF (0x2A, AUX_VBFDW_OFST) +DEF (0x2B, AUX_VBFDW_INTSTAT) +DEF (0x2C, AX2 (A4)) +DEF (0x2C, AUX_XMAC0_24) +DEF (0x2D, AY2 (A4)) +DEF (0x2D, AUX_XMAC1_24) +DEF (0x2E, MX2 (A4)) +DEF (0x2E, AUX_XMAC2_24) +DEF (0x2F, MY2 (A4)) +DEF (0x2F, AUX_FBF_STORE_16) +DEF (0x30, AX0) +DEF (0x31, AX1) +DEF (0x32, AY0 (A4)) +DEF (0x32, AUX_CRC_POLY) +DEF (0x33, AY1 (A4)) +DEF (0x33, AUX_CRC_MODE) +DEF (0x34, MX0) +DEF (0x35, MX1) +DEF (0x36, MY0) +DEF (0x37, MY1) +DEF (0x38, XYCONFIG) +DEF (0x39, SCRATCH_A) +DEF (0x3A, BURSTSYS) +DEF (0x3A, TSCH) +DEF (0x3B, BURSTXYM) +DEF (0x3C, BURSTSZ) +DEF (0x3D, BURSTVAL) +DEF (0x40, XTP_NEWVAL) +DEF (0x41, AUX_MACMODE) +DEF (0x42, LSP_NEWVAL) +DEF (0x43, AUX_IRQ_LV12) +DEF (0x44, AUX_XMAC0) +DEF (0x45, AUX_XMAC1) +DEF (0x46, AUX_XMAC2) +DEF (0x47, DC_IVDC) +DEF (0x48, DC_CTRL) +DEF (0x49, DC_LDL) +DEF (0x4A, DC_IVDL) +DEF (0x4B, DC_FLSH) +DEF (0x4C, DC_FLDL) +DEF (0x50, HEXDATA) +DEF (0x51, HEXCTRL) +DEF (0x52, LED) +DEF (0x53, LCDINSTR (A4)) +DEF (0x54, LCDDATA (A4)) +DEF (0x55, LCDSTAT (A4)) +DEF (0x56, DILSTAT) +DEF (0x57, SWSTAT) +DEF (0x58, DC_RAM_ADDR) +DEF (0x58, DC_RAM_ADDR) +DEF (0x59, DC_TAG) +DEF (0x59, DC_TAG) +DEF (0x5A, DC_WP) +DEF (0x5B, DC_DATA) +DEF (0x61, DCCM_BASE_BUILD) +DEF (0x62, CRC_BUILD) +DEF (0x63, BTA_LINK_BUILD) +DEF (0x64, VBFDW_BUILD) +DEF (0x65, EA_BUILD) +DEF (0x66, DATASPACE) +DEF (0x67, MEMSUBSYS) +DEF (0x68, VECBASE_AC_BUILD) +DEF (0x69, P_BASE_ADDR) +DEF (0x6A, DATA_UNCACHED_BUILD) +DEF (0x6B, FP_BUILD) +DEF (0x6C, DPFP_BUILD) +DEF (0x6D, MPU_BUILD) +DEF (0x6E, RF_BUILD) +DEF (0x6F, MMU_BUILD) +DEF (0x70, AA2_BUILD) +DEF (0x71, VECBASE_BUILD) +DEF (0x72, D_CACHE_BUILD) +DEF (0x73, MADI_BUILD) +DEF (0x74, DCCM_BUILD) +DEF (0x75, TIMER_BUILD) +DEF (0x76, AP_BUILD) +DEF (0x77, I_CACHE_BUILD) +DEF (0x78, ICCM_BUILD) +DEF (0x79, DSPRAM_BUILD) +DEF (0x7A, MAC_BUILD) +DEF (0x7B, MULTIPLY_BUILD) +DEF (0x7C, SWAP_BUILD) +DEF (0x7D, NORM_BUILD) +DEF (0x7E, MINMAX_BUILD) +DEF (0x7F, BARREL_BUILD) +DEF (0x80, AX0) +DEF (0x81, AX1) +DEF (0x82, AX2) +DEF (0x83, AX3) +DEF (0x84, AY0) +DEF (0x85, AY1) +DEF (0x86, AY2) +DEF (0x87, AY3) +DEF (0x88, MX00) +DEF (0x89, MX01) +DEF (0x8A, MX10) +DEF (0x8B, MX11) +DEF (0x8C, MX20) +DEF (0x8D, MX21) +DEF (0x8E, MX30) +DEF (0x8F, MX31) +DEF (0x90, MY00) +DEF (0x91, MY01) +DEF (0x92, MY10) +DEF (0x93, MY11) +DEF (0x94, MY20) +DEF (0x95, MY21) +DEF (0x96, MY30) +DEF (0x97, MY31) +DEF (0x98, XYCONFIG) +DEF (0x99, BURSTSYS) +DEF (0x9A, BURSTXYM) +DEF (0x9B, BURSTSZ) +DEF (0x9C, BURSTVAL) +DEF (0x9D, XYLSBASEX) +DEF (0x9E, XYLSBASEY) +DEF (0x9F, AUX_XMACLW_H) +DEF (0xA0, AUX_XMACLW_L) +DEF (0xA1, SE_CTRL) +DEF (0xA2, SE_STAT) +DEF (0xA3, SE_ERR) +DEF (0xA4, SE_EADR) +DEF (0xA5, SE_SPC) +DEF (0xA6, SDM_BASE) +DEF (0xA7, SCM_BASE) +DEF (0xA8, SE_DBG_CTRL) +DEF (0xA9, SE_DBG_DATA0) +DEF (0xAA, SE_DBG_DATA1) +DEF (0xAB, SE_DBG_DATA2) +DEF (0xAC, SE_DBG_DATA3) +DEF (0xAD, SE_WATCH) +DEF (0xC0, BPU_BUILD) +DEF (0xC1, ARC600_BUILD_CONFIG) +DEF (0xC2, ISA_CONFIG) +DEF (0xF4, HWP_BUILD) +DEF (0xF5, PCT_BUILD) +DEF (0xF6, CC_BUILD) +DEF (0xF7, PM_BCR) +DEF (0xF8, SCQ_SWITCH_BUILD) +DEF (0xF9, VRAPTOR_BUILD) +DEF (0xFA, DMA_CONFIG) +DEF (0xFB, SIMD_CONFIG) +DEF (0xFC, VLC_BUILD) +DEF (0xFD, SIMD_DMA_BUILD) +DEF (0xFE, IFETCH_QUEUE_BUILD) +DEF (0xFF, SMART_BUILD) +DEF (0x100, COUNT1) +DEF (0x101, CONTROL1) +DEF (0x101, CONTROL1) +DEF (0x102, LIMIT1) +DEF (0x103, TIMER_XX) +DEF (0x120, ARCANGEL_PERIPH_XX) +DEF (0x140, PERIPH_XX) +DEF (0x200, AUX_IRQ_LEV) +DEF (0x201, AUX_IRQ_HINT) +DEF (0x202, AUX_INTER_CORE_INTERRUPT) +DEF (0x210, AES_AUX_0) +DEF (0x211, AES_AUX_1) +DEF (0x212, AES_AUX_2) +DEF (0x213, AES_CRYPT_MODE) +DEF (0x214, AES_AUXS) +DEF (0x215, AES_AUXI) +DEF (0x216, AES_AUX_3) +DEF (0x217, AES_AUX_4) +DEF (0x218, ARITH_CTL_AUX) +DEF (0x219, DES_AUX) +DEF (0x220, AP_AMV0) +DEF (0x221, AP_AMM0) +DEF (0x222, AP_AC0) +DEF (0x223, AP_AMV1) +DEF (0x224, AP_AMM1) +DEF (0x225, AP_AC1) +DEF (0x226, AP_AMV2) +DEF (0x227, AP_AMM2) +DEF (0x228, AP_AC2) +DEF (0x229, AP_AMV3) +DEF (0x22A, AP_AMM3) +DEF (0x22B, AP_AC3) +DEF (0x22C, AP_AMV4) +DEF (0x22D, AP_AMM4) +DEF (0x22E, AP_AC4) +DEF (0x22F, AP_AMV5) +DEF (0x230, AP_AMM5) +DEF (0x231, AP_AC5) +DEF (0x232, AP_AMV6) +DEF (0x233, AP_AMM6) +DEF (0x234, AP_AC6) +DEF (0x235, AP_AMV7) +DEF (0x236, AP_AMM7) +DEF (0x237, AP_AC7) +DEF (0x240, CC_*) +DEF (0x250, PCT_COUNT*) +DEF (0x260, PCT_SNAP*) +DEF (0x270, PCT_CONFIG*) +DEF (0x278, PCT_CONTROL) +DEF (0x279, PCT_BANK) +DEF (0x300, FP_STATUS) +DEF (0x300, RTT (A5 - A4)) +DEF (0x301, AUX_DPFP1L) +DEF (0x301, RTT (A5 - A4)) +DEF (0x302, AUX_DPFP1H) +DEF (0x302, RTT (A5 - A4)) +DEF (0x303, AUX_DPFP2L) +DEF (0x303, RTT (A5 - A4)) +DEF (0x304, AUX_DPFP2H) +DEF (0x304, RTT (A5 - A4)) +DEF (0x305, DPFP_STATUS) +DEF (0x305, RTT (A5 - A4)) +DEF (0x306, RTT) +DEF (0x400, ERET) +DEF (0x401, ERBTA) +DEF (0x402, ERSTATUS) +DEF (0x403, ECR) +DEF (0x404, EFA) +DEF (0x405, TLBPD0) +DEF (0x406, TLBPD1) +DEF (0x407, TLBIndex) +DEF (0x408, TLBCommand) +DEF (0x409, PID) +DEF (0x409, MPUEN) +DEF (0x40A, ICAUSE1) +DEF (0x40B, ICAUSE2) +DEF (0x40C, AUX_IENABLE) +DEF (0x40D, AUX_ITRIGGER) +DEF (0x410, XPU) +DEF (0x412, BTA) +DEF (0x413, BTA_L1) +DEF (0x414, BTA_L2) +DEF (0x415, AUX_IRQ_PULSE_CANCEL) +DEF (0x416, AUX_IRQ_PENDING) +DEF (0x418, SCRATCH_DATA0) +DEF (0x420, MPUIC) +DEF (0x421, MPUFA) +DEF (0x422, MPURDB0) +DEF (0x423, MPURDP0) +DEF (0x424, MPURDB1) +DEF (0x425, MPURDP1) +DEF (0x426, MPURDB2) +DEF (0x427, MPURDP2) +DEF (0x428, MPURDB3) +DEF (0x429, MPURDP3) +DEF (0x42A, MPURDB4) +DEF (0x42B, MPURDP4) +DEF (0x42C, MPURDB5) +DEF (0x42D, MPURDP5) +DEF (0x42E, MPURDB6) +DEF (0x42F, MPURDP6) +DEF (0x430, MPURDB7) +DEF (0x431, MPURDP7) +DEF (0x432, MPURDB8) +DEF (0x433, MPURDP8) +DEF (0x434, MPURDB9) +DEF (0x435, MPURDP9) +DEF (0x436, MPURDB10) +DEF (0x437, MPURDP10) +DEF (0x438, MPURDB11) +DEF (0x439, MPURDP11) +DEF (0x43A, MPURDB12) +DEF (0x43B, MPURDP12) +DEF (0x43C, MPURDB13) +DEF (0x43D, MPURDP13) +DEF (0x43E, MPURDB14) +DEF (0x43F, MPURDP14) +DEF (0x440, MPURDB15) +DEF (0x441, MPURDP15) +DEF (0x44F, EIA_FLAGS) +DEF (0x450, PM_STATUS) +DEF (0x451, WAKE) +DEF (0x452, DVFS_PERFORMANCE) +DEF (0x453, PWR_CTRL) +DEF (0x500, AUX_VLC_BUF_IDX) +DEF (0x501, AUX_VLC_READ_BUF) +DEF (0x502, AUX_VLC_VALID_BITS) +DEF (0x503, AUX_VLC_BUF_IN) +DEF (0x504, AUX_VLC_BUF_FREE) +DEF (0x505, AUX_VLC_IBUF_STATUS) +DEF (0x506, AUX_VLC_SETUP) +DEF (0x507, AUX_VLC_BITS) +DEF (0x508, AUX_VLC_TABLE) +DEF (0x509, AUX_VLC_GET_SYMBOL) +DEF (0x50A, AUX_VLC_READ_SYMBOL) +DEF (0x510, AUX_UCAVLC_SETUP) +DEF (0x511, AUX_UCAVLC_STATE) +DEF (0x512, AUX_CAVLC_ZERO_LEFT) +DEF (0x514, AUX_UVLC_I_STATE) +DEF (0x51C, AUX_VLC_DMA_PTR) +DEF (0x51D, AUX_VLC_DMA_END) +DEF (0x51E, AUX_VLC_DMA_ESC) +DEF (0x51F, AUX_VLC_DMA_CTRL) +DEF (0x520, AUX_VLC_GET_0BIT) +DEF (0x521, AUX_VLC_GET_1BIT) +DEF (0x522, AUX_VLC_GET_2BIT) +DEF (0x523, AUX_VLC_GET_3BIT) +DEF (0x524, AUX_VLC_GET_4BIT) +DEF (0x525, AUX_VLC_GET_5BIT) +DEF (0x526, AUX_VLC_GET_6BIT) +DEF (0x527, AUX_VLC_GET_7BIT) +DEF (0x528, AUX_VLC_GET_8BIT) +DEF (0x529, AUX_VLC_GET_9BIT) +DEF (0x52A, AUX_VLC_GET_10BIT) +DEF (0x52B, AUX_VLC_GET_11BIT) +DEF (0x52C, AUX_VLC_GET_12BIT) +DEF (0x52D, AUX_VLC_GET_13BIT) +DEF (0x52E, AUX_VLC_GET_14BIT) +DEF (0x52F, AUX_VLC_GET_15BIT) +DEF (0x530, AUX_VLC_GET_16BIT) +DEF (0x531, AUX_VLC_GET_17BIT) +DEF (0x532, AUX_VLC_GET_18BIT) +DEF (0x533, AUX_VLC_GET_19BIT) +DEF (0x534, AUX_VLC_GET_20BIT) +DEF (0x535, AUX_VLC_GET_21BIT) +DEF (0x536, AUX_VLC_GET_22BIT) +DEF (0x537, AUX_VLC_GET_23BIT) +DEF (0x538, AUX_VLC_GET_24BIT) +DEF (0x539, AUX_VLC_GET_25BIT) +DEF (0x53A, AUX_VLC_GET_26BIT) +DEF (0x53B, AUX_VLC_GET_27BIT) +DEF (0x53C, AUX_VLC_GET_28BIT) +DEF (0x53D, AUX_VLC_GET_29BIT) +DEF (0x53E, AUX_VLC_GET_30BIT) +DEF (0x53F, AUX_VLC_GET_31BIT) +DEF (0x540, AUX_CABAC_CTRL) +DEF (0x541, AUX_CABAC_CTX_STATE) +DEF (0x542, AUX_CABAC_COD_PARAM) +DEF (0x543, AUX_CABAC_MISC0) +DEF (0x544, AUX_CABAC_MISC1) +DEF (0x545, AUX_CABAC_MISC2) +DEF (0x600, ARC600_BUILD_CONFIG) +DEF (0x700, SMART_CONTROL) +DEF (0x701, SMART_DATA_0) +DEF (0x701, SMART_DATA_1) +DEF (0x701, SMART_DATA_2) +DEF (0x701, SMART_DATA_3) diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h new file mode 100644 index 0000000..78e5b51 --- /dev/null +++ b/opcodes/arc-tbl.h @@ -0,0 +1,18198 @@ +/* ARC instruction defintions. + Copyright (C) 1994-2015 Free Software Foundation, Inc. + + Contributed by Claudiu Zissulescu (claziss@synopsys.com) + + This file is part of libopcodes. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* abs<.f> b,c 00100bbb00101111FBBBCCCCCC001001. */ +{ "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, + +/* abs<.f> 0,c 0010011000101111F111CCCCCC001001. */ +{ "abs", 0x262F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* abs<.f> b,u6 00100bbb01101111FBBBuuuuuu001001. */ +{ "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* abs<.f> 0,u6 0010011001101111F111uuuuuu001001. */ +{ "abs", 0x266F7009, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* abs<.f> b,limm 00100bbb00101111FBBB111110001001. */ +{ "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* abs<.f> 0,limm 0010011000101111F111111110001001. */ +{ "abs", 0x262F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* abss<.f> b,c 00101bbb00101111FBBBCCCCCC000101. */ +{ "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { C_F }}, + +/* abss<.f> 0,c 0010111000101111F111CCCCCC000101. */ +{ "abss", 0x2E2F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* abss<.f> b,u6 00101bbb01101111FBBBuuuuuu000101. */ +{ "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* abss<.f> 0,u6 0010111001101111F111uuuuuu000101. */ +{ "abss", 0x2E6F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* abss<.f> b,limm 00101bbb00101111FBBB111110000101. */ +{ "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* abss<.f> 0,limm 0010111000101111F111111110000101. */ +{ "abss", 0x2E2F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* abssh<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ +{ "abssh", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }}, + +/* abssh<.f> 0,c 0010111000101111F111CCCCCC000100. */ +{ "abssh", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }}, + +/* abssh<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ +{ "abssh", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* abssh<.f> 0,u6 0010111001101111F111uuuuuu000100. */ +{ "abssh", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* abssh<.f> b,limm 00101bbb00101111FBBB111110000100. */ +{ "abssh", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* abssh<.f> 0,limm 0010111000101111F111111110000100. */ +{ "abssh", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* abssw<.f> b,c 00101bbb00101111FBBBCCCCCC000100. */ +{ "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* abssw<.f> 0,c 0010111000101111F111CCCCCC000100. */ +{ "abssw", 0x2E2F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* abssw<.f> b,u6 00101bbb01101111FBBBuuuuuu000100. */ +{ "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* abssw<.f> 0,u6 0010111001101111F111uuuuuu000100. */ +{ "abssw", 0x2E6F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* abssw<.f> b,limm 00101bbb00101111FBBB111110000100. */ +{ "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* abssw<.f> 0,limm 0010111000101111F111111110000100. */ +{ "abssw", 0x2E2F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* abs_s b,c 01111bbbccc10001. */ +{ "abs_s", 0x00007811, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* acm<.f> a,b,c 00110bbb00101000FBBBCCCCCCAAAAAA. */ +{ "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* acm<.f><.cc> b,b,c 00110bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "acm", 0x30E80000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* acm<.f> a,b,u6 00110bbb01101000FBBBuuuuuuAAAAAA. */ +{ "acm", 0x30680000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* acm<.f><.cc> b,b,u6 00110bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "acm", 0x30E80020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* acm<.f> b,b,s12 00110bbb10101000FBBBssssssSSSSSS. */ +{ "acm", 0x30A80000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* acm<.f> a,limm,c 0011011000101000F111CCCCCCAAAAAA. */ +{ "acm", 0x36287000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* acm<.f> a,b,limm 00110bbb00101000FBBB111110AAAAAA. */ +{ "acm", 0x30280F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* acm<.f><.cc> b,b,limm 00110bbb11101000FBBB1111100QQQQQ. */ +{ "acm", 0x30E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* adc<.f> a,b,c 00100bbb00000001FBBBCCCCCCAAAAAA. */ +{ "adc", 0x20010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* adc<.f> 0,b,c 00100bbb00000001FBBBCCCCCC111110. */ +{ "adc", 0x2001003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* adc<.f><.cc> b,b,c 00100bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "adc", 0x20C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* adc<.f> a,b,u6 00100bbb01000001FBBBuuuuuuAAAAAA. */ +{ "adc", 0x20410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* adc<.f> 0,b,u6 00100bbb01000001FBBBuuuuuu111110. */ +{ "adc", 0x2041003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* adc<.f><.cc> b,b,u6 00100bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "adc", 0x20C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* adc<.f> b,b,s12 00100bbb10000001FBBBssssssSSSSSS. */ +{ "adc", 0x20810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* adc<.f> a,limm,c 0010011000000001F111CCCCCCAAAAAA. */ +{ "adc", 0x26017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* adc<.f> a,b,limm 00100bbb00000001FBBB111110AAAAAA. */ +{ "adc", 0x20010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* adc<.f> 0,limm,c 0010011000000001F111CCCCCC111110. */ +{ "adc", 0x2601703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* adc<.f> 0,b,limm 00100bbb00000001FBBB111110111110. */ +{ "adc", 0x20010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* adc<.f><.cc> b,b,limm 00100bbb11000001FBBB1111100QQQQQ. */ +{ "adc", 0x20C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* adc<.f><.cc> 0,limm,c 0010011011000001F111CCCCCC0QQQQQ. */ +{ "adc", 0x26C17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* adc<.f> a,limm,u6 0010011001000001F111uuuuuuAAAAAA. */ +{ "adc", 0x26417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* adc<.f> 0,limm,u6 0010011001000001F111uuuuuu111110. */ +{ "adc", 0x2641703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* adc<.f><.cc> 0,limm,u6 0010011011000001F111uuuuuu1QQQQQ. */ +{ "adc", 0x26C17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* adc<.f> 0,limm,s12 0010011010000001F111ssssssSSSSSS. */ +{ "adc", 0x26817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* adc<.f> a,limm,limm 0010011000000001F111111110AAAAAA. */ +{ "adc", 0x26017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* adc<.f> 0,limm,limm 0010011000000001F111111110111110. */ +{ "adc", 0x26017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* adc<.f><.cc> 0,limm,limm 0010011011000001F1111111100QQQQQ. */ +{ "adc", 0x26C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add<.f> a,b,c 00100bbb00000000FBBBCCCCCCAAAAAA. */ +{ "add", 0x20000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* add<.f> 0,b,c 00100bbb00000000FBBBCCCCCC111110. */ +{ "add", 0x2000003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* add<.f><.cc> b,b,c 00100bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "add", 0x20C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */ +{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* add<.f> 0,b,u6 00100bbb01000000FBBBuuuuuu111110. */ +{ "add", 0x2040003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* add<.f> b,b,s12 00100bbb10000000FBBBssssssSSSSSS. */ +{ "add", 0x20800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* add<.f> a,limm,c 0010011000000000F111CCCCCCAAAAAA. */ +{ "add", 0x26007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */ +{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* add<.f> 0,limm,c 0010011000000000F111CCCCCC111110. */ +{ "add", 0x2600703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* add<.f> 0,b,limm 00100bbb00000000FBBB111110111110. */ +{ "add", 0x20000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */ +{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* add<.f><.cc> 0,limm,c 0010011011000000F111CCCCCC0QQQQQ. */ +{ "add", 0x26C07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* add<.f> a,limm,u6 0010011001000000F111uuuuuuAAAAAA. */ +{ "add", 0x26407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* add<.f> 0,limm,u6 0010011001000000F111uuuuuu111110. */ +{ "add", 0x2640703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* add<.f><.cc> 0,limm,u6 0010011011000000F111uuuuuu1QQQQQ. */ +{ "add", 0x26C07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* add<.f> 0,limm,s12 0010011010000000F111ssssssSSSSSS. */ +{ "add", 0x26807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* add<.f> a,limm,limm 0010011000000000F111111110AAAAAA. */ +{ "add", 0x26007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* add<.f> 0,limm,limm 0010011000000000F111111110111110. */ +{ "add", 0x26007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* add<.f><.cc> 0,limm,limm 0010011011000000F1111111100QQQQQ. */ +{ "add", 0x26C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add1<.f> a,b,c 00100bbb00010100FBBBCCCCCCAAAAAA. */ +{ "add1", 0x20140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* add1<.f> 0,b,c 00100bbb00010100FBBBCCCCCC111110. */ +{ "add1", 0x2014003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* add1<.f><.cc> b,b,c 00100bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "add1", 0x20D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* add1<.f> a,b,u6 00100bbb01010100FBBBuuuuuuAAAAAA. */ +{ "add1", 0x20540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* add1<.f> 0,b,u6 00100bbb01010100FBBBuuuuuu111110. */ +{ "add1", 0x2054003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* add1<.f><.cc> b,b,u6 00100bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "add1", 0x20D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* add1<.f> b,b,s12 00100bbb10010100FBBBssssssSSSSSS. */ +{ "add1", 0x20940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* add1<.f> a,limm,c 0010011000010100F111CCCCCCAAAAAA. */ +{ "add1", 0x26147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* add1<.f> a,b,limm 00100bbb00010100FBBB111110AAAAAA. */ +{ "add1", 0x20140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* add1<.f> 0,limm,c 0010011000010100F111CCCCCC111110. */ +{ "add1", 0x2614703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* add1<.f> 0,b,limm 00100bbb00010100FBBB111110111110. */ +{ "add1", 0x20140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* add1<.f><.cc> b,b,limm 00100bbb11010100FBBB1111100QQQQQ. */ +{ "add1", 0x20D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* add1<.f><.cc> 0,limm,c 0010011011010100F111CCCCCC0QQQQQ. */ +{ "add1", 0x26D47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* add1<.f> a,limm,u6 0010011001010100F111uuuuuuAAAAAA. */ +{ "add1", 0x26547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* add1<.f> 0,limm,u6 0010011001010100F111uuuuuu111110. */ +{ "add1", 0x2654703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* add1<.f><.cc> 0,limm,u6 0010011011010100F111uuuuuu1QQQQQ. */ +{ "add1", 0x26D47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* add1<.f> 0,limm,s12 0010011010010100F111ssssssSSSSSS. */ +{ "add1", 0x26947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* add1<.f> a,limm,limm 0010011000010100F111111110AAAAAA. */ +{ "add1", 0x26147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* add1<.f> 0,limm,limm 0010011000010100F111111110111110. */ +{ "add1", 0x26147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* add1<.f><.cc> 0,limm,limm 0010011011010100F1111111100QQQQQ. */ +{ "add1", 0x26D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add1_s b,b,c 01111bbbccc10100. */ +{ "add1_s", 0x00007814, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* add2<.f> a,b,c 00100bbb00010101FBBBCCCCCCAAAAAA. */ +{ "add2", 0x20150000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* add2<.f> 0,b,c 00100bbb00010101FBBBCCCCCC111110. */ +{ "add2", 0x2015003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* add2<.f><.cc> b,b,c 00100bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "add2", 0x20D50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* add2<.f> a,b,u6 00100bbb01010101FBBBuuuuuuAAAAAA. */ +{ "add2", 0x20550000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* add2<.f> 0,b,u6 00100bbb01010101FBBBuuuuuu111110. */ +{ "add2", 0x2055003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* add2<.f><.cc> b,b,u6 00100bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "add2", 0x20D50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* add2<.f> b,b,s12 00100bbb10010101FBBBssssssSSSSSS. */ +{ "add2", 0x20950000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* add2<.f> a,limm,c 0010011000010101F111CCCCCCAAAAAA. */ +{ "add2", 0x26157000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* add2<.f> a,b,limm 00100bbb00010101FBBB111110AAAAAA. */ +{ "add2", 0x20150F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* add2<.f> 0,limm,c 0010011000010101F111CCCCCC111110. */ +{ "add2", 0x2615703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* add2<.f> 0,b,limm 00100bbb00010101FBBB111110111110. */ +{ "add2", 0x20150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* add2<.f><.cc> b,b,limm 00100bbb11010101FBBB1111100QQQQQ. */ +{ "add2", 0x20D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* add2<.f><.cc> 0,limm,c 0010011011010101F111CCCCCC0QQQQQ. */ +{ "add2", 0x26D57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* add2<.f> a,limm,u6 0010011001010101F111uuuuuuAAAAAA. */ +{ "add2", 0x26557000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* add2<.f> 0,limm,u6 0010011001010101F111uuuuuu111110. */ +{ "add2", 0x2655703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* add2<.f><.cc> 0,limm,u6 0010011011010101F111uuuuuu1QQQQQ. */ +{ "add2", 0x26D57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* add2<.f> 0,limm,s12 0010011010010101F111ssssssSSSSSS. */ +{ "add2", 0x26957000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* add2<.f> a,limm,limm 0010011000010101F111111110AAAAAA. */ +{ "add2", 0x26157F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* add2<.f> 0,limm,limm 0010011000010101F111111110111110. */ +{ "add2", 0x26157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* add2<.f><.cc> 0,limm,limm 0010011011010101F1111111100QQQQQ. */ +{ "add2", 0x26D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add2_s b,b,c 01111bbbccc10101. */ +{ "add2_s", 0x00007815, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* add3<.f> a,b,c 00100bbb00010110FBBBCCCCCCAAAAAA. */ +{ "add3", 0x20160000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* add3<.f> 0,b,c 00100bbb00010110FBBBCCCCCC111110. */ +{ "add3", 0x2016003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* add3<.f><.cc> b,b,c 00100bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "add3", 0x20D60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* add3<.f> a,b,u6 00100bbb01010110FBBBuuuuuuAAAAAA. */ +{ "add3", 0x20560000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* add3<.f> 0,b,u6 00100bbb01010110FBBBuuuuuu111110. */ +{ "add3", 0x2056003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* add3<.f><.cc> b,b,u6 00100bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "add3", 0x20D60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* add3<.f> b,b,s12 00100bbb10010110FBBBssssssSSSSSS. */ +{ "add3", 0x20960000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* add3<.f> a,limm,c 0010011000010110F111CCCCCCAAAAAA. */ +{ "add3", 0x26167000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* add3<.f> a,b,limm 00100bbb00010110FBBB111110AAAAAA. */ +{ "add3", 0x20160F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* add3<.f> 0,limm,c 0010011000010110F111CCCCCC111110. */ +{ "add3", 0x2616703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* add3<.f> 0,b,limm 00100bbb00010110FBBB111110111110. */ +{ "add3", 0x20160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* add3<.f><.cc> b,b,limm 00100bbb11010110FBBB1111100QQQQQ. */ +{ "add3", 0x20D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* add3<.f><.cc> 0,limm,c 0010011011010110F111CCCCCC0QQQQQ. */ +{ "add3", 0x26D67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* add3<.f> a,limm,u6 0010011001010110F111uuuuuuAAAAAA. */ +{ "add3", 0x26567000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* add3<.f> 0,limm,u6 0010011001010110F111uuuuuu111110. */ +{ "add3", 0x2656703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* add3<.f><.cc> 0,limm,u6 0010011011010110F111uuuuuu1QQQQQ. */ +{ "add3", 0x26D67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* add3<.f> 0,limm,s12 0010011010010110F111ssssssSSSSSS. */ +{ "add3", 0x26967000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* add3<.f> a,limm,limm 0010011000010110F111111110AAAAAA. */ +{ "add3", 0x26167F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* add3<.f> 0,limm,limm 0010011000010110F111111110111110. */ +{ "add3", 0x26167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* add3<.f><.cc> 0,limm,limm 0010011011010110F1111111100QQQQQ. */ +{ "add3", 0x26D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add3_s b,b,c 01111bbbccc10110. */ +{ "add3_s", 0x00007816, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* addqbs<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ +{ "addqbs", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* addqbs<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "addqbs", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* addqbs<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ +{ "addqbs", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* addqbs<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "addqbs", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* addqbs<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ +{ "addqbs", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* addqbs<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ +{ "addqbs", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* addqbs<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ +{ "addqbs", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* addqbs<.f><.cc> b,b,limm 00110bbb11100100FBBB1111100QQQQQ. */ +{ "addqbs", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* adds<.f> a,b,c 00101bbb00000110FBBBCCCCCCAAAAAA. */ +{ "adds", 0x28060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* adds<.f> 0,b,c 00101bbb00000110FBBBCCCCCC111110. */ +{ "adds", 0x2806003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* adds<.f><.cc> b,b,c 00101bbb11000110FBBBCCCCCC0QQQQQ. */ +{ "adds", 0x28C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* adds<.f> a,b,u6 00101bbb01000110FBBBuuuuuuAAAAAA. */ +{ "adds", 0x28460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* adds<.f> 0,b,u6 00101bbb01000110FBBBuuuuuu111110. */ +{ "adds", 0x2846003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* adds<.f><.cc> b,b,u6 00101bbb11000110FBBBuuuuuu1QQQQQ. */ +{ "adds", 0x28C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* adds<.f> b,b,s12 00101bbb10000110FBBBssssssSSSSSS. */ +{ "adds", 0x28860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* adds<.f> a,limm,c 0010111000000110F111CCCCCCAAAAAA. */ +{ "adds", 0x2E067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* adds<.f> a,b,limm 00101bbb00000110FBBB111110AAAAAA. */ +{ "adds", 0x28060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* adds<.f> 0,limm,c 0010111000000110F111CCCCCC111110. */ +{ "adds", 0x2E06703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* adds<.f> 0,b,limm 00101bbb00000110FBBB111110111110. */ +{ "adds", 0x28060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* adds<.f><.cc> b,b,limm 00101bbb11000110FBBB1111100QQQQQ. */ +{ "adds", 0x28C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* adds<.f><.cc> 0,limm,c 0010111011000110F111CCCCCC0QQQQQ. */ +{ "adds", 0x2EC67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* adds<.f> a,limm,u6 0010111001000110F111uuuuuuAAAAAA. */ +{ "adds", 0x2E467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* adds<.f> 0,limm,u6 0010111001000110F111uuuuuu111110. */ +{ "adds", 0x2E46703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* adds<.f><.cc> 0,limm,u6 0010111011000110F111uuuuuu1QQQQQ. */ +{ "adds", 0x2EC67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* adds<.f> 0,limm,s12 0010111010000110F111ssssssSSSSSS. */ +{ "adds", 0x2E867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* adds<.f> a,limm,limm 0010111000000110F111111110AAAAAA. */ +{ "adds", 0x2E067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* adds<.f> 0,limm,limm 0010111000000110F111111110111110. */ +{ "adds", 0x2E067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* adds<.f><.cc> 0,limm,limm 0010111011000110F1111111100QQQQQ. */ +{ "adds", 0x2EC67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* addsdw<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ +{ "addsdw", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* addsdw<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ +{ "addsdw", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* addsdw<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "addsdw", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* addsdw<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ +{ "addsdw", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* addsdw<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ +{ "addsdw", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* addsdw<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "addsdw", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* addsdw<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ +{ "addsdw", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* addsdw<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ +{ "addsdw", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* addsdw<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ +{ "addsdw", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* addsdw<.f> 0,limm,c 0010111000101000F111CCCCCC111110. */ +{ "addsdw", 0x2E28703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* addsdw<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ +{ "addsdw", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* addsdw<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ +{ "addsdw", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* addsdw<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ +{ "addsdw", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* addsdw<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ +{ "addsdw", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* addsdw<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ +{ "addsdw", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* addsdw<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ +{ "addsdw", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* addsdw<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ +{ "addsdw", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* addsdw<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ +{ "addsdw", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* addsdw<.f> 0,limm,limm 0010111000101000F111111110111110. */ +{ "addsdw", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* addsdw<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ +{ "addsdw", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* add_s a,b,c 01100bbbccc11aaa. */ +{ "add_s", 0x00006018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA_S, RB_S, RC_S }, { 0 }}, + +/* add_s b,b,h 01110bbbhhh00HHH. */ +{ "add_s", 0x00007000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RB_Sdup, R6H }, { 0 }}, + +/* add_s b,b,h 01110bbbhhh000HH. */ +{ "add_s", 0x00007000, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RH_S }, { 0 }}, + +/* add_s h,h,s3 01110ssshhh001HH. */ +{ "add_s", 0x00007004, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RH_S, RH_Sdup, SIMM3_5_S }, { 0 }}, + +/* add_s c,b,u3 01101bbbccc00uuu. */ +{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, + +/* add_s R0,b,u6 01001bbb0UUU1uuu. */ +{ "add_s", 0x00004808, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { R0_S, RB_S, UIMM6_13_S }, { 0 }}, + +/* add_s R1,b,u6 01001bbb1UUU1uuu. */ +{ "add_s", 0x00004888, 0x0000F888, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { R1_S, RB_S, UIMM6_13_S }, { 0 }}, + +/* add_s b,sp,u7 11000bbb100uuuuu. */ +{ "add_s", 0x0000C080, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, SP_S, UIMM7_A32_11_S }, { 0 }}, + +/* add_s b,b,u7 11100bbb0uuuuuuu. */ +{ "add_s", 0x0000E000, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM7_9_S }, { 0 }}, + +/* add_s SP,SP,u7 11000000101uuuuu. */ +{ "add_s", 0x0000C0A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }}, + +/* add_s R0,GP,s11 1100111sssssssss. */ +{ "add_s", 0x0000CE00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { R0_S, GP_S, SIMM11_A32_7_S }, { 0 }}, + +/* add_s b,b,limm 01110bbb11000111. */ +{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }}, + +/* add_s b,b,limm 01110bbb11000011. */ +{ "add_s", 0x000070C3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, LIMM_S }, { 0 }}, + +/* add_s 0,limm,s3 01110sss11000111. */ +{ "add_s", 0x000070C7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA_S, LIMM_S, SIMM3_5_S }, { 0 }}, + +/* aex b,c 00100bbb00100111RBBBCCCCCCRRRRRR. */ +{ "aex", 0x20270000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* aex<.cc> b,c 00100bbb11100111RBBBCCCCCC0QQQQQ. */ +{ "aex", 0x20E70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* aex b,u6 00100bbb01100111RBBBuuuuuuRRRRRR. */ +{ "aex", 0x20670000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* aex<.cc> b,u6 00100bbb11100111RBBBuuuuuu1QQQQQ. */ +{ "aex", 0x20E70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }}, + +/* aex b,s12 00100bbb10100111RBBBssssssSSSSSS. */ +{ "aex", 0x20A70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* aex limm,c 0010011000100111R111CCCCCCRRRRRR. */ +{ "aex", 0x26277000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* aex b,limm 00100bbb00100111RBBB111110RRRRRR. */ +{ "aex", 0x20270F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,c 0010011011100111R111CCCCCC0QQQQQ. */ +{ "aex", 0x26E77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* aex<.cc> b,limm 00100bbb11100111RBBB1111100QQQQQ. */ +{ "aex", 0x20E70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_CC }}, + +/* aex limm,u6 0010011001100111R111uuuuuuRRRRRR. */ +{ "aex", 0x26677000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,u6 0010011011100111R111uuuuuu1QQQQQ. */ +{ "aex", 0x26E77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }}, + +/* aex limm,s12 0010011010100111R111ssssssSSSSSS. */ +{ "aex", 0x26A77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* aex limm,limm 0010011000100111R111111110RRRRRR. */ +{ "aex", 0x26277F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }}, + +/* aex<.cc> limm,limm 0010011011100111R1111111100QQQQQ. */ +{ "aex", 0x26E77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_CC }}, + +/* and<.f> a,b,c 00100bbb00000100FBBBCCCCCCAAAAAA. */ +{ "and", 0x20040000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* and<.f> 0,b,c 00100bbb00000100FBBBCCCCCC111110. */ +{ "and", 0x2004003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* and<.f><.cc> b,b,c 00100bbb11000100FBBBCCCCCC0QQQQQ. */ +{ "and", 0x20C40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* and<.f> a,b,u6 00100bbb01000100FBBBuuuuuuAAAAAA. */ +{ "and", 0x20440000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* and<.f> 0,b,u6 00100bbb01000100FBBBuuuuuu111110. */ +{ "and", 0x2044003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* and<.f><.cc> b,b,u6 00100bbb11000100FBBBuuuuuu1QQQQQ. */ +{ "and", 0x20C40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* and<.f> b,b,s12 00100bbb10000100FBBBssssssSSSSSS. */ +{ "and", 0x20840000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* and<.f> a,limm,c 0010011000000100F111CCCCCCAAAAAA. */ +{ "and", 0x26047000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* and<.f> a,b,limm 00100bbb00000100FBBB111110AAAAAA. */ +{ "and", 0x20040F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* and<.f> 0,limm,c 0010011000000100F111CCCCCC111110. */ +{ "and", 0x2604703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* and<.f> 0,b,limm 00100bbb00000100FBBB111110111110. */ +{ "and", 0x20040FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* and<.f><.cc> b,b,limm 00100bbb11000100FBBB1111100QQQQQ. */ +{ "and", 0x20C40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* and<.f><.cc> 0,limm,c 0010011011000100F111CCCCCC0QQQQQ. */ +{ "and", 0x26C47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* and<.f> a,limm,u6 0010011001000100F111uuuuuuAAAAAA. */ +{ "and", 0x26447000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* and<.f> 0,limm,u6 0010011001000100F111uuuuuu111110. */ +{ "and", 0x2644703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* and<.f><.cc> 0,limm,u6 0010011011000100F111uuuuuu1QQQQQ. */ +{ "and", 0x26C47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* and<.f> 0,limm,s12 0010011010000100F111ssssssSSSSSS. */ +{ "and", 0x26847000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* and<.f> a,limm,limm 0010011000000100F111111110AAAAAA. */ +{ "and", 0x26047F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* and<.f> 0,limm,limm 0010011000000100F111111110111110. */ +{ "and", 0x26047FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* and<.f><.cc> 0,limm,limm 0010011011000100F1111111100QQQQQ. */ +{ "and", 0x26C47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* and_s b,b,c 01111bbbccc00100. */ +{ "and_s", 0x00007804, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* asl<.f> b,c 00100bbb00101111FBBBCCCCCC000000. */ +{ "asl", 0x202F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* asl<.f> 0,c 0010011000101111F111CCCCCC000000. */ +{ "asl", 0x262F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* asl<.f> a,b,c 00101bbb00000000FBBBCCCCCCAAAAAA. */ +{ "asl", 0x28000000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }}, + +/* asl<.f> 0,b,c 00101bbb00000000FBBBCCCCCC111110. */ +{ "asl", 0x2800003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }}, + +/* asl<.f><.cc> b,b,c 00101bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "asl", 0x28C00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asl<.f> b,u6 00100bbb01101111FBBBuuuuuu000000. */ +{ "asl", 0x206F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,u6 0010011001101111F111uuuuuu000000. */ +{ "asl", 0x266F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* asl<.f> a,b,u6 00101bbb01000000FBBBuuuuuuAAAAAA. */ +{ "asl", 0x28400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,b,u6 00101bbb01000000FBBBuuuuuu111110. */ +{ "asl", 0x2840003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asl<.f><.cc> b,b,u6 00101bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "asl", 0x28C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asl<.f> b,b,s12 00101bbb10000000FBBBssssssSSSSSS. */ +{ "asl", 0x28800000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asl<.f> b,limm 00100bbb00101111FBBB111110000000. */ +{ "asl", 0x202F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* asl<.f> 0,limm 0010011000101111F111111110000000. */ +{ "asl", 0x262F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* asl<.f> a,limm,c 0010111000000000F111CCCCCCAAAAAA. */ +{ "asl", 0x2E007000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }}, + +/* asl<.f> a,b,limm 00101bbb00000000FBBB111110AAAAAA. */ +{ "asl", 0x28000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }}, + +/* asl<.f> 0,limm,c 0010111000000000F111CCCCCC111110. */ +{ "asl", 0x2E00703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }}, + +/* asl<.f> 0,b,limm 00101bbb00000000FBBB111110111110. */ +{ "asl", 0x28000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }}, + +/* asl<.f><.cc> b,b,limm 00101bbb11000000FBBB1111100QQQQQ. */ +{ "asl", 0x28C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asl<.f><.cc> 0,limm,c 0010111011000000F111CCCCCC0QQQQQ. */ +{ "asl", 0x2EC07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asl<.f> a,limm,u6 0010111001000000F111uuuuuuAAAAAA. */ +{ "asl", 0x2E407000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asl<.f> 0,limm,u6 0010111001000000F111uuuuuu111110. */ +{ "asl", 0x2E40703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asl<.f><.cc> 0,limm,u6 0010111011000000F111uuuuuu1QQQQQ. */ +{ "asl", 0x2EC07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asl<.f> 0,limm,s12 0010111010000000F111ssssssSSSSSS. */ +{ "asl", 0x2E807000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asl<.f> a,limm,limm 0010111000000000F111111110AAAAAA. */ +{ "asl", 0x2E007F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asl<.f> 0,limm,limm 0010111000000000F111111110111110. */ +{ "asl", 0x2E007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asl<.f><.cc> 0,limm,limm 0010111011000000F1111111100QQQQQ. */ +{ "asl", 0x2EC07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* aslacc c 00101000001011110000CCCCCC111111. */ +{ "aslacc", 0x282F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }}, + +/* aslacc u6 00101000011011110000uuuuuu111111. */ +{ "aslacc", 0x286F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }}, + +/* asldw<.f> a,b,c 00101bbb00100001FBBBCCCCCCAAAAAA. */ +{ "asldw", 0x28210000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* asldw<.f> 0,b,c 00101bbb00100001FBBBCCCCCC111110. */ +{ "asldw", 0x2821003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* asldw<.f><.cc> b,b,c 00101bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "asldw", 0x28E10000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asldw<.f> a,b,u6 00101bbb01100001FBBBuuuuuuAAAAAA. */ +{ "asldw", 0x28610000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asldw<.f> 0,b,u6 00101bbb01100001FBBBuuuuuu111110. */ +{ "asldw", 0x2861003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asldw<.f><.cc> b,b,u6 00101bbb11100001FBBBuuuuuu1QQQQQ. */ +{ "asldw", 0x28E10020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asldw<.f> b,b,s12 00101bbb10100001FBBBssssssSSSSSS. */ +{ "asldw", 0x28A10000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asldw<.f> a,limm,c 0010111000100001F111CCCCCCAAAAAA. */ +{ "asldw", 0x2E217000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asldw<.f> a,b,limm 00101bbb00100001FBBB111110AAAAAA. */ +{ "asldw", 0x28210F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asldw<.f> 0,limm,c 0010111000100001F111CCCCCC111110. */ +{ "asldw", 0x2E21703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asldw<.f> 0,b,limm 00101bbb00100001FBBB111110111110. */ +{ "asldw", 0x28210FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,c 0010111011100001F111CCCCCC0QQQQQ. */ +{ "asldw", 0x2EE17000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asldw<.f><.cc> b,b,limm 00101bbb11100001FBBB1111100QQQQQ. */ +{ "asldw", 0x28E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asldw<.f> a,limm,u6 0010111001100001F111uuuuuuAAAAAA. */ +{ "asldw", 0x2E617000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asldw<.f> 0,limm,u6 0010111001100001F111uuuuuu111110. */ +{ "asldw", 0x2E61703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,u6 0010111011100001F111uuuuuu1QQQQQ. */ +{ "asldw", 0x2EE17020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asldw<.f> 0,limm,s12 0010111010100001F111ssssssSSSSSS. */ +{ "asldw", 0x2EA17000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asldw<.f> a,limm,limm 0010111000100001F111111110AAAAAA. */ +{ "asldw", 0x2E217F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asldw<.f> 0,limm,limm 0010111000100001F111111110111110. */ +{ "asldw", 0x2E217FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asldw<.f><.cc> 0,limm,limm 0010111011100001F1111111100QQQQQ. */ +{ "asldw", 0x2EE17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asls<.f> a,b,c 00101bbb00001010FBBBCCCCCCAAAAAA. */ +{ "asls", 0x280A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* asls<.f> 0,b,c 00101bbb00001010FBBBCCCCCC111110. */ +{ "asls", 0x280A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* asls<.f><.cc> b,b,c 00101bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "asls", 0x28CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asls<.f> a,b,u6 00101bbb01001010FBBBuuuuuuAAAAAA. */ +{ "asls", 0x284A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asls<.f> 0,b,u6 00101bbb01001010FBBBuuuuuu111110. */ +{ "asls", 0x284A003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asls<.f><.cc> b,b,u6 00101bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "asls", 0x28CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asls<.f> b,b,s12 00101bbb10001010FBBBssssssSSSSSS. */ +{ "asls", 0x288A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asls<.f> a,limm,c 0010111000001010F111CCCCCCAAAAAA. */ +{ "asls", 0x2E0A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asls<.f> a,b,limm 00101bbb00001010FBBB111110AAAAAA. */ +{ "asls", 0x280A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asls<.f> 0,limm,c 0010111000001010F111CCCCCC111110. */ +{ "asls", 0x2E0A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asls<.f> 0,b,limm 00101bbb00001010FBBB111110111110. */ +{ "asls", 0x280A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asls<.f><.cc> b,b,limm 00101bbb11001010FBBB1111100QQQQQ. */ +{ "asls", 0x28CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asls<.f><.cc> 0,limm,c 0010111011001010F111CCCCCC0QQQQQ. */ +{ "asls", 0x2ECA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asls<.f> a,limm,u6 0010111001001010F111uuuuuuAAAAAA. */ +{ "asls", 0x2E4A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asls<.f> 0,limm,u6 0010111001001010F111uuuuuu111110. */ +{ "asls", 0x2E4A703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asls<.f><.cc> 0,limm,u6 0010111011001010F111uuuuuu1QQQQQ. */ +{ "asls", 0x2ECA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asls<.f> 0,limm,s12 0010111010001010F111ssssssSSSSSS. */ +{ "asls", 0x2E8A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asls<.f> a,limm,limm 0010111000001010F111111110AAAAAA. */ +{ "asls", 0x2E0A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asls<.f> 0,limm,limm 0010111000001010F111111110111110. */ +{ "asls", 0x2E0A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asls<.f><.cc> 0,limm,limm 0010111011001010F1111111100QQQQQ. */ +{ "asls", 0x2ECA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* aslsacc c 00101001001011110000CCCCCC111111. */ +{ "aslsacc", 0x292F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }}, + +/* aslsacc u6 00101001011011110000uuuuuu111111. */ +{ "aslsacc", 0x296F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }}, + +/* aslsdw<.f> a,b,c 00101bbb00100100FBBBCCCCCCAAAAAA. */ +{ "aslsdw", 0x28240000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* aslsdw<.f> 0,b,c 00101bbb00100100FBBBCCCCCC111110. */ +{ "aslsdw", 0x2824003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* aslsdw<.f><.cc> b,b,c 00101bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "aslsdw", 0x28E40000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* aslsdw<.f> a,b,u6 00101bbb01100100FBBBuuuuuuAAAAAA. */ +{ "aslsdw", 0x28640000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* aslsdw<.f> 0,b,u6 00101bbb01100100FBBBuuuuuu111110. */ +{ "aslsdw", 0x2864003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* aslsdw<.f><.cc> b,b,u6 00101bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "aslsdw", 0x28E40020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* aslsdw<.f> b,b,s12 00101bbb10100100FBBBssssssSSSSSS. */ +{ "aslsdw", 0x28A40000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* aslsdw<.f> a,limm,c 0010111000100100F111CCCCCCAAAAAA. */ +{ "aslsdw", 0x2E247000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* aslsdw<.f> a,b,limm 00101bbb00100100FBBB111110AAAAAA. */ +{ "aslsdw", 0x28240F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* aslsdw<.f> 0,limm,c 0010111000100100F111CCCCCC111110. */ +{ "aslsdw", 0x2E24703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* aslsdw<.f> 0,b,limm 00101bbb00100100FBBB111110111110. */ +{ "aslsdw", 0x28240FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,c 0010111011100100F111CCCCCC0QQQQQ. */ +{ "aslsdw", 0x2EE47000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* aslsdw<.f><.cc> b,b,limm 00101bbb11100100FBBB1111100QQQQQ. */ +{ "aslsdw", 0x28E40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* aslsdw<.f> a,limm,u6 0010111001100100F111uuuuuuAAAAAA. */ +{ "aslsdw", 0x2E647000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* aslsdw<.f> 0,limm,u6 0010111001100100F111uuuuuu111110. */ +{ "aslsdw", 0x2E64703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,u6 0010111011100100F111uuuuuu1QQQQQ. */ +{ "aslsdw", 0x2EE47020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* aslsdw<.f> 0,limm,s12 0010111010100100F111ssssssSSSSSS. */ +{ "aslsdw", 0x2EA47000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* aslsdw<.f> a,limm,limm 0010111000100100F111111110AAAAAA. */ +{ "aslsdw", 0x2E247F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* aslsdw<.f> 0,limm,limm 0010111000100100F111111110111110. */ +{ "aslsdw", 0x2E247FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* aslsdw<.f><.cc> 0,limm,limm 0010111011100100F1111111100QQQQQ. */ +{ "aslsdw", 0x2EE47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asl_s b,c 01111bbbccc11011. */ +{ "asl_s", 0x0000781B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }}, + +/* asl_s b,b,c 01111bbbccc11000. */ +{ "asl_s", 0x00007818, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* asl_s c,b,u3 01101bbbccc10uuu. */ +{ "asl_s", 0x00006810, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, + +/* asl_s b,b,u5 10111bbb000uuuuu. */ +{ "asl_s", 0x0000B800, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* asr<.f> b,c 00100bbb00101111FBBBCCCCCC000001. */ +{ "asr", 0x202F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* asr<.f> 0,c 0010011000101111F111CCCCCC000001. */ +{ "asr", 0x262F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* asr<.f> a,b,c 00101bbb00000010FBBBCCCCCCAAAAAA. */ +{ "asr", 0x28020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }}, + +/* asr<.f> 0,b,c 00101bbb00000010FBBBCCCCCC111110. */ +{ "asr", 0x2802003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }}, + +/* asr<.f><.cc> b,b,c 00101bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "asr", 0x28C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asr<.f> b,u6 00100bbb01101111FBBBuuuuuu000001. */ +{ "asr", 0x206F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,u6 0010011001101111F111uuuuuu000001. */ +{ "asr", 0x266F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* asr<.f> a,b,u6 00101bbb01000010FBBBuuuuuuAAAAAA. */ +{ "asr", 0x28420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,b,u6 00101bbb01000010FBBBuuuuuu111110. */ +{ "asr", 0x2842003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asr<.f><.cc> b,b,u6 00101bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "asr", 0x28C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asr<.f> b,b,s12 00101bbb10000010FBBBssssssSSSSSS. */ +{ "asr", 0x28820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asr<.f> b,limm 00100bbb00101111FBBB111110000001. */ +{ "asr", 0x202F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* asr<.f> 0,limm 0010011000101111F111111110000001. */ +{ "asr", 0x262F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* asr<.f> a,limm,c 0010111000000010F111CCCCCCAAAAAA. */ +{ "asr", 0x2E027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }}, + +/* asr<.f> a,b,limm 00101bbb00000010FBBB111110AAAAAA. */ +{ "asr", 0x28020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }}, + +/* asr<.f> 0,limm,c 0010111000000010F111CCCCCC111110. */ +{ "asr", 0x2E02703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }}, + +/* asr<.f> 0,b,limm 00101bbb00000010FBBB111110111110. */ +{ "asr", 0x28020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }}, + +/* asr<.f><.cc> b,b,limm 00101bbb11000010FBBB1111100QQQQQ. */ +{ "asr", 0x28C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asr<.f><.cc> 0,limm,c 0010111011000010F111CCCCCC0QQQQQ. */ +{ "asr", 0x2EC27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asr<.f> a,limm,u6 0010111001000010F111uuuuuuAAAAAA. */ +{ "asr", 0x2E427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asr<.f> 0,limm,u6 0010111001000010F111uuuuuu111110. */ +{ "asr", 0x2E42703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asr<.f><.cc> 0,limm,u6 0010111011000010F111uuuuuu1QQQQQ. */ +{ "asr", 0x2EC27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asr<.f> 0,limm,s12 0010111010000010F111ssssssSSSSSS. */ +{ "asr", 0x2E827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asr<.f> a,limm,limm 0010111000000010F111111110AAAAAA. */ +{ "asr", 0x2E027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asr<.f> 0,limm,limm 0010111000000010F111111110111110. */ +{ "asr", 0x2E027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asr<.f><.cc> 0,limm,limm 0010111011000010F1111111100QQQQQ. */ +{ "asr", 0x2EC27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asr16<.f> b,c 00101bbb00101111FBBBCCCCCC001100. */ +{ "asr16", 0x282F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }}, + +/* asr16<.f> 0,c 0010111000101111F111CCCCCC001100. */ +{ "asr16", 0x2E2F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }}, + +/* asr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001100. */ +{ "asr16", 0x286F000C, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* asr16<.f> 0,u6 0010111001101111F111uuuuuu001100. */ +{ "asr16", 0x2E6F700C, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* asr16<.f> b,limm 00101bbb00101111FBBB111110001100. */ +{ "asr16", 0x282F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }}, + +/* asr16<.f> 0,limm 0010111000101111F111111110001100. */ +{ "asr16", 0x2E2F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }}, + +/* asr8<.f> b,c 00101bbb00101111FBBBCCCCCC001101. */ +{ "asr8", 0x282F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }}, + +/* asr8<.f> 0,c 0010111000101111F111CCCCCC001101. */ +{ "asr8", 0x2E2F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }}, + +/* asr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001101. */ +{ "asr8", 0x286F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* asr8<.f> 0,u6 0010111001101111F111uuuuuu001101. */ +{ "asr8", 0x2E6F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* asr8<.f> b,limm 00101bbb00101111FBBB111110001101. */ +{ "asr8", 0x282F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }}, + +/* asr8<.f> 0,limm 0010111000101111F111111110001101. */ +{ "asr8", 0x2E2F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }}, + +/* asrdw<.f> a,b,c 00101bbb00100010FBBBCCCCCCAAAAAA. */ +{ "asrdw", 0x28220000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* asrdw<.f> 0,b,c 00101bbb00100010FBBBCCCCCC111110. */ +{ "asrdw", 0x2822003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* asrdw<.f><.cc> b,b,c 00101bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "asrdw", 0x28E20000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asrdw<.f> a,b,u6 00101bbb01100010FBBBuuuuuuAAAAAA. */ +{ "asrdw", 0x28620000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asrdw<.f> 0,b,u6 00101bbb01100010FBBBuuuuuu111110. */ +{ "asrdw", 0x2862003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asrdw<.f><.cc> b,b,u6 00101bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "asrdw", 0x28E20020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asrdw<.f> b,b,s12 00101bbb10100010FBBBssssssSSSSSS. */ +{ "asrdw", 0x28A20000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asrdw<.f> a,limm,c 0010111000100010F111CCCCCCAAAAAA. */ +{ "asrdw", 0x2E227000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asrdw<.f> a,b,limm 00101bbb00100010FBBB111110AAAAAA. */ +{ "asrdw", 0x28220F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asrdw<.f> 0,limm,c 0010111000100010F111CCCCCC111110. */ +{ "asrdw", 0x2E22703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asrdw<.f> 0,b,limm 00101bbb00100010FBBB111110111110. */ +{ "asrdw", 0x28220FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,c 0010111011100010F111CCCCCC0QQQQQ. */ +{ "asrdw", 0x2EE27000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asrdw<.f><.cc> b,b,limm 00101bbb11100010FBBB1111100QQQQQ. */ +{ "asrdw", 0x28E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asrdw<.f> a,limm,u6 0010111001100010F111uuuuuuAAAAAA. */ +{ "asrdw", 0x2E627000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrdw<.f> 0,limm,u6 0010111001100010F111uuuuuu111110. */ +{ "asrdw", 0x2E62703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,u6 0010111011100010F111uuuuuu1QQQQQ. */ +{ "asrdw", 0x2EE27020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asrdw<.f> 0,limm,s12 0010111010100010F111ssssssSSSSSS. */ +{ "asrdw", 0x2EA27000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asrdw<.f> a,limm,limm 0010111000100010F111111110AAAAAA. */ +{ "asrdw", 0x2E227F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asrdw<.f> 0,limm,limm 0010111000100010F111111110111110. */ +{ "asrdw", 0x2E227FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asrdw<.f><.cc> 0,limm,limm 0010111011100010F1111111100QQQQQ. */ +{ "asrdw", 0x2EE27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asrs<.f> a,b,c 00101bbb00001011FBBBCCCCCCAAAAAA. */ +{ "asrs", 0x280B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* asrs<.f> 0,b,c 00101bbb00001011FBBBCCCCCC111110. */ +{ "asrs", 0x280B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* asrs<.f><.cc> b,b,c 00101bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "asrs", 0x28CB0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asrs<.f> a,b,u6 00101bbb01001011FBBBuuuuuuAAAAAA. */ +{ "asrs", 0x284B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asrs<.f> 0,b,u6 00101bbb01001011FBBBuuuuuu111110. */ +{ "asrs", 0x284B003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asrs<.f><.cc> b,b,u6 00101bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "asrs", 0x28CB0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asrs<.f> b,b,s12 00101bbb10001011FBBBssssssSSSSSS. */ +{ "asrs", 0x288B0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asrs<.f> a,limm,c 0010111000001011F111CCCCCCAAAAAA. */ +{ "asrs", 0x2E0B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asrs<.f> a,b,limm 00101bbb00001011FBBB111110AAAAAA. */ +{ "asrs", 0x280B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asrs<.f> 0,limm,c 0010111000001011F111CCCCCC111110. */ +{ "asrs", 0x2E0B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asrs<.f> 0,b,limm 00101bbb00001011FBBB111110111110. */ +{ "asrs", 0x280B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asrs<.f><.cc> b,b,limm 00101bbb11001011FBBB1111100QQQQQ. */ +{ "asrs", 0x28CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asrs<.f><.cc> 0,limm,c 0010111011001011F111CCCCCC0QQQQQ. */ +{ "asrs", 0x2ECB7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asrs<.f> a,limm,u6 0010111001001011F111uuuuuuAAAAAA. */ +{ "asrs", 0x2E4B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrs<.f> 0,limm,u6 0010111001001011F111uuuuuu111110. */ +{ "asrs", 0x2E4B703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrs<.f><.cc> 0,limm,u6 0010111011001011F111uuuuuu1QQQQQ. */ +{ "asrs", 0x2ECB7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asrs<.f> 0,limm,s12 0010111010001011F111ssssssSSSSSS. */ +{ "asrs", 0x2E8B7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asrs<.f> a,limm,limm 0010111000001011F111111110AAAAAA. */ +{ "asrs", 0x2E0B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asrs<.f> 0,limm,limm 0010111000001011F111111110111110. */ +{ "asrs", 0x2E0B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asrs<.f><.cc> 0,limm,limm 0010111011001011F1111111100QQQQQ. */ +{ "asrs", 0x2ECB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asrsdw<.f> a,b,c 00101bbb00100101FBBBCCCCCCAAAAAA. */ +{ "asrsdw", 0x28250000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* asrsdw<.f> 0,b,c 00101bbb00100101FBBBCCCCCC111110. */ +{ "asrsdw", 0x2825003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* asrsdw<.f><.cc> b,b,c 00101bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "asrsdw", 0x28E50000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asrsdw<.f> a,b,u6 00101bbb01100101FBBBuuuuuuAAAAAA. */ +{ "asrsdw", 0x28650000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asrsdw<.f> 0,b,u6 00101bbb01100101FBBBuuuuuu111110. */ +{ "asrsdw", 0x2865003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asrsdw<.f><.cc> b,b,u6 00101bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "asrsdw", 0x28E50020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asrsdw<.f> b,b,s12 00101bbb10100101FBBBssssssSSSSSS. */ +{ "asrsdw", 0x28A50000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asrsdw<.f> a,limm,c 0010111000100101F111CCCCCCAAAAAA. */ +{ "asrsdw", 0x2E257000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asrsdw<.f> a,b,limm 00101bbb00100101FBBB111110AAAAAA. */ +{ "asrsdw", 0x28250F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asrsdw<.f> 0,limm,c 0010111000100101F111CCCCCC111110. */ +{ "asrsdw", 0x2E25703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asrsdw<.f> 0,b,limm 00101bbb00100101FBBB111110111110. */ +{ "asrsdw", 0x28250FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,c 0010111011100101F111CCCCCC0QQQQQ. */ +{ "asrsdw", 0x2EE57000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asrsdw<.f><.cc> b,b,limm 00101bbb11100101FBBB1111100QQQQQ. */ +{ "asrsdw", 0x28E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asrsdw<.f> a,limm,u6 0010111001100101F111uuuuuuAAAAAA. */ +{ "asrsdw", 0x2E657000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrsdw<.f> 0,limm,u6 0010111001100101F111uuuuuu111110. */ +{ "asrsdw", 0x2E65703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,u6 0010111011100101F111uuuuuu1QQQQQ. */ +{ "asrsdw", 0x2EE57020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asrsdw<.f> 0,limm,s12 0010111010100101F111ssssssSSSSSS. */ +{ "asrsdw", 0x2EA57000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asrsdw<.f> a,limm,limm 0010111000100101F111111110AAAAAA. */ +{ "asrsdw", 0x2E257F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asrsdw<.f> 0,limm,limm 0010111000100101F111111110111110. */ +{ "asrsdw", 0x2E257FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asrsdw<.f><.cc> 0,limm,limm 0010111011100101F1111111100QQQQQ. */ +{ "asrsdw", 0x2EE57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asrsr<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ +{ "asrsr", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* asrsr<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ +{ "asrsr", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* asrsr<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "asrsr", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* asrsr<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ +{ "asrsr", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* asrsr<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ +{ "asrsr", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* asrsr<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "asrsr", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* asrsr<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ +{ "asrsr", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* asrsr<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ +{ "asrsr", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* asrsr<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ +{ "asrsr", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* asrsr<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ +{ "asrsr", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* asrsr<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ +{ "asrsr", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* asrsr<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ +{ "asrsr", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* asrsr<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ +{ "asrsr", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* asrsr<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ +{ "asrsr", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrsr<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ +{ "asrsr", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* asrsr<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ +{ "asrsr", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* asrsr<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ +{ "asrsr", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* asrsr<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ +{ "asrsr", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* asrsr<.f> 0,limm,limm 0010111000001100F111111110111110. */ +{ "asrsr", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* asrsr<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ +{ "asrsr", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* asr_s b,c 01111bbbccc11100. */ +{ "asr_s", 0x0000781C, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }}, + +/* asr_s b,b,c 01111bbbccc11010. */ +{ "asr_s", 0x0000781A, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* asr_s c,b,u3 01101bbbccc11uuu. */ +{ "asr_s", 0x00006818, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, + +/* asr_s b,b,u5 10111bbb010uuuuu. */ +{ "asr_s", 0x0000B840, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* avgqb<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ +{ "avgqb", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* avgqb<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "avgqb", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* avgqb<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ +{ "avgqb", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* avgqb<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "avgqb", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* avgqb<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ +{ "avgqb", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* avgqb<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ +{ "avgqb", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* avgqb<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ +{ "avgqb", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* avgqb<.f><.cc> b,b,limm 00110bbb11100011FBBB1111100QQQQQ. */ +{ "avgqb", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */ +{ "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A16_5 }, { C_D }}, + +/* b<.d><cc> s21 00000ssssssssss0SSSSSSSSSSNQQQQQ. */ +{ "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }}, + +/* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110. */ +{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110. */ +{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110. */ +{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110. */ +{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110. */ +{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110. */ +{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110. */ +{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110. */ +{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110. */ +{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110. */ +{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* bbit0 limm,limm,s9 00001110sssssss1S111111110001110. */ +{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, + +/* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110. */ +{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111. */ +{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111. */ +{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111. */ +{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111. */ +{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111. */ +{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111. */ +{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111. */ +{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111. */ +{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111. */ +{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111. */ +{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* bbit1 limm,limm,s9 00001110sssssss1S111111110001111. */ +{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }}, + +/* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111. */ +{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA. */ +{ "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* bclr<.f> 0,b,c 00100bbb00010000FBBBCCCCCC111110. */ +{ "bclr", 0x2010003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* bclr<.f><.cc> b,b,c 00100bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "bclr", 0x20D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bclr<.f> a,b,u6 00100bbb01010000FBBBuuuuuuAAAAAA. */ +{ "bclr", 0x20500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bclr<.f> 0,b,u6 00100bbb01010000FBBBuuuuuu111110. */ +{ "bclr", 0x2050003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bclr<.f><.cc> b,b,u6 00100bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "bclr", 0x20D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bclr<.f> b,b,s12 00100bbb10010000FBBBssssssSSSSSS. */ +{ "bclr", 0x20900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bclr<.f> a,limm,c 0010011000010000F111CCCCCCAAAAAA. */ +{ "bclr", 0x26107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bclr<.f> a,b,limm 00100bbb00010000FBBB111110AAAAAA. */ +{ "bclr", 0x20100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bclr<.f> 0,limm,c 0010011000010000F111CCCCCC111110. */ +{ "bclr", 0x2610703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bclr<.f> 0,b,limm 00100bbb00010000FBBB111110111110. */ +{ "bclr", 0x20100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bclr<.f><.cc> b,b,limm 00100bbb11010000FBBB1111100QQQQQ. */ +{ "bclr", 0x20D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bclr<.f><.cc> 0,limm,c 0010011011010000F111CCCCCC0QQQQQ. */ +{ "bclr", 0x26D07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bclr<.f> a,limm,u6 0010011001010000F111uuuuuuAAAAAA. */ +{ "bclr", 0x26507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bclr<.f> 0,limm,u6 0010011001010000F111uuuuuu111110. */ +{ "bclr", 0x2650703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bclr<.f><.cc> 0,limm,u6 0010011011010000F111uuuuuu1QQQQQ. */ +{ "bclr", 0x26D07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bclr<.f> 0,limm,s12 0010011010010000F111ssssssSSSSSS. */ +{ "bclr", 0x26907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bclr<.f> a,limm,limm 0010011000010000F111111110AAAAAA. */ +{ "bclr", 0x26107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bclr<.f> 0,limm,limm 0010011000010000F111111110111110. */ +{ "bclr", 0x26107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bclr<.f><.cc> 0,limm,limm 0010011011010000F1111111100QQQQQ. */ +{ "bclr", 0x26D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* bclr_s b,b,u5 10111bbb101uuuuu. */ +{ "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* beq_s s10 1111001sssssssss. */ +{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }}, + +/* bge_s s7 1111011001ssssss. */ +{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bgt_s s7 1111011000ssssss. */ +{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bhi_s s7 1111011100ssssss. */ +{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bhs_s s7 1111011101ssssss. */ +{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bi c 00100RRR001001000RRRCCCCCCRRRRRR. */ +{ "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* bi limm 00100RRR001001000RRR111110RRRRRR. */ +{ "bi", 0x20240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* bic<.f> a,b,c 00100bbb00000110FBBBCCCCCCAAAAAA. */ +{ "bic", 0x20060000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* bic<.f> 0,b,c 00100bbb00000110FBBBCCCCCC111110. */ +{ "bic", 0x2006003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* bic<.f><.cc> b,b,c 00100bbb11000110FBBBCCCCCC0QQQQQ. */ +{ "bic", 0x20C60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bic<.f> a,b,u6 00100bbb01000110FBBBuuuuuuAAAAAA. */ +{ "bic", 0x20460000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bic<.f> 0,b,u6 00100bbb01000110FBBBuuuuuu111110. */ +{ "bic", 0x2046003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bic<.f><.cc> b,b,u6 00100bbb11000110FBBBuuuuuu1QQQQQ. */ +{ "bic", 0x20C60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bic<.f> b,b,s12 00100bbb10000110FBBBssssssSSSSSS. */ +{ "bic", 0x20860000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bic<.f> a,limm,c 0010011000000110F111CCCCCCAAAAAA. */ +{ "bic", 0x26067000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bic<.f> a,b,limm 00100bbb00000110FBBB111110AAAAAA. */ +{ "bic", 0x20060F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bic<.f> 0,limm,c 0010011000000110F111CCCCCC111110. */ +{ "bic", 0x2606703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bic<.f> 0,b,limm 00100bbb00000110FBBB111110111110. */ +{ "bic", 0x20060FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bic<.f><.cc> b,b,limm 00100bbb11000110FBBB1111100QQQQQ. */ +{ "bic", 0x20C60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bic<.f><.cc> 0,limm,c 0010011011000110F111CCCCCC0QQQQQ. */ +{ "bic", 0x26C67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bic<.f> a,limm,u6 0010011001000110F111uuuuuuAAAAAA. */ +{ "bic", 0x26467000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bic<.f> 0,limm,u6 0010011001000110F111uuuuuu111110. */ +{ "bic", 0x2646703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bic<.f><.cc> 0,limm,u6 0010011011000110F111uuuuuu1QQQQQ. */ +{ "bic", 0x26C67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bic<.f> 0,limm,s12 0010011010000110F111ssssssSSSSSS. */ +{ "bic", 0x26867000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bic<.f> a,limm,limm 0010011000000110F111111110AAAAAA. */ +{ "bic", 0x26067F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bic<.f> 0,limm,limm 0010011000000110F111111110111110. */ +{ "bic", 0x26067FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bic<.f><.cc> 0,limm,limm 0010011011000110F1111111100QQQQQ. */ +{ "bic", 0x26C67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* bic_s b,b,c 01111bbbccc00110. */ +{ "bic_s", 0x00007806, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* bih c 00100RRR001001010RRRCCCCCCRRRRRR. */ +{ "bih", 0x20250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* bih limm 00100RRR001001010RRR111110RRRRRR. */ +{ "bih", 0x20250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */ +{ "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM25_A32_5 }, { C_D }}, + +/* bl<.cc><.d> s21 00001sssssssss00SSSSSSSSSSNQQQQQ. */ +{ "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }}, + +/* ble_s s7 1111011011ssssss. */ +{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* blo_s s7 1111011110ssssss. */ +{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bls_s s7 1111011111ssssss. */ +{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* blt_s s7 1111011010ssssss. */ +{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }}, + +/* bl_s s13 11111sssssssssss. */ +{ "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }}, + +/* bmsk<.f> a,b,c 00100bbb00010011FBBBCCCCCCAAAAAA. */ +{ "bmsk", 0x20130000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* bmsk<.f> 0,b,c 00100bbb00010011FBBBCCCCCC111110. */ +{ "bmsk", 0x2013003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* bmsk<.f><.cc> b,b,c 00100bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "bmsk", 0x20D30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bmsk<.f> a,b,u6 00100bbb01010011FBBBuuuuuuAAAAAA. */ +{ "bmsk", 0x20530000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bmsk<.f> 0,b,u6 00100bbb01010011FBBBuuuuuu111110. */ +{ "bmsk", 0x2053003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bmsk<.f><.cc> b,b,u6 00100bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "bmsk", 0x20D30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bmsk<.f> b,b,s12 00100bbb10010011FBBBssssssSSSSSS. */ +{ "bmsk", 0x20930000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bmsk<.f> a,limm,c 0010011000010011F111CCCCCCAAAAAA. */ +{ "bmsk", 0x26137000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bmsk<.f> a,b,limm 00100bbb00010011FBBB111110AAAAAA. */ +{ "bmsk", 0x20130F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bmsk<.f> 0,limm,c 0010011000010011F111CCCCCC111110. */ +{ "bmsk", 0x2613703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bmsk<.f> 0,b,limm 00100bbb00010011FBBB111110111110. */ +{ "bmsk", 0x20130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bmsk<.f><.cc> b,b,limm 00100bbb11010011FBBB1111100QQQQQ. */ +{ "bmsk", 0x20D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bmsk<.f><.cc> 0,limm,c 0010011011010011F111CCCCCC0QQQQQ. */ +{ "bmsk", 0x26D37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bmsk<.f> a,limm,u6 0010011001010011F111uuuuuuAAAAAA. */ +{ "bmsk", 0x26537000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bmsk<.f> 0,limm,u6 0010011001010011F111uuuuuu111110. */ +{ "bmsk", 0x2653703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bmsk<.f><.cc> 0,limm,u6 0010011011010011F111uuuuuu1QQQQQ. */ +{ "bmsk", 0x26D37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bmsk<.f> 0,limm,s12 0010011010010011F111ssssssSSSSSS. */ +{ "bmsk", 0x26937000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bmsk<.f> a,limm,limm 0010011000010011F111111110AAAAAA. */ +{ "bmsk", 0x26137F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bmsk<.f> 0,limm,limm 0010011000010011F111111110111110. */ +{ "bmsk", 0x26137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bmsk<.f><.cc> 0,limm,limm 0010011011010011F1111111100QQQQQ. */ +{ "bmsk", 0x26D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* bmskn<.f> a,b,c 00100bbb00101100FBBBCCCCCCAAAAAA. */ +{ "bmskn", 0x202C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* bmskn<.f> 0,b,c 00100bbb00101100FBBBCCCCCC111110. */ +{ "bmskn", 0x202C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* bmskn<.f><.cc> b,b,c 00100bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "bmskn", 0x20EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bmskn<.f> a,b,u6 00100bbb01101100FBBBuuuuuuAAAAAA. */ +{ "bmskn", 0x206C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bmskn<.f> 0,b,u6 00100bbb01101100FBBBuuuuuu111110. */ +{ "bmskn", 0x206C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bmskn<.f><.cc> b,b,u6 00100bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "bmskn", 0x20EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bmskn<.f> b,b,s12 00100bbb10101100FBBBssssssSSSSSS. */ +{ "bmskn", 0x20AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bmskn<.f> a,limm,c 0010011000101100F111CCCCCCAAAAAA. */ +{ "bmskn", 0x262C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bmskn<.f> a,b,limm 00100bbb00101100FBBB111110AAAAAA. */ +{ "bmskn", 0x202C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bmskn<.f> 0,limm,c 0010011000101100F111CCCCCC111110. */ +{ "bmskn", 0x262C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bmskn<.f> 0,b,limm 00100bbb00101100FBBB111110111110. */ +{ "bmskn", 0x202C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bmskn<.f><.cc> b,b,limm 00100bbb11101100FBBB1111100QQQQQ. */ +{ "bmskn", 0x20EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bmskn<.f><.cc> 0,limm,c 0010011011101100F111CCCCCC0QQQQQ. */ +{ "bmskn", 0x26EC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bmskn<.f> a,limm,u6 0010011001101100F111uuuuuuAAAAAA. */ +{ "bmskn", 0x266C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bmskn<.f> 0,limm,u6 0010011001101100F111uuuuuu111110. */ +{ "bmskn", 0x266C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bmskn<.f><.cc> 0,limm,u6 0010011011101100F111uuuuuu1QQQQQ. */ +{ "bmskn", 0x26EC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bmskn<.f> 0,limm,s12 0010011010101100F111ssssssSSSSSS. */ +{ "bmskn", 0x26AC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bmskn<.f> a,limm,limm 0010011000101100F111111110AAAAAA. */ +{ "bmskn", 0x262C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bmskn<.f> 0,limm,limm 0010011000101100F111111110111110. */ +{ "bmskn", 0x262C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bmskn<.f><.cc> 0,limm,limm 0010011011101100F1111111100QQQQQ. */ +{ "bmskn", 0x26EC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* bmsk_s b,b,u5 10111bbb110uuuuu. */ +{ "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* bne_s s10 1111010sssssssss. */ +{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }}, + +/* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000. */ +{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000. */ +{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000. */ +{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000. */ +{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* breq b,limm,s9 00001bbbsssssss1SBBB111110000000. */ +{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* breq limm,c,s9 00001110sssssss1S111CCCCCC000000. */ +{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000. */ +{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000. */ +{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000. */ +{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000. */ +{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000. */ +{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* breq_s b,0,s8 11101bbb0sssssss. */ +{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }}, + +/* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011. */ +{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011. */ +{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011. */ +{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011. */ +{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brge b,limm,s9 00001bbbsssssss1SBBB111110000011. */ +{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* brge limm,c,s9 00001110sssssss1S111CCCCCC000011. */ +{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011. */ +{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011. */ +{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011. */ +{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011. */ +{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011. */ +{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101. */ +{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101. */ +{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101. */ +{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101. */ +{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101. */ +{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101. */ +{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101. */ +{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101. */ +{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101. */ +{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101. */ +{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101. */ +{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* brk 00100101011011110000000000111111. */ +{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* brk_s 0111111111111111. */ +{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */ +{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100. */ +{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100. */ +{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100. */ +{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100. */ +{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100. */ +{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100. */ +{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100. */ +{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100. */ +{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100. */ +{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100. */ +{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010. */ +{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010. */ +{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010. */ +{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010. */ +{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010. */ +{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010. */ +{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010. */ +{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010. */ +{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010. */ +{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010. */ +{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010. */ +{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001. */ +{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }}, + +/* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001. */ +{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001. */ +{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }}, + +/* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001. */ +{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }}, + +/* brne b,limm,s9 00001bbbsssssss1SBBB111110000001. */ +{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }}, + +/* brne limm,c,s9 00001110sssssss1S111CCCCCC000001. */ +{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }}, + +/* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001. */ +{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }}, + +/* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001. */ +{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }}, + +/* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001. */ +{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }}, + +/* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001. */ +{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }}, + +/* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001. */ +{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }}, + +/* brne_s b,0,s8 11101bbb1sssssss. */ +{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }}, + +/* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA. */ +{ "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* bset<.f> 0,b,c 00100bbb00001111FBBBCCCCCC111110. */ +{ "bset", 0x200F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* bset<.f><.cc> b,b,c 00100bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "bset", 0x20CF0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bset<.f> a,b,u6 00100bbb01001111FBBBuuuuuuAAAAAA. */ +{ "bset", 0x204F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bset<.f> 0,b,u6 00100bbb01001111FBBBuuuuuu111110. */ +{ "bset", 0x204F003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bset<.f><.cc> b,b,u6 00100bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "bset", 0x20CF0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bset<.f> b,b,s12 00100bbb10001111FBBBssssssSSSSSS. */ +{ "bset", 0x208F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bset<.f> a,limm,c 0010011000001111F111CCCCCCAAAAAA. */ +{ "bset", 0x260F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bset<.f> a,b,limm 00100bbb00001111FBBB111110AAAAAA. */ +{ "bset", 0x200F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bset<.f> 0,limm,c 0010011000001111F111CCCCCC111110. */ +{ "bset", 0x260F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bset<.f> 0,b,limm 00100bbb00001111FBBB111110111110. */ +{ "bset", 0x200F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bset<.f><.cc> b,b,limm 00100bbb11001111FBBB1111100QQQQQ. */ +{ "bset", 0x20CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bset<.f><.cc> 0,limm,c 0010011011001111F111CCCCCC0QQQQQ. */ +{ "bset", 0x26CF7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bset<.f> a,limm,u6 0010011001001111F111uuuuuuAAAAAA. */ +{ "bset", 0x264F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bset<.f> 0,limm,u6 0010011001001111F111uuuuuu111110. */ +{ "bset", 0x264F703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bset<.f><.cc> 0,limm,u6 0010011011001111F111uuuuuu1QQQQQ. */ +{ "bset", 0x26CF7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bset<.f> 0,limm,s12 0010011010001111F111ssssssSSSSSS. */ +{ "bset", 0x268F7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bset<.f> a,limm,limm 0010011000001111F111111110AAAAAA. */ +{ "bset", 0x260F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bset<.f> 0,limm,limm 0010011000001111F111111110111110. */ +{ "bset", 0x260F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bset<.f><.cc> 0,limm,limm 0010011011001111F1111111100QQQQQ. */ +{ "bset", 0x26CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* bset_s b,b,u5 10111bbb100uuuuu. */ +{ "bset_s", 0x0000B880, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* btst b,c 00100bbb000100011BBBCCCCCCRRRRRR. */ +{ "btst", 0x20118000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { 0 }}, + +/* btst b,c 00100bbb000100011BBBCCCCCC000000. */ +{ "btst", 0x20118000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, RC }, { 0 }}, + +/* btst<.cc> b,c 00100bbb110100011BBBCCCCCC0QQQQQ. */ +{ "btst", 0x20D18000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_CC }}, + +/* btst b,u6 00100bbb010100011BBBuuuuuuRRRRRR. */ +{ "btst", 0x20518000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* btst b,u6 00100bbb010100011BBBuuuuuu000000. */ +{ "btst", 0x20518000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* btst<.cc> b,u6 00100bbb110100011BBBuuuuuu1QQQQQ. */ +{ "btst", 0x20D18020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* btst b,s12 00100bbb100100011BBBssssssSSSSSS. */ +{ "btst", 0x20918000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* btst limm,c 00100110000100011111CCCCCCRRRRRR. */ +{ "btst", 0x2611F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { 0 }}, + +/* btst b,limm 00100bbb000100011BBB111110RRRRRR. */ +{ "btst", 0x20118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { 0 }}, + +/* btst limm,c 00100110000100011111CCCCCC000000. */ +{ "btst", 0x2611F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, RC }, { 0 }}, + +/* btst b,limm 00100bbb000100011BBB111110000000. */ +{ "btst", 0x20118F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, LIMM }, { 0 }}, + +/* btst<.cc> b,limm 00100bbb110100011BBB1111100QQQQQ. */ +{ "btst", 0x20D18F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_CC }}, + +/* btst<.cc> limm,c 00100110110100011111CCCCCC0QQQQQ. */ +{ "btst", 0x26D1F000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { C_CC }}, + +/* btst limm,u6 00100110010100011111uuuuuuRRRRRR. */ +{ "btst", 0x2651F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* btst limm,u6 00100110010100011111uuuuuu000000. */ +{ "btst", 0x2651F000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* btst<.cc> limm,u6 00100110110100011111uuuuuu1QQQQQ. */ +{ "btst", 0x26D1F020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* btst limm,s12 00100110100100011111ssssssSSSSSS. */ +{ "btst", 0x2691F000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* btst limm,limm 00100110000100011111111110RRRRRR. */ +{ "btst", 0x2611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* btst limm,limm 00100110000100011111111110000000. */ +{ "btst", 0x2611FF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* btst<.cc> limm,limm 001001101101000111111111100QQQQQ. */ +{ "btst", 0x26D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* btst_s b,u5 10111bbb111uuuuu. */ +{ "btst_s", 0x0000B8E0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, UIMM5_11_S }, { 0 }}, + +/* bxor<.f> a,b,c 00100bbb00010010FBBBCCCCCCAAAAAA. */ +{ "bxor", 0x20120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* bxor<.f> 0,b,c 00100bbb00010010FBBBCCCCCC111110. */ +{ "bxor", 0x2012003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* bxor<.f><.cc> b,b,c 00100bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "bxor", 0x20D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* bxor<.f> a,b,u6 00100bbb01010010FBBBuuuuuuAAAAAA. */ +{ "bxor", 0x20520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* bxor<.f> 0,b,u6 00100bbb01010010FBBBuuuuuu111110. */ +{ "bxor", 0x2052003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* bxor<.f><.cc> b,b,u6 00100bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "bxor", 0x20D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* bxor<.f> b,b,s12 00100bbb10010010FBBBssssssSSSSSS. */ +{ "bxor", 0x20920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* bxor<.f> a,limm,c 0010011000010010F111CCCCCCAAAAAA. */ +{ "bxor", 0x26127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* bxor<.f> a,b,limm 00100bbb00010010FBBB111110AAAAAA. */ +{ "bxor", 0x20120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* bxor<.f> 0,limm,c 0010011000010010F111CCCCCC111110. */ +{ "bxor", 0x2612703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* bxor<.f> 0,b,limm 00100bbb00010010FBBB111110111110. */ +{ "bxor", 0x20120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* bxor<.f><.cc> b,b,limm 00100bbb11010010FBBB1111100QQQQQ. */ +{ "bxor", 0x20D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* bxor<.f><.cc> 0,limm,c 0010011011010010F111CCCCCC0QQQQQ. */ +{ "bxor", 0x26D27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* bxor<.f> a,limm,u6 0010011001010010F111uuuuuuAAAAAA. */ +{ "bxor", 0x26527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* bxor<.f> 0,limm,u6 0010011001010010F111uuuuuu111110. */ +{ "bxor", 0x2652703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* bxor<.f><.cc> 0,limm,u6 0010011011010010F111uuuuuu1QQQQQ. */ +{ "bxor", 0x26D27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* bxor<.f> 0,limm,s12 0010011010010010F111ssssssSSSSSS. */ +{ "bxor", 0x26927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* bxor<.f> a,limm,limm 0010011000010010F111111110AAAAAA. */ +{ "bxor", 0x26127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* bxor<.f> 0,limm,limm 0010011000010010F111111110111110. */ +{ "bxor", 0x26127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* bxor<.f><.cc> 0,limm,limm 0010011011010010F1111111100QQQQQ. */ +{ "bxor", 0x26D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* b_s s10 1111000sssssssss. */ +{ "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }}, + +/* cbflyhf0r a,b,c 00110bbb000110111BBBCCCCCCAAAAAA. */ +{ "cbflyhf0r", 0x301B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cbflyhf0r 0,b,c 00110bbb000110111BBBCCCCCC111110. */ +{ "cbflyhf0r", 0x301B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,c 00110bbb110110111BBBCCCCCC0QQQQQ. */ +{ "cbflyhf0r", 0x30DB8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cbflyhf0r a,b,u6 00110bbb010110111BBBuuuuuuAAAAAA. */ +{ "cbflyhf0r", 0x305B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cbflyhf0r 0,b,u6 00110bbb010110111BBBuuuuuu111110. */ +{ "cbflyhf0r", 0x305B803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,u6 00110bbb110110111BBBuuuuuu1QQQQQ. */ +{ "cbflyhf0r", 0x30DB8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cbflyhf0r b,b,s12 00110bbb100110111BBBssssssSSSSSS. */ +{ "cbflyhf0r", 0x309B8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cbflyhf0r a,limm,c 00110110000110111111CCCCCCAAAAAA. */ +{ "cbflyhf0r", 0x361BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cbflyhf0r a,b,limm 00110bbb000110111BBB111110AAAAAA. */ +{ "cbflyhf0r", 0x301B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cbflyhf0r 0,limm,c 00110110000110111111CCCCCC111110. */ +{ "cbflyhf0r", 0x361BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cbflyhf0r 0,b,limm 00110bbb000110111BBB111110111110. */ +{ "cbflyhf0r", 0x301B8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cbflyhf0r<.cc> b,b,limm 00110bbb110110111BBB1111100QQQQQ. */ +{ "cbflyhf0r", 0x30DB8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cbflyhf0r<.cc> 0,limm,c 00110110110110111111CCCCCC0QQQQQ. */ +{ "cbflyhf0r", 0x36DBF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cbflyhf0r a,limm,u6 00110110010110111111uuuuuuAAAAAA. */ +{ "cbflyhf0r", 0x365BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cbflyhf0r 0,limm,u6 00110110010110111111uuuuuu111110. */ +{ "cbflyhf0r", 0x365BF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cbflyhf0r<.cc> 0,limm,u6 00110110110110111111uuuuuu1QQQQQ. */ +{ "cbflyhf0r", 0x36DBF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cbflyhf0r 0,limm,s12 00110110100110111111ssssssSSSSSS. */ +{ "cbflyhf0r", 0x369BF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cbflyhf0r a,limm,limm 00110110000110111111111110AAAAAA. */ +{ "cbflyhf0r", 0x361BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cbflyhf0r 0,limm,limm 00110110000110111111111110111110. */ +{ "cbflyhf0r", 0x361BFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cbflyhf0r<.cc> 0,limm,limm 001101101101101111111111100QQQQQ. */ +{ "cbflyhf0r", 0x36DBFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cbflyhf1r b,c 00110bbb001011110BBBCCCCCC111001. */ +{ "cbflyhf1r", 0x302F0039, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* cbflyhf1r 0,c 00110110001011110111CCCCCC011001. */ +{ "cbflyhf1r", 0x362F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* cbflyhf1r b,u6 00110bbb011011110BBBuuuuuu011001. */ +{ "cbflyhf1r", 0x306F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* cbflyhf1r 0,u6 00110110011011110111uuuuuu011001. */ +{ "cbflyhf1r", 0x366F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* cbflyhf1r b,limm 00110bbb001011110BBB111110011001. */ +{ "cbflyhf1r", 0x302F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* cbflyhf1r 0,limm 00110110001011110111111110011001. */ +{ "cbflyhf1r", 0x362F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* clamp<.f> a,b,c 00110bbb00101010FBBBCCCCCCAAAAAA. */ +{ "clamp", 0x302A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* clamp<.f><.cc> b,b,c 00110bbb11101010FBBBCCCCCC0QQQQQ. */ +{ "clamp", 0x30EA0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* clamp<.f> a,b,u6 00110bbb01101010FBBBuuuuuuAAAAAA. */ +{ "clamp", 0x306A0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* clamp<.f><.cc> b,b,u6 00110bbb11101010FBBBuuuuuu1QQQQQ. */ +{ "clamp", 0x30EA0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* clamp<.f> b,b,s12 00110bbb10101010FBBBssssssSSSSSS. */ +{ "clamp", 0x30AA0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* clamp<.f> a,limm,c 0011011000101010F111CCCCCCAAAAAA. */ +{ "clamp", 0x362A7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* clamp<.f> a,b,limm 00110bbb00101010FBBB111110AAAAAA. */ +{ "clamp", 0x302A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* clamp<.f><.cc> b,b,limm 00110bbb11101010FBBB1111100QQQQQ. */ +{ "clamp", 0x30EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* clri c 00100111001011110000CCCCCC111111. */ +{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }}, + +/* clri 0 00100111001011110000111110111111. */ +{ "clri", 0x272F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { ZA }, { 0 }}, + +/* clri u6 00100111011011110000uuuuuu111111. */ +{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }}, + +/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */ +{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmacchfr 0,b,c 00110bbb000010011BBBCCCCCC111110. */ +{ "cmacchfr", 0x3009803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmacchfr<.cc> b,b,c 00110bbb110010011BBBCCCCCC0QQQQQ. */ +{ "cmacchfr", 0x30C98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmacchfr a,b,u6 00110bbb010010011BBBuuuuuuAAAAAA. */ +{ "cmacchfr", 0x30498000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmacchfr 0,b,u6 00110bbb010010011BBBuuuuuu111110. */ +{ "cmacchfr", 0x3049803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmacchfr<.cc> b,b,u6 00110bbb110010011BBBuuuuuu1QQQQQ. */ +{ "cmacchfr", 0x30C98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmacchfr b,b,s12 00110bbb100010011BBBssssssSSSSSS. */ +{ "cmacchfr", 0x30898000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmacchfr a,limm,c 00110110000010011111CCCCCCAAAAAA. */ +{ "cmacchfr", 0x3609F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmacchfr a,b,limm 00110bbb000010011BBB111110AAAAAA. */ +{ "cmacchfr", 0x30098F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmacchfr 0,limm,c 00110110000010011111CCCCCC111110. */ +{ "cmacchfr", 0x3609F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmacchfr 0,b,limm 00110bbb000010011BBB111110111110. */ +{ "cmacchfr", 0x30098FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,c 00110bbb110010011BBB1111100QQQQQ. */ +{ "cmacchfr", 0x30C98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmacchfr<.cc> b,b,limm 00110110110010011111CCCCCC0QQQQQ. */ +{ "cmacchfr", 0x36C9F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmacchfr a,limm,u6 00110110010010011111uuuuuuAAAAAA. */ +{ "cmacchfr", 0x3649F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmacchfr 0,limm,u6 00110110010010011111uuuuuu111110. */ +{ "cmacchfr", 0x3649F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,u6 00110110110010011111uuuuuu1QQQQQ. */ +{ "cmacchfr", 0x36C9F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmacchfr 0,limm,s12 00110110100010011111ssssssSSSSSS. */ +{ "cmacchfr", 0x3689F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmacchfr a,limm,limm 00110110000010011111111110AAAAAA. */ +{ "cmacchfr", 0x3609FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmacchfr 0,limm,limm 00110110000010011111111110111110. */ +{ "cmacchfr", 0x3609FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmacchfr<.cc> 0,limm,limm 001101101100100111111111100QQQQQ. */ +{ "cmacchfr", 0x36C9FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmacchnfr a,b,c 00110bbb000010001BBBCCCCCCAAAAAA. */ +{ "cmacchnfr", 0x30088000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmacchnfr 0,b,c 00110bbb000010001BBBCCCCCC111110. */ +{ "cmacchnfr", 0x3008803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmacchnfr<.cc> b,b,c 00110bbb110010001BBBCCCCCC0QQQQQ. */ +{ "cmacchnfr", 0x30C88000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmacchnfr a,b,u6 00110bbb010010001BBBuuuuuuAAAAAA. */ +{ "cmacchnfr", 0x30488000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmacchnfr 0,b,u6 00110bbb010010001BBBuuuuuu111110. */ +{ "cmacchnfr", 0x3048803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmacchnfr<.cc> b,b,u6 00110bbb110010001BBBuuuuuu1QQQQQ. */ +{ "cmacchnfr", 0x30C88020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmacchnfr b,b,s12 00110bbb100010001BBBssssssSSSSSS. */ +{ "cmacchnfr", 0x30888000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmacchnfr a,limm,c 00110110000010001111CCCCCCAAAAAA. */ +{ "cmacchnfr", 0x3608F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmacchnfr a,b,limm 00110bbb000010001BBB111110AAAAAA. */ +{ "cmacchnfr", 0x30088F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmacchnfr 0,limm,c 00110110000010001111CCCCCC111110. */ +{ "cmacchnfr", 0x3608F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmacchnfr 0,b,limm 00110bbb000010001BBB111110111110. */ +{ "cmacchnfr", 0x30088FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,c 00110bbb110010001BBB1111100QQQQQ. */ +{ "cmacchnfr", 0x30C88F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmacchnfr<.cc> b,b,limm 00110110110010001111CCCCCC0QQQQQ. */ +{ "cmacchnfr", 0x36C8F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmacchnfr a,limm,u6 00110110010010001111uuuuuuAAAAAA. */ +{ "cmacchnfr", 0x3648F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmacchnfr 0,limm,u6 00110110010010001111uuuuuu111110. */ +{ "cmacchnfr", 0x3648F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,u6 00110110110010001111uuuuuu1QQQQQ. */ +{ "cmacchnfr", 0x36C8F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmacchnfr 0,limm,s12 00110110100010001111ssssssSSSSSS. */ +{ "cmacchnfr", 0x3688F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmacchnfr a,limm,limm 00110110000010001111111110AAAAAA. */ +{ "cmacchnfr", 0x3608FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmacchnfr 0,limm,limm 00110110000010001111111110111110. */ +{ "cmacchnfr", 0x3608FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmacchnfr<.cc> 0,limm,limm 001101101100100011111111100QQQQQ. */ +{ "cmacchnfr", 0x36C8FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmachfr a,b,c 00110bbb000001111BBBCCCCCCAAAAAA. */ +{ "cmachfr", 0x30078000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmachfr 0,b,c 00110bbb000001111BBBCCCCCC111110. */ +{ "cmachfr", 0x3007803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmachfr<.cc> b,b,c 00110bbb110001111BBBCCCCCC0QQQQQ. */ +{ "cmachfr", 0x30C78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmachfr a,b,u6 00110bbb010001111BBBuuuuuuAAAAAA. */ +{ "cmachfr", 0x30478000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmachfr 0,b,u6 00110bbb010001111BBBuuuuuu111110. */ +{ "cmachfr", 0x3047803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmachfr<.cc> b,b,u6 00110bbb110001111BBBuuuuuu1QQQQQ. */ +{ "cmachfr", 0x30C78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmachfr b,b,s12 00110bbb100001111BBBssssssSSSSSS. */ +{ "cmachfr", 0x30878000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmachfr a,limm,c 00110110000001111111CCCCCCAAAAAA. */ +{ "cmachfr", 0x3607F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmachfr a,b,limm 00110bbb000001111BBB111110AAAAAA. */ +{ "cmachfr", 0x30078F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmachfr 0,limm,c 00110110000001111111CCCCCC111110. */ +{ "cmachfr", 0x3607F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmachfr 0,b,limm 00110bbb000001111BBB111110111110. */ +{ "cmachfr", 0x30078FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmachfr<.cc> 0,limm,c 00110bbb110001111BBB1111100QQQQQ. */ +{ "cmachfr", 0x30C78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmachfr<.cc> b,b,limm 00110110110001111111CCCCCC0QQQQQ. */ +{ "cmachfr", 0x36C7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmachfr a,limm,u6 00110110010001111111uuuuuuAAAAAA. */ +{ "cmachfr", 0x3647F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmachfr 0,limm,u6 00110110010001111111uuuuuu111110. */ +{ "cmachfr", 0x3647F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmachfr<.cc> 0,limm,u6 00110110110001111111uuuuuu1QQQQQ. */ +{ "cmachfr", 0x36C7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmachfr 0,limm,s12 00110110100001111111ssssssSSSSSS. */ +{ "cmachfr", 0x3687F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmachfr a,limm,limm 00110110000001111111111110AAAAAA. */ +{ "cmachfr", 0x3607FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmachfr 0,limm,limm 00110110000001111111111110111110. */ +{ "cmachfr", 0x3607FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmachfr<.cc> 0,limm,limm 001101101100011111111111100QQQQQ. */ +{ "cmachfr", 0x36C7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmachnfr a,b,c 00110bbb000001101BBBCCCCCCAAAAAA. */ +{ "cmachnfr", 0x30068000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmachnfr 0,b,c 00110bbb000001101BBBCCCCCC111110. */ +{ "cmachnfr", 0x3006803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmachnfr<.cc> b,b,c 00110bbb110001101BBBCCCCCC0QQQQQ. */ +{ "cmachnfr", 0x30C68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmachnfr a,b,u6 00110bbb010001101BBBuuuuuuAAAAAA. */ +{ "cmachnfr", 0x30468000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmachnfr 0,b,u6 00110bbb010001101BBBuuuuuu111110. */ +{ "cmachnfr", 0x3046803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmachnfr<.cc> b,b,u6 00110bbb110001101BBBuuuuuu1QQQQQ. */ +{ "cmachnfr", 0x30C68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmachnfr b,b,s12 00110bbb100001101BBBssssssSSSSSS. */ +{ "cmachnfr", 0x30868000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmachnfr a,limm,c 00110110000001101111CCCCCCAAAAAA. */ +{ "cmachnfr", 0x3606F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmachnfr a,b,limm 00110bbb000001101BBB111110AAAAAA. */ +{ "cmachnfr", 0x30068F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmachnfr 0,limm,c 00110110000001101111CCCCCC111110. */ +{ "cmachnfr", 0x3606F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmachnfr 0,b,limm 00110bbb000001101BBB111110111110. */ +{ "cmachnfr", 0x30068FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,c 00110bbb110001101BBB1111100QQQQQ. */ +{ "cmachnfr", 0x30C68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmachnfr<.cc> b,b,limm 00110110110001101111CCCCCC0QQQQQ. */ +{ "cmachnfr", 0x36C6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmachnfr a,limm,u6 00110110010001101111uuuuuuAAAAAA. */ +{ "cmachnfr", 0x3646F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmachnfr 0,limm,u6 00110110010001101111uuuuuu111110. */ +{ "cmachnfr", 0x3646F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,u6 00110110110001101111uuuuuu1QQQQQ. */ +{ "cmachnfr", 0x36C6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmachnfr 0,limm,s12 00110110100001101111ssssssSSSSSS. */ +{ "cmachnfr", 0x3686F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmachnfr a,limm,limm 00110110000001101111111110AAAAAA. */ +{ "cmachnfr", 0x3606FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmachnfr 0,limm,limm 00110110000001101111111110111110. */ +{ "cmachnfr", 0x3606FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmachnfr<.cc> 0,limm,limm 001101101100011011111111100QQQQQ. */ +{ "cmachnfr", 0x36C6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmacrdw<.f> a,b,c 00101bbb00100110FBBBCCCCCCAAAAAA. */ +{ "cmacrdw", 0x28260000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* cmacrdw<.f> 0,b,c 00101bbb00100110FBBBCCCCCC111110. */ +{ "cmacrdw", 0x2826003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* cmacrdw<.f><.cc> b,b,c 00101bbb11100110FBBBCCCCCC0QQQQQ. */ +{ "cmacrdw", 0x28E60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* cmacrdw<.f> a,b,u6 00101bbb01100110FBBBuuuuuuAAAAAA. */ +{ "cmacrdw", 0x28660000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f> 0,b,u6 00101bbb01100110FBBBuuuuuu111110. */ +{ "cmacrdw", 0x2866003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f><.cc> b,b,u6 00101bbb11100110FBBBuuuuuu1QQQQQ. */ +{ "cmacrdw", 0x28E60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* cmacrdw<.f> b,b,s12 00101bbb10100110FBBBssssssSSSSSS. */ +{ "cmacrdw", 0x28A60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* cmacrdw<.f> a,limm,c 0010111000100110F111CCCCCCAAAAAA. */ +{ "cmacrdw", 0x2E267000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* cmacrdw<.f> a,b,limm 00101bbb00100110FBBB111110AAAAAA. */ +{ "cmacrdw", 0x28260F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* cmacrdw<.f> 0,limm,c 0010111000100110F111CCCCCC111110. */ +{ "cmacrdw", 0x2E26703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* cmacrdw<.f> 0,b,limm 00101bbb00100110FBBB111110111110. */ +{ "cmacrdw", 0x28260FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,c 0010111011100110F111CCCCCC0QQQQQ. */ +{ "cmacrdw", 0x2EE67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* cmacrdw<.f><.cc> b,b,limm 00101bbb11100110FBBB1111100QQQQQ. */ +{ "cmacrdw", 0x28E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* cmacrdw<.f> a,limm,u6 0010111001100110F111uuuuuuAAAAAA. */ +{ "cmacrdw", 0x2E667000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f> 0,limm,u6 0010111001100110F111uuuuuu111110. */ +{ "cmacrdw", 0x2E66703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,u6 0010111011100110F111uuuuuu1QQQQQ. */ +{ "cmacrdw", 0x2EE67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* cmacrdw<.f> 0,limm,s12 0010111010100110F111ssssssSSSSSS. */ +{ "cmacrdw", 0x2EA67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* cmacrdw<.f> a,limm,limm 0010111000100110F111111110AAAAAA. */ +{ "cmacrdw", 0x2E267F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* cmacrdw<.f> 0,limm,limm 0010111000100110F111111110111110. */ +{ "cmacrdw", 0x2E267FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* cmacrdw<.f><.cc> 0,limm,limm 0010111011100110F1111111100QQQQQ. */ +{ "cmacrdw", 0x2EE67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* cmp b,c 00100bbb000011001BBBCCCCCCRRRRRR. */ +{ "cmp", 0x200C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, + +/* cmp b,c 00100bbb000011001BBBCCCCCC000000. */ +{ "cmp", 0x200C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { 0 }}, + +/* cmp<.cc> b,c 00100bbb110011001BBBCCCCCC0QQQQQ. */ +{ "cmp", 0x20CC8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_CC }}, + +/* cmp b,u6 00100bbb010011001BBBuuuuuuRRRRRR. */ +{ "cmp", 0x204C8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* cmp b,u6 00100bbb010011001BBBuuuuuu000000. */ +{ "cmp", 0x204C8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* cmp<.cc> b,u6 00100bbb110011001BBBuuuuuu1QQQQQ. */ +{ "cmp", 0x20CC8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* cmp b,s12 00100bbb100011001BBBssssssSSSSSS. */ +{ "cmp", 0x208C8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* cmp limm,c 00100110000011001111CCCCCCRRRRRR. */ +{ "cmp", 0x260CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* cmp b,limm 00100bbb000011001BBB111110RRRRRR. */ +{ "cmp", 0x200C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* cmp limm,c 00100110000011001111CCCCCC000000. */ +{ "cmp", 0x260CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* cmp b,limm 00100bbb000011001BBB111110000000. */ +{ "cmp", 0x200C8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* cmp<.cc> b,limm 00100bbb110011001BBB1111100QQQQQ. */ +{ "cmp", 0x20CC8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_CC }}, + +/* cmp<.cc> limm,c 00100110110011001111CCCCCC0QQQQQ. */ +{ "cmp", 0x26CCF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { C_CC }}, + +/* cmp limm,u6 00100110010011001111uuuuuuRRRRRR. */ +{ "cmp", 0x264CF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* cmp limm,u6 00100110010011001111uuuuuu000000. */ +{ "cmp", 0x264CF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* cmp<.cc> limm,u6 00100110110011001111uuuuuu1QQQQQ. */ +{ "cmp", 0x26CCF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* cmp limm,s12 00100110100011001111ssssssSSSSSS. */ +{ "cmp", 0x268CF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* cmp limm,limm 00100110000011001111111110RRRRRR. */ +{ "cmp", 0x260CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* cmp limm,limm 00100110000011001111111110000000. */ +{ "cmp", 0x260CFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* cmp<.cc> limm,limm 001001101100110011111111100QQQQQ. */ +{ "cmp", 0x26CCFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* cmpychfr a,b,c 00110bbb000001011BBBCCCCCCAAAAAA. */ +{ "cmpychfr", 0x30058000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmpychfr 0,b,c 00110bbb000001011BBBCCCCCC111110. */ +{ "cmpychfr", 0x3005803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmpychfr<.cc> b,b,c 00110bbb110001011BBBCCCCCC0QQQQQ. */ +{ "cmpychfr", 0x30C58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmpychfr a,b,u6 00110bbb010001011BBBuuuuuuAAAAAA. */ +{ "cmpychfr", 0x30458000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmpychfr 0,b,u6 00110bbb010001011BBBuuuuuu111110. */ +{ "cmpychfr", 0x3045803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmpychfr<.cc> b,b,u6 00110bbb110001011BBBuuuuuu1QQQQQ. */ +{ "cmpychfr", 0x30C58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmpychfr b,b,s12 00110bbb100001011BBBssssssSSSSSS. */ +{ "cmpychfr", 0x30858000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmpychfr a,limm,c 00110110000001011111CCCCCCAAAAAA. */ +{ "cmpychfr", 0x3605F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmpychfr a,b,limm 00110bbb000001011BBB111110AAAAAA. */ +{ "cmpychfr", 0x30058F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmpychfr 0,limm,c 00110110000001011111CCCCCC111110. */ +{ "cmpychfr", 0x3605F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmpychfr 0,b,limm 00110bbb000001011BBB111110111110. */ +{ "cmpychfr", 0x30058FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,c 00110bbb110001011BBB1111100QQQQQ. */ +{ "cmpychfr", 0x30C58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmpychfr<.cc> b,b,limm 00110110110001011111CCCCCC0QQQQQ. */ +{ "cmpychfr", 0x36C5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmpychfr a,limm,u6 00110110010001011111uuuuuuAAAAAA. */ +{ "cmpychfr", 0x3645F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpychfr 0,limm,u6 00110110010001011111uuuuuu111110. */ +{ "cmpychfr", 0x3645F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,u6 00110110110001011111uuuuuu1QQQQQ. */ +{ "cmpychfr", 0x36C5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmpychfr 0,limm,s12 00110110100001011111ssssssSSSSSS. */ +{ "cmpychfr", 0x3685F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmpychfr a,limm,limm 00110110000001011111111110AAAAAA. */ +{ "cmpychfr", 0x3605FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmpychfr 0,limm,limm 00110110000001011111111110111110. */ +{ "cmpychfr", 0x3605FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmpychfr<.cc> 0,limm,limm 001101101100010111111111100QQQQQ. */ +{ "cmpychfr", 0x36C5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmpychnfr a,b,c 00110bbb000000101BBBCCCCCCAAAAAA. */ +{ "cmpychnfr", 0x30028000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmpychnfr 0,b,c 00110bbb000000001BBBCCCCCC111110. */ +{ "cmpychnfr", 0x3000803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmpychnfr<.cc> b,b,c 00110bbb110000001BBBCCCCCC0QQQQQ. */ +{ "cmpychnfr", 0x30C08000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmpychnfr a,b,u6 00110bbb010000001BBBuuuuuuAAAAAA. */ +{ "cmpychnfr", 0x30408000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmpychnfr 0,b,u6 00110bbb010000001BBBuuuuuu111110. */ +{ "cmpychnfr", 0x3040803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmpychnfr<.cc> b,b,u6 00110bbb110000001BBBuuuuuu1QQQQQ. */ +{ "cmpychnfr", 0x30C08020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmpychnfr b,b,s12 00110bbb100000001BBBssssssSSSSSS. */ +{ "cmpychnfr", 0x30808000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmpychnfr a,limm,c 00110110000000001111CCCCCCAAAAAA. */ +{ "cmpychnfr", 0x3600F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmpychnfr a,b,limm 00110bbb000000001BBB111110AAAAAA. */ +{ "cmpychnfr", 0x30008F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmpychnfr 0,limm,c 00110110000000001111CCCCCC111110. */ +{ "cmpychnfr", 0x3600F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmpychnfr 0,b,limm 00110bbb000000001BBB111110111110. */ +{ "cmpychnfr", 0x30008FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,c 00110bbb110000001BBB1111100QQQQQ. */ +{ "cmpychnfr", 0x30C08F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmpychnfr<.cc> b,b,limm 00110110110000001111CCCCCC0QQQQQ. */ +{ "cmpychnfr", 0x36C0F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmpychnfr a,limm,u6 00110110010000001111uuuuuuAAAAAA. */ +{ "cmpychnfr", 0x3640F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpychnfr 0,limm,u6 00110110010000001111uuuuuu111110. */ +{ "cmpychnfr", 0x3640F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,u6 00110110110000001111uuuuuu1QQQQQ. */ +{ "cmpychnfr", 0x36C0F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmpychnfr 0,limm,s12 00110110100000001111ssssssSSSSSS. */ +{ "cmpychnfr", 0x3680F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmpychnfr a,limm,limm 00110110000000001111111110AAAAAA. */ +{ "cmpychnfr", 0x3600FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmpychnfr 0,limm,limm 00110110000000001111111110111110. */ +{ "cmpychnfr", 0x3600FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmpychnfr<.cc> 0,limm,limm 001101101100000011111111100QQQQQ. */ +{ "cmpychnfr", 0x36C0FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmpyhfmr a,b,c 00110bbb000110110BBBCCCCCCAAAAAA. */ +{ "cmpyhfmr", 0x301B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmpyhfmr 0,b,c 00110bbb000110110BBBCCCCCC111110. */ +{ "cmpyhfmr", 0x301B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmpyhfmr<.cc> b,b,c 00110bbb110110110BBBCCCCCC0QQQQQ. */ +{ "cmpyhfmr", 0x30DB0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmpyhfmr a,b,u6 00110bbb010110110BBBuuuuuuAAAAAA. */ +{ "cmpyhfmr", 0x305B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhfmr 0,b,u6 00110bbb010110110BBBuuuuuu111110. */ +{ "cmpyhfmr", 0x305B003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhfmr<.cc> b,b,u6 00110bbb110110110BBBuuuuuu1QQQQQ. */ +{ "cmpyhfmr", 0x30DB0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmpyhfmr b,b,s12 00110bbb100110110BBBssssssSSSSSS. */ +{ "cmpyhfmr", 0x309B0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmpyhfmr a,limm,c 00110110000110110111CCCCCCAAAAAA. */ +{ "cmpyhfmr", 0x361B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmpyhfmr a,b,limm 00110bbb000110110BBB111110AAAAAA. */ +{ "cmpyhfmr", 0x301B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmpyhfmr 0,limm,c 00110110000110110111CCCCCC111110. */ +{ "cmpyhfmr", 0x361B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmpyhfmr 0,b,limm 00110bbb000110110BBB111110111110. */ +{ "cmpyhfmr", 0x301B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,c 00110bbb110110110BBB1111100QQQQQ. */ +{ "cmpyhfmr", 0x30DB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmpyhfmr<.cc> b,b,limm 00110110110110110111CCCCCC0QQQQQ. */ +{ "cmpyhfmr", 0x36DB7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmpyhfmr a,limm,u6 00110110010110110111uuuuuuAAAAAA. */ +{ "cmpyhfmr", 0x365B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhfmr 0,limm,u6 00110110010110110111uuuuuu111110. */ +{ "cmpyhfmr", 0x365B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,u6 00110110110110110111uuuuuu1QQQQQ. */ +{ "cmpyhfmr", 0x36DB7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmpyhfmr 0,limm,s12 00110110100110110111ssssssSSSSSS. */ +{ "cmpyhfmr", 0x369B7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmpyhfmr a,limm,limm 00110110000110110111111110AAAAAA. */ +{ "cmpyhfmr", 0x361B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhfmr 0,limm,limm 00110110000110110111111110111110. */ +{ "cmpyhfmr", 0x361B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhfmr<.cc> 0,limm,limm 001101101101101101111111100QQQQQ. */ +{ "cmpyhfmr", 0x36DB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmpyhfr a,b,c 00110bbb000000011BBBCCCCCCAAAAAA. */ +{ "cmpyhfr", 0x30018000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmpyhfr 0,b,c 00110bbb000000011BBBCCCCCC111110. */ +{ "cmpyhfr", 0x3001803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmpyhfr<.cc> b,b,c 00110bbb110000011BBBCCCCCC0QQQQQ. */ +{ "cmpyhfr", 0x30C18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmpyhfr a,b,u6 00110bbb010000011BBBuuuuuuAAAAAA. */ +{ "cmpyhfr", 0x30418000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhfr 0,b,u6 00110bbb010000011BBBuuuuuu111110. */ +{ "cmpyhfr", 0x3041803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhfr<.cc> b,b,u6 00110bbb110000011BBBuuuuuu1QQQQQ. */ +{ "cmpyhfr", 0x30C18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmpyhfr b,b,s12 00110bbb100000011BBBssssssSSSSSS. */ +{ "cmpyhfr", 0x30818000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmpyhfr a,limm,c 00110110000000011111CCCCCCAAAAAA. */ +{ "cmpyhfr", 0x3601F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmpyhfr a,b,limm 00110bbb000000011BBB111110AAAAAA. */ +{ "cmpyhfr", 0x30018F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmpyhfr 0,limm,c 00110110000000011111CCCCCC111110. */ +{ "cmpyhfr", 0x3601F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmpyhfr 0,b,limm 00110bbb000000011BBB111110111110. */ +{ "cmpyhfr", 0x30018FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,c 00110bbb110000011BBB1111100QQQQQ. */ +{ "cmpyhfr", 0x30C18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmpyhfr<.cc> b,b,limm 00110110110000011111CCCCCC0QQQQQ. */ +{ "cmpyhfr", 0x36C1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmpyhfr a,limm,u6 00110110010000011111uuuuuuAAAAAA. */ +{ "cmpyhfr", 0x3641F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhfr 0,limm,u6 00110110010000011111uuuuuu111110. */ +{ "cmpyhfr", 0x3641F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,u6 00110110110000011111uuuuuu1QQQQQ. */ +{ "cmpyhfr", 0x36C1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmpyhfr 0,limm,s12 00110110100000011111ssssssSSSSSS. */ +{ "cmpyhfr", 0x3681F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmpyhfr a,limm,limm 00110110000000011111111110AAAAAA. */ +{ "cmpyhfr", 0x3601FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhfr 0,limm,limm 00110110000000011111111110111110. */ +{ "cmpyhfr", 0x3601FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhfr<.cc> 0,limm,limm 001101101100000111111111100QQQQQ. */ +{ "cmpyhfr", 0x36C1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmpyhnfr a,b,c 00110bbb000000001BBBCCCCCCAAAAAA. */ +{ "cmpyhnfr", 0x30008000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* cmpyhnfr 0,b,c 00110bbb000000101BBBCCCCCC111110. */ +{ "cmpyhnfr", 0x3002803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* cmpyhnfr<.cc> b,b,c 00110bbb110000101BBBCCCCCC0QQQQQ. */ +{ "cmpyhnfr", 0x30C28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* cmpyhnfr a,b,u6 00110bbb010000101BBBuuuuuuAAAAAA. */ +{ "cmpyhnfr", 0x30428000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhnfr 0,b,u6 00110bbb010000101BBBuuuuuu111110. */ +{ "cmpyhnfr", 0x3042803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* cmpyhnfr<.cc> b,b,u6 00110bbb110000101BBBuuuuuu1QQQQQ. */ +{ "cmpyhnfr", 0x30C28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* cmpyhnfr b,b,s12 00110bbb100000101BBBssssssSSSSSS. */ +{ "cmpyhnfr", 0x30828000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* cmpyhnfr a,limm,c 00110110000000101111CCCCCCAAAAAA. */ +{ "cmpyhnfr", 0x3602F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* cmpyhnfr a,b,limm 00110bbb000000101BBB111110AAAAAA. */ +{ "cmpyhnfr", 0x30028F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* cmpyhnfr 0,limm,c 00110110000000101111CCCCCC111110. */ +{ "cmpyhnfr", 0x3602F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* cmpyhnfr 0,b,limm 00110bbb000000101BBB111110111110. */ +{ "cmpyhnfr", 0x30028FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,c 00110bbb110000101BBB1111100QQQQQ. */ +{ "cmpyhnfr", 0x30C28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* cmpyhnfr<.cc> b,b,limm 00110110110000101111CCCCCC0QQQQQ. */ +{ "cmpyhnfr", 0x36C2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* cmpyhnfr a,limm,u6 00110110010000101111uuuuuuAAAAAA. */ +{ "cmpyhnfr", 0x3642F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhnfr 0,limm,u6 00110110010000101111uuuuuu111110. */ +{ "cmpyhnfr", 0x3642F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,u6 00110110110000101111uuuuuu1QQQQQ. */ +{ "cmpyhnfr", 0x36C2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* cmpyhnfr 0,limm,s12 00110110100000101111ssssssSSSSSS. */ +{ "cmpyhnfr", 0x3682F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* cmpyhnfr a,limm,limm 00110110000000101111111110AAAAAA. */ +{ "cmpyhnfr", 0x3602FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhnfr 0,limm,limm 00110110000000101111111110111110. */ +{ "cmpyhnfr", 0x3602FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* cmpyhnfr<.cc> 0,limm,limm 001101101100001011111111100QQQQQ. */ +{ "cmpyhnfr", 0x36C2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* cmp_s b,h 01110bbbhhh10HHH. */ +{ "cmp_s", 0x00007010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, R6H }, { 0 }}, + +/* cmp_s b,h 01110bbbhhh100HH. */ +{ "cmp_s", 0x00007010, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RH_S }, { 0 }}, + +/* cmp_s h,s3 01110ssshhh101HH. */ +{ "cmp_s", 0x00007014, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RH_S, SIMM3_5_S }, { 0 }}, + +/* cmp_s b,u7 11100bbb1uuuuuuu. */ +{ "cmp_s", 0x0000E080, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, UIMM7_9_S }, { 0 }}, + +/* cmp_s b,limm 01110bbb11010111. */ +{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, LIMM_S }, { 0 }}, + +/* cmp_s b,limm 01110bbb11010011. */ +{ "cmp_s", 0x000070D3, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, LIMM_S }, { 0 }}, + +/* cmp_s limm,s3 01110sss11010111. */ +{ "cmp_s", 0x000070D7, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM_S, SIMM3_5_S }, { 0 }}, + +/* crc<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ +{ "crc", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* crc<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ +{ "crc", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* crc<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "crc", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* crc<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ +{ "crc", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* crc<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ +{ "crc", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* crc<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "crc", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* crc<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ +{ "crc", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* crc<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ +{ "crc", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* crc<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ +{ "crc", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* crc<.f> 0,limm,c 0010111000101100F111CCCCCC111110. */ +{ "crc", 0x2E2C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* crc<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ +{ "crc", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* crc<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ +{ "crc", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* crc<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ +{ "crc", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* crc<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ +{ "crc", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* crc<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ +{ "crc", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* crc<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ +{ "crc", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* crc<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ +{ "crc", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* crc<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ +{ "crc", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* crc<.f> 0,limm,limm 0010111000101100F111111110111110. */ +{ "crc", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* crc<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ +{ "crc", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ +{ "daddh11", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh11<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ +{ "daddh11", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh11<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "daddh11", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,c 00110bbb00110100FBBBCCCCCCAAAAAA. */ +{ "daddh11", 0x30340000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh11<.f> 0,b,c 00110bbb00110100FBBBCCCCCC111110. */ +{ "daddh11", 0x3034003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh11<.f><.cc> b,b,c 00110bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "daddh11", 0x30F40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ +{ "daddh11", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ +{ "daddh11", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "daddh11", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> a,b,u6 00110bbb01110100FBBBuuuuuuAAAAAA. */ +{ "daddh11", 0x30740000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,b,u6 00110bbb01110100FBBBuuuuuu111110. */ +{ "daddh11", 0x3074003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> b,b,u6 00110bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "daddh11", 0x30F40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ +{ "daddh11", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh11<.f> b,b,s12 00110bbb10110100FBBBssssssSSSSSS. */ +{ "daddh11", 0x30B40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh11<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ +{ "daddh11", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh11<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ +{ "daddh11", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh11<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ +{ "daddh11", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh11<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ +{ "daddh11", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,c 0011011011001100F111CCCCCC0QQQQQ. */ +{ "daddh11", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh11<.f><.cc> b,b,limm 00110bbb11001100FBBB1111100QQQQQ. */ +{ "daddh11", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,c 0011011000110100F111CCCCCCAAAAAA. */ +{ "daddh11", 0x36347000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh11<.f> a,b,limm 00110bbb00110100FBBB111110AAAAAA. */ +{ "daddh11", 0x30340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh11<.f> 0,limm,c 0011011000110100F111CCCCCC111110. */ +{ "daddh11", 0x3634703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh11<.f> 0,b,limm 00110bbb00110100FBBB111110111110. */ +{ "daddh11", 0x30340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,c 0011011011110100F111CCCCCC0QQQQQ. */ +{ "daddh11", 0x36F47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh11<.f><.cc> b,b,limm 00110bbb11110100FBBB1111100QQQQQ. */ +{ "daddh11", 0x30F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ +{ "daddh11", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ +{ "daddh11", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ +{ "daddh11", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,u6 0011011001110100F111uuuuuuAAAAAA. */ +{ "daddh11", 0x36747000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,u6 0011011001110100F111uuuuuu111110. */ +{ "daddh11", 0x3674703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,u6 0011011011110100F111uuuuuu1QQQQQ. */ +{ "daddh11", 0x36F47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh11<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ +{ "daddh11", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh11<.f> 0,limm,s12 0011011010110100F111ssssssSSSSSS. */ +{ "daddh11", 0x36B47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh11<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ +{ "daddh11", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh11<.f> 0,limm,limm 0011011000001100F111111110111110. */ +{ "daddh11", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ +{ "daddh11", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh11<.f> a,limm,limm 0011011000110100F111111110AAAAAA. */ +{ "daddh11", 0x36347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh11<.f> 0,limm,limm 0011011000110100F111111110111110. */ +{ "daddh11", 0x36347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh11<.f><.cc> 0,limm,limm 0011011011110100F1111111100QQQQQ. */ +{ "daddh11", 0x36F47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ +{ "daddh12", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh12<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ +{ "daddh12", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh12<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "daddh12", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,c 00110bbb00110101FBBBCCCCCCAAAAAA. */ +{ "daddh12", 0x30350000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh12<.f> 0,b,c 00110bbb00110101FBBBCCCCCC111110. */ +{ "daddh12", 0x3035003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh12<.f><.cc> b,b,c 00110bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "daddh12", 0x30F50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ +{ "daddh12", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ +{ "daddh12", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "daddh12", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> a,b,u6 00110bbb01110101FBBBuuuuuuAAAAAA. */ +{ "daddh12", 0x30750000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,b,u6 00110bbb01110101FBBBuuuuuu111110. */ +{ "daddh12", 0x3075003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> b,b,u6 00110bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "daddh12", 0x30F50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ +{ "daddh12", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh12<.f> b,b,s12 00110bbb10110101FBBBssssssSSSSSS. */ +{ "daddh12", 0x30B50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh12<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ +{ "daddh12", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh12<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ +{ "daddh12", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh12<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ +{ "daddh12", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh12<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ +{ "daddh12", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,c 0011011011001101F111CCCCCC0QQQQQ. */ +{ "daddh12", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh12<.f><.cc> b,b,limm 00110bbb11001101FBBB1111100QQQQQ. */ +{ "daddh12", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,c 0011011000110101F111CCCCCCAAAAAA. */ +{ "daddh12", 0x36357000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh12<.f> a,b,limm 00110bbb00110101FBBB111110AAAAAA. */ +{ "daddh12", 0x30350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh12<.f> 0,limm,c 0011011000110101F111CCCCCC111110. */ +{ "daddh12", 0x3635703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh12<.f> 0,b,limm 00110bbb00110101FBBB111110111110. */ +{ "daddh12", 0x30350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,c 0011011011110101F111CCCCCC0QQQQQ. */ +{ "daddh12", 0x36F57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh12<.f><.cc> b,b,limm 00110bbb11110101FBBB1111100QQQQQ. */ +{ "daddh12", 0x30F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ +{ "daddh12", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ +{ "daddh12", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ +{ "daddh12", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,u6 0011011001110101F111uuuuuuAAAAAA. */ +{ "daddh12", 0x36757000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,u6 0011011001110101F111uuuuuu111110. */ +{ "daddh12", 0x3675703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,u6 0011011011110101F111uuuuuu1QQQQQ. */ +{ "daddh12", 0x36F57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh12<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ +{ "daddh12", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh12<.f> 0,limm,s12 0011011010110101F111ssssssSSSSSS. */ +{ "daddh12", 0x36B57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh12<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ +{ "daddh12", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh12<.f> 0,limm,limm 0011011000001101F111111110111110. */ +{ "daddh12", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ +{ "daddh12", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh12<.f> a,limm,limm 0011011000110101F111111110AAAAAA. */ +{ "daddh12", 0x36357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh12<.f> 0,limm,limm 0011011000110101F111111110111110. */ +{ "daddh12", 0x36357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh12<.f><.cc> 0,limm,limm 0011011011110101F1111111100QQQQQ. */ +{ "daddh12", 0x36F57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ +{ "daddh21", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh21<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ +{ "daddh21", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh21<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "daddh21", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,c 00110bbb00110110FBBBCCCCCCAAAAAA. */ +{ "daddh21", 0x30360000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh21<.f> 0,b,c 00110bbb00110110FBBBCCCCCC111110. */ +{ "daddh21", 0x3036003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh21<.f><.cc> b,b,c 00110bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "daddh21", 0x30F60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ +{ "daddh21", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ +{ "daddh21", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "daddh21", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> a,b,u6 00110bbb01110110FBBBuuuuuuAAAAAA. */ +{ "daddh21", 0x30760000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,b,u6 00110bbb01110110FBBBuuuuuu111110. */ +{ "daddh21", 0x3076003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> b,b,u6 00110bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "daddh21", 0x30F60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ +{ "daddh21", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh21<.f> b,b,s12 00110bbb10110110FBBBssssssSSSSSS. */ +{ "daddh21", 0x30B60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh21<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ +{ "daddh21", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh21<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ +{ "daddh21", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh21<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ +{ "daddh21", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh21<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ +{ "daddh21", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,c 0011011011001110F111CCCCCC0QQQQQ. */ +{ "daddh21", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh21<.f><.cc> b,b,limm 00110bbb11001110FBBB1111100QQQQQ. */ +{ "daddh21", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,c 0011011000110110F111CCCCCCAAAAAA. */ +{ "daddh21", 0x36367000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh21<.f> a,b,limm 00110bbb00110110FBBB111110AAAAAA. */ +{ "daddh21", 0x30360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh21<.f> 0,limm,c 0011011000110110F111CCCCCC111110. */ +{ "daddh21", 0x3636703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh21<.f> 0,b,limm 00110bbb00110110FBBB111110111110. */ +{ "daddh21", 0x30360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,c 0011011011110110F111CCCCCC0QQQQQ. */ +{ "daddh21", 0x36F67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh21<.f><.cc> b,b,limm 00110bbb11110110FBBB1111100QQQQQ. */ +{ "daddh21", 0x30F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ +{ "daddh21", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ +{ "daddh21", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ +{ "daddh21", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,u6 0011011001110110F111uuuuuuAAAAAA. */ +{ "daddh21", 0x36767000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,u6 0011011001110110F111uuuuuu111110. */ +{ "daddh21", 0x3676703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,u6 0011011011110110F111uuuuuu1QQQQQ. */ +{ "daddh21", 0x36F67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh21<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ +{ "daddh21", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh21<.f> 0,limm,s12 0011011010110110F111ssssssSSSSSS. */ +{ "daddh21", 0x36B67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh21<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ +{ "daddh21", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh21<.f> 0,limm,limm 0011011000001110F111111110111110. */ +{ "daddh21", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ +{ "daddh21", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh21<.f> a,limm,limm 0011011000110110F111111110AAAAAA. */ +{ "daddh21", 0x36367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh21<.f> 0,limm,limm 0011011000110110F111111110111110. */ +{ "daddh21", 0x36367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh21<.f><.cc> 0,limm,limm 0011011011110110F1111111100QQQQQ. */ +{ "daddh21", 0x36F67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ +{ "daddh22", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh22<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ +{ "daddh22", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh22<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "daddh22", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,c 00110bbb00110111FBBBCCCCCCAAAAAA. */ +{ "daddh22", 0x30370000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* daddh22<.f> 0,b,c 00110bbb00110111FBBBCCCCCC111110. */ +{ "daddh22", 0x3037003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* daddh22<.f><.cc> b,b,c 00110bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "daddh22", 0x30F70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ +{ "daddh22", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ +{ "daddh22", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "daddh22", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> a,b,u6 00110bbb01110111FBBBuuuuuuAAAAAA. */ +{ "daddh22", 0x30770000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,b,u6 00110bbb01110111FBBBuuuuuu111110. */ +{ "daddh22", 0x3077003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> b,b,u6 00110bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "daddh22", 0x30F70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ +{ "daddh22", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh22<.f> b,b,s12 00110bbb10110111FBBBssssssSSSSSS. */ +{ "daddh22", 0x30B70000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* daddh22<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ +{ "daddh22", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh22<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ +{ "daddh22", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh22<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ +{ "daddh22", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh22<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ +{ "daddh22", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,c 0011011011001111F111CCCCCC0QQQQQ. */ +{ "daddh22", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh22<.f><.cc> b,b,limm 00110bbb11001111FBBB1111100QQQQQ. */ +{ "daddh22", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,c 0011011000110111F111CCCCCCAAAAAA. */ +{ "daddh22", 0x36377000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* daddh22<.f> a,b,limm 00110bbb00110111FBBB111110AAAAAA. */ +{ "daddh22", 0x30370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* daddh22<.f> 0,limm,c 0011011000110111F111CCCCCC111110. */ +{ "daddh22", 0x3637703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* daddh22<.f> 0,b,limm 00110bbb00110111FBBB111110111110. */ +{ "daddh22", 0x30370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,c 0011011011110111F111CCCCCC0QQQQQ. */ +{ "daddh22", 0x36F77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* daddh22<.f><.cc> b,b,limm 00110bbb11110111FBBB1111100QQQQQ. */ +{ "daddh22", 0x30F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ +{ "daddh22", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ +{ "daddh22", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ +{ "daddh22", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,u6 0011011001110111F111uuuuuuAAAAAA. */ +{ "daddh22", 0x36777000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,u6 0011011001110111F111uuuuuu111110. */ +{ "daddh22", 0x3677703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,u6 0011011011110111F111uuuuuu1QQQQQ. */ +{ "daddh22", 0x36F77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* daddh22<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ +{ "daddh22", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh22<.f> 0,limm,s12 0011011010110111F111ssssssSSSSSS. */ +{ "daddh22", 0x36B77000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* daddh22<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ +{ "daddh22", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh22<.f> 0,limm,limm 0011011000001111F111111110111110. */ +{ "daddh22", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ +{ "daddh22", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* daddh22<.f> a,limm,limm 0011011000110111F111111110AAAAAA. */ +{ "daddh22", 0x36377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* daddh22<.f> 0,limm,limm 0011011000110111F111111110111110. */ +{ "daddh22", 0x36377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* daddh22<.f><.cc> 0,limm,limm 0011011011110111F1111111100QQQQQ. */ +{ "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ +{ "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dexcl1<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ +{ "dexcl1", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "dexcl1", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,c 00110bbb00111100FBBBCCCCCCAAAAAA. */ +{ "dexcl1", 0x303C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dexcl1<.f> 0,b,c 00110bbb00111100FBBBCCCCCC111110. */ +{ "dexcl1", 0x303C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,c 00110bbb11111100FBBBCCCCCC0QQQQQ. */ +{ "dexcl1", 0x30FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ +{ "dexcl1", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ +{ "dexcl1", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "dexcl1", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> a,b,u6 00110bbb01111100FBBBuuuuuuAAAAAA. */ +{ "dexcl1", 0x307C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,b,u6 00110bbb01111100FBBBuuuuuu111110. */ +{ "dexcl1", 0x307C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> b,b,u6 00110bbb11111100FBBBuuuuuu1QQQQQ. */ +{ "dexcl1", 0x30FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ +{ "dexcl1", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> b,b,s12 00110bbb10111100FBBBssssssSSSSSS. */ +{ "dexcl1", 0x30BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ +{ "dexcl1", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dexcl1<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ +{ "dexcl1", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dexcl1<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ +{ "dexcl1", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dexcl1<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ +{ "dexcl1", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ +{ "dexcl1", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dexcl1<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ +{ "dexcl1", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,c 0011011000111100F111CCCCCCAAAAAA. */ +{ "dexcl1", 0x363C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dexcl1<.f> a,b,limm 00110bbb00111100FBBB111110AAAAAA. */ +{ "dexcl1", 0x303C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dexcl1<.f> 0,limm,c 0011011000111100F111CCCCCC111110. */ +{ "dexcl1", 0x363C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dexcl1<.f> 0,b,limm 00110bbb00111100FBBB111110111110. */ +{ "dexcl1", 0x303C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,c 0011011011111100F111CCCCCC0QQQQQ. */ +{ "dexcl1", 0x36FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dexcl1<.f><.cc> b,b,limm 00110bbb11111100FBBB1111100QQQQQ. */ +{ "dexcl1", 0x30FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ +{ "dexcl1", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ +{ "dexcl1", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ +{ "dexcl1", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,u6 0011011001111100F111uuuuuuAAAAAA. */ +{ "dexcl1", 0x367C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,u6 0011011001111100F111uuuuuu111110. */ +{ "dexcl1", 0x367C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,u6 0011011011111100F111uuuuuu1QQQQQ. */ +{ "dexcl1", 0x36FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl1<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ +{ "dexcl1", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> 0,limm,s12 0011011010111100F111ssssssSSSSSS. */ +{ "dexcl1", 0x36BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dexcl1<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ +{ "dexcl1", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl1<.f> 0,limm,limm 0011011000011000F111111110111110. */ +{ "dexcl1", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ +{ "dexcl1", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dexcl1<.f> a,limm,limm 0011011000111100F111111110AAAAAA. */ +{ "dexcl1", 0x363C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl1<.f> 0,limm,limm 0011011000111100F111111110111110. */ +{ "dexcl1", 0x363C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl1<.f><.cc> 0,limm,limm 0011011011111100F1111111100QQQQQ. */ +{ "dexcl1", 0x36FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ +{ "dexcl2", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dexcl2<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ +{ "dexcl2", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "dexcl2", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,c 00110bbb00111101FBBBCCCCCCAAAAAA. */ +{ "dexcl2", 0x303D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dexcl2<.f> 0,b,c 00110bbb00111101FBBBCCCCCC111110. */ +{ "dexcl2", 0x303D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,c 00110bbb11111101FBBBCCCCCC0QQQQQ. */ +{ "dexcl2", 0x30FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ +{ "dexcl2", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ +{ "dexcl2", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "dexcl2", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> a,b,u6 00110bbb01111101FBBBuuuuuuAAAAAA. */ +{ "dexcl2", 0x307D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,b,u6 00110bbb01111101FBBBuuuuuu111110. */ +{ "dexcl2", 0x307D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> b,b,u6 00110bbb11111101FBBBuuuuuu1QQQQQ. */ +{ "dexcl2", 0x30FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ +{ "dexcl2", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> b,b,s12 00110bbb10111101FBBBssssssSSSSSS. */ +{ "dexcl2", 0x30BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ +{ "dexcl2", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dexcl2<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ +{ "dexcl2", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dexcl2<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ +{ "dexcl2", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dexcl2<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ +{ "dexcl2", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ +{ "dexcl2", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dexcl2<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ +{ "dexcl2", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,c 0011011000111101F111CCCCCCAAAAAA. */ +{ "dexcl2", 0x363D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dexcl2<.f> a,b,limm 00110bbb00111101FBBB111110AAAAAA. */ +{ "dexcl2", 0x303D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dexcl2<.f> 0,limm,c 0011011000111101F111CCCCCC111110. */ +{ "dexcl2", 0x363D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dexcl2<.f> 0,b,limm 00110bbb00111101FBBB111110111110. */ +{ "dexcl2", 0x303D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,c 0011011011111101F111CCCCCC0QQQQQ. */ +{ "dexcl2", 0x36FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dexcl2<.f><.cc> b,b,limm 00110bbb11111101FBBB1111100QQQQQ. */ +{ "dexcl2", 0x30FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ +{ "dexcl2", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ +{ "dexcl2", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ +{ "dexcl2", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,u6 0011011001111101F111uuuuuuAAAAAA. */ +{ "dexcl2", 0x367D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,u6 0011011001111101F111uuuuuu111110. */ +{ "dexcl2", 0x367D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,u6 0011011011111101F111uuuuuu1QQQQQ. */ +{ "dexcl2", 0x36FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dexcl2<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ +{ "dexcl2", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> 0,limm,s12 0011011010111101F111ssssssSSSSSS. */ +{ "dexcl2", 0x36BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dexcl2<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ +{ "dexcl2", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl2<.f> 0,limm,limm 0011011000011001F111111110111110. */ +{ "dexcl2", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ +{ "dexcl2", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dexcl2<.f> a,limm,limm 0011011000111101F111111110AAAAAA. */ +{ "dexcl2", 0x363D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl2<.f> 0,limm,limm 0011011000111101F111111110111110. */ +{ "dexcl2", 0x363D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dexcl2<.f><.cc> 0,limm,limm 0011011011111101F1111111100QQQQQ. */ +{ "dexcl2", 0x36FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* div<.f> a,b,c 00101bbb00000100FBBBCCCCCCAAAAAA. */ +{ "div", 0x28040000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }}, + +/* div<.f> 0,b,c 00101bbb00000100FBBBCCCCCC111110. */ +{ "div", 0x2804003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }}, + +/* div<.f><.cc> b,b,c 00101bbb11000100FBBBCCCCCC0QQQQQ. */ +{ "div", 0x28C40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* div<.f> a,b,u6 00101bbb01000100FBBBuuuuuuAAAAAA. */ +{ "div", 0x28440000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }}, + +/* div<.f> 0,b,u6 00101bbb01000100FBBBuuuuuu111110. */ +{ "div", 0x2844003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* div<.f><.cc> b,b,u6 00101bbb11000100FBBBuuuuuu1QQQQQ. */ +{ "div", 0x28C40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* div<.f> b,b,s12 00101bbb10000100FBBBssssssSSSSSS. */ +{ "div", 0x28840000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* div<.f> a,limm,c 0010111000000100F111CCCCCCAAAAAA. */ +{ "div", 0x2E047000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }}, + +/* div<.f> a,b,limm 00101bbb00000100FBBB111110AAAAAA. */ +{ "div", 0x28040F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }}, + +/* div<.f> 0,limm,c 0010111000000100F111CCCCCC111110. */ +{ "div", 0x2E04703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }}, + +/* div<.f> 0,b,limm 00101bbb00000100FBBB111110111110. */ +{ "div", 0x28040FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }}, + +/* div<.f><.cc> b,b,limm 00101bbb11000100FBBB1111100QQQQQ. */ +{ "div", 0x28C40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* div<.f><.cc> 0,limm,c 0010111011000100F111CCCCCC0QQQQQ. */ +{ "div", 0x2EC47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* div<.f> a,limm,u6 0010111001000100F111uuuuuuAAAAAA. */ +{ "div", 0x2E447000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* div<.f> 0,limm,u6 0010111001000100F111uuuuuu111110. */ +{ "div", 0x2E44703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* div<.f><.cc> 0,limm,u6 0010111011000100F111uuuuuu1QQQQQ. */ +{ "div", 0x2EC47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* div<.f> 0,limm,s12 0010111010000100F111ssssssSSSSSS. */ +{ "div", 0x2E847000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* div<.f> a,limm,limm 0010111000000100F111111110AAAAAA. */ +{ "div", 0x2E047F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }}, + +/* div<.f> 0,limm,limm 0010111000000100F111111110111110. */ +{ "div", 0x2E047FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* div<.f><.cc> 0,limm,limm 0010111011000100F1111111100QQQQQ. */ +{ "div", 0x2EC47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* divacc c 00101011001011110000CCCCCC111111. */ +{ "divacc", 0x2B2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }}, + +/* divacc u6 00101011011011110000uuuuuu111111. */ +{ "divacc", 0x2B6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }}, + +/* divaw<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ +{ "divaw", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* divaw<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ +{ "divaw", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* divaw<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "divaw", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* divaw<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ +{ "divaw", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* divaw<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ +{ "divaw", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* divaw<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "divaw", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* divaw<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ +{ "divaw", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* divaw<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ +{ "divaw", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* divaw<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ +{ "divaw", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* divaw<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ +{ "divaw", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* divaw<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ +{ "divaw", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* divaw<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ +{ "divaw", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* divaw<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ +{ "divaw", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* divaw<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ +{ "divaw", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* divaw<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ +{ "divaw", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* divaw<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ +{ "divaw", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* divaw<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ +{ "divaw", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* divaw<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ +{ "divaw", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* divaw<.f> 0,limm,limm 0010111000001000F111111110111110. */ +{ "divaw", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* divaw<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ +{ "divaw", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* divu<.f> a,b,c 00101bbb00000101FBBBCCCCCCAAAAAA. */ +{ "divu", 0x28050000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }}, + +/* divu<.f> 0,b,c 00101bbb00000101FBBBCCCCCC111110. */ +{ "divu", 0x2805003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }}, + +/* divu<.f><.cc> b,b,c 00101bbb11000101FBBBCCCCCC0QQQQQ. */ +{ "divu", 0x28C50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* divu<.f> a,b,u6 00101bbb01000101FBBBuuuuuuAAAAAA. */ +{ "divu", 0x28450000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }}, + +/* divu<.f> 0,b,u6 00101bbb01000101FBBBuuuuuu111110. */ +{ "divu", 0x2845003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* divu<.f><.cc> b,b,u6 00101bbb11000101FBBBuuuuuu1QQQQQ. */ +{ "divu", 0x28C50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* divu<.f> b,b,s12 00101bbb10000101FBBBssssssSSSSSS. */ +{ "divu", 0x28850000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* divu<.f> a,limm,c 0010111000000101F111CCCCCCAAAAAA. */ +{ "divu", 0x2E057000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }}, + +/* divu<.f> a,b,limm 00101bbb00000101FBBB111110AAAAAA. */ +{ "divu", 0x28050F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }}, + +/* divu<.f> 0,limm,c 0010111000000101F111CCCCCC111110. */ +{ "divu", 0x2E05703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }}, + +/* divu<.f> 0,b,limm 00101bbb00000101FBBB111110111110. */ +{ "divu", 0x28050FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }}, + +/* divu<.f><.cc> b,b,limm 00101bbb11000101FBBB1111100QQQQQ. */ +{ "divu", 0x28C50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* divu<.f><.cc> 0,limm,c 0010111011000101F111CCCCCC0QQQQQ. */ +{ "divu", 0x2EC57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* divu<.f> a,limm,u6 0010111001000101F111uuuuuuAAAAAA. */ +{ "divu", 0x2E457000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* divu<.f> 0,limm,u6 0010111001000101F111uuuuuu111110. */ +{ "divu", 0x2E45703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* divu<.f><.cc> 0,limm,u6 0010111011000101F111uuuuuu1QQQQQ. */ +{ "divu", 0x2EC57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* divu<.f> 0,limm,s12 0010111010000101F111ssssssSSSSSS. */ +{ "divu", 0x2E857000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* divu<.f> a,limm,limm 0010111000000101F111111110AAAAAA. */ +{ "divu", 0x2E057F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }}, + +/* divu<.f> 0,limm,limm 0010111000000101F111111110111110. */ +{ "divu", 0x2E057FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* divu<.f><.cc> 0,limm,limm 0010111011000101F1111111100QQQQQ. */ +{ "divu", 0x2EC57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmach<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ +{ "dmach", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* dmach<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ +{ "dmach", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* dmach<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "dmach", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmach<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ +{ "dmach", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmach<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ +{ "dmach", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmach<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "dmach", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmach<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ +{ "dmach", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmach<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ +{ "dmach", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* dmach<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ +{ "dmach", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* dmach<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ +{ "dmach", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* dmach<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ +{ "dmach", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* dmach<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ +{ "dmach", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmach<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ +{ "dmach", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmach<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ +{ "dmach", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmach<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ +{ "dmach", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmach<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ +{ "dmach", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmach<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ +{ "dmach", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmach<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ +{ "dmach", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmach<.f> 0,limm,limm 0010111000010010F111111110111110. */ +{ "dmach", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmach<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ +{ "dmach", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmachbl<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA. */ +{ "dmachbl", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmachbl<.f> 0,b,c 00110bbb00011000FBBBCCCCCC111110. */ +{ "dmachbl", 0x3018003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,c 00110bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "dmachbl", 0x30D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmachbl<.f> a,b,u6 00110bbb01011000FBBBuuuuuuAAAAAA. */ +{ "dmachbl", 0x30580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmachbl<.f> 0,b,u6 00110bbb01011000FBBBuuuuuu111110. */ +{ "dmachbl", 0x3058003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,u6 00110bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "dmachbl", 0x30D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbl<.f> b,b,s12 00110bbb10011000FBBBssssssSSSSSS. */ +{ "dmachbl", 0x30980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmachbl<.f> a,limm,c 0011011000011000F111CCCCCCAAAAAA. */ +{ "dmachbl", 0x36187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmachbl<.f> a,b,limm 00110bbb00011000FBBB111110AAAAAA. */ +{ "dmachbl", 0x30180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmachbl<.f> 0,limm,c 0011011000011000F111CCCCCC111110. */ +{ "dmachbl", 0x3618703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmachbl<.f> 0,b,limm 00110bbb00011000FBBB111110111110. */ +{ "dmachbl", 0x30180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmachbl<.f><.cc> b,b,limm 00110bbb11011000FBBB1111100QQQQQ. */ +{ "dmachbl", 0x30D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmachbl<.f><.cc> 0,limm,c 0011011011011000F111CCCCCC0QQQQQ. */ +{ "dmachbl", 0x36D87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmachbl<.f> a,limm,u6 0011011001011000F111uuuuuuAAAAAA. */ +{ "dmachbl", 0x36587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachbl<.f> 0,limm,u6 0011011001011000F111uuuuuu111110. */ +{ "dmachbl", 0x3658703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachbl<.f><.cc> 0,limm,u6 0011011011011000F111uuuuuu1QQQQQ. */ +{ "dmachbl", 0x36D87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbl<.f> 0,limm,s12 0011011010011000F111ssssssSSSSSS. */ +{ "dmachbl", 0x36987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmachbl<.f> a,limm,limm 0011011000011000F111111110AAAAAA. */ +{ "dmachbl", 0x36187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmachbl<.f> 0,limm,limm 0011011000011000F111111110111110. */ +{ "dmachbl", 0x36187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmachbl<.f><.cc> 0,limm,limm 0011011011011000F1111111100QQQQQ. */ +{ "dmachbl", 0x36D87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmachbm<.f> a,b,c 00110bbb00011001FBBBCCCCCCAAAAAA. */ +{ "dmachbm", 0x30190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmachbm<.f> 0,b,c 00110bbb00011001FBBBCCCCCC111110. */ +{ "dmachbm", 0x3019003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,c 00110bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "dmachbm", 0x30D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmachbm<.f> a,b,u6 00110bbb01011001FBBBuuuuuuAAAAAA. */ +{ "dmachbm", 0x30590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmachbm<.f> 0,b,u6 00110bbb01011001FBBBuuuuuu111110. */ +{ "dmachbm", 0x3059003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,u6 00110bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "dmachbm", 0x30D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbm<.f> b,b,s12 00110bbb10011001FBBBssssssSSSSSS. */ +{ "dmachbm", 0x30990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmachbm<.f> a,limm,c 0011011000011001F111CCCCCCAAAAAA. */ +{ "dmachbm", 0x36197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmachbm<.f> a,b,limm 00110bbb00011001FBBB111110AAAAAA. */ +{ "dmachbm", 0x30190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmachbm<.f> 0,limm,c 0011011000011001F111CCCCCC111110. */ +{ "dmachbm", 0x3619703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmachbm<.f> 0,b,limm 00110bbb00011001FBBB111110111110. */ +{ "dmachbm", 0x30190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmachbm<.f><.cc> b,b,limm 00110bbb11011001FBBB1111100QQQQQ. */ +{ "dmachbm", 0x30D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmachbm<.f><.cc> 0,limm,c 0011011011011001F111CCCCCC0QQQQQ. */ +{ "dmachbm", 0x36D97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmachbm<.f> a,limm,u6 0011011001011001F111uuuuuuAAAAAA. */ +{ "dmachbm", 0x36597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachbm<.f> 0,limm,u6 0011011001011001F111uuuuuu111110. */ +{ "dmachbm", 0x3659703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachbm<.f><.cc> 0,limm,u6 0011011011011001F111uuuuuu1QQQQQ. */ +{ "dmachbm", 0x36D97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachbm<.f> 0,limm,s12 0011011010011001F111ssssssSSSSSS. */ +{ "dmachbm", 0x36997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmachbm<.f> a,limm,limm 0011011000011001F111111110AAAAAA. */ +{ "dmachbm", 0x36197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmachbm<.f> 0,limm,limm 0011011000011001F111111110111110. */ +{ "dmachbm", 0x36197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmachbm<.f><.cc> 0,limm,limm 0011011011011001F1111111100QQQQQ. */ +{ "dmachbm", 0x36D97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmachf<.f> a,b,c 00101bbb00101100FBBBCCCCCCAAAAAA. */ +{ "dmachf", 0x282C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmachf<.f> 0,b,c 00101bbb00101100FBBBCCCCCC111110. */ +{ "dmachf", 0x282C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmachf<.f><.cc> b,b,c 00101bbb11101100FBBBCCCCCC0QQQQQ. */ +{ "dmachf", 0x28EC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmachf<.f> a,b,u6 00101bbb01101100FBBBuuuuuuAAAAAA. */ +{ "dmachf", 0x286C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmachf<.f> 0,b,u6 00101bbb01101100FBBBuuuuuu111110. */ +{ "dmachf", 0x286C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmachf<.f><.cc> b,b,u6 00101bbb11101100FBBBuuuuuu1QQQQQ. */ +{ "dmachf", 0x28EC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachf<.f> b,b,s12 00101bbb10101100FBBBssssssSSSSSS. */ +{ "dmachf", 0x28AC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmachf<.f> a,limm,c 0010111000101100F111CCCCCCAAAAAA. */ +{ "dmachf", 0x2E2C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmachf<.f> a,b,limm 00101bbb00101100FBBB111110AAAAAA. */ +{ "dmachf", 0x282C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmachf<.f> 0,limm,c 0010111001101100F111CCCCCC111110. */ +{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmachf<.f> 0,b,limm 00101bbb00101100FBBB111110111110. */ +{ "dmachf", 0x282C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmachf<.f><.cc> b,b,limm 00101bbb11101100FBBB1111100QQQQQ. */ +{ "dmachf", 0x28EC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmachf<.f><.cc> 0,limm,c 0010111011101100F111CCCCCC0QQQQQ. */ +{ "dmachf", 0x2EEC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmachf<.f> a,limm,u6 0010111001101100F111uuuuuuAAAAAA. */ +{ "dmachf", 0x2E6C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachf<.f> 0,limm,u6 0010111001101100F111uuuuuu111110. */ +{ "dmachf", 0x2E6C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachf<.f><.cc> 0,limm,u6 0010111011101100F111uuuuuu1QQQQQ. */ +{ "dmachf", 0x2EEC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachf<.f> 0,limm,s12 0010111010101100F111ssssssSSSSSS. */ +{ "dmachf", 0x2EAC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmachf<.f> a,limm,limm 0010111000101100F111111110AAAAAA. */ +{ "dmachf", 0x2E2C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmachf<.f> 0,limm,limm 0010111000101100F111111110111110. */ +{ "dmachf", 0x2E2C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmachf<.f><.cc> 0,limm,limm 0010111011101100F1111111100QQQQQ. */ +{ "dmachf", 0x2EEC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmachfr<.f> a,b,c 00101bbb00101101FBBBCCCCCCAAAAAA. */ +{ "dmachfr", 0x282D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmachfr<.f> 0,b,c 00101bbb00101101FBBBCCCCCC111110. */ +{ "dmachfr", 0x282D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,c 00101bbb11101101FBBBCCCCCC0QQQQQ. */ +{ "dmachfr", 0x28ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmachfr<.f> a,b,u6 00101bbb01101101FBBBuuuuuuAAAAAA. */ +{ "dmachfr", 0x286D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmachfr<.f> 0,b,u6 00101bbb01101101FBBBuuuuuu111110. */ +{ "dmachfr", 0x286D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,u6 00101bbb11101101FBBBuuuuuu1QQQQQ. */ +{ "dmachfr", 0x28ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachfr<.f> b,b,s12 00101bbb10101101FBBBssssssSSSSSS. */ +{ "dmachfr", 0x28AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmachfr<.f> a,limm,c 0010111000101101F111CCCCCCAAAAAA. */ +{ "dmachfr", 0x2E2D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmachfr<.f> a,b,limm 00101bbb00101101FBBB111110AAAAAA. */ +{ "dmachfr", 0x282D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmachfr<.f> 0,limm,c 0010111001101101F111CCCCCC111110. */ +{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmachfr<.f> 0,b,limm 00101bbb00101101FBBB111110111110. */ +{ "dmachfr", 0x282D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmachfr<.f><.cc> b,b,limm 00101bbb11101101FBBB1111100QQQQQ. */ +{ "dmachfr", 0x28ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmachfr<.f><.cc> 0,limm,c 0010111011101101F111CCCCCC0QQQQQ. */ +{ "dmachfr", 0x2EED7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmachfr<.f> a,limm,u6 0010111001101101F111uuuuuuAAAAAA. */ +{ "dmachfr", 0x2E6D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachfr<.f> 0,limm,u6 0010111001101101F111uuuuuu111110. */ +{ "dmachfr", 0x2E6D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachfr<.f><.cc> 0,limm,u6 0010111011101101F111uuuuuu1QQQQQ. */ +{ "dmachfr", 0x2EED7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachfr<.f> 0,limm,s12 0010111010101101F111ssssssSSSSSS. */ +{ "dmachfr", 0x2EAD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmachfr<.f> a,limm,limm 0010111000101101F111111110AAAAAA. */ +{ "dmachfr", 0x2E2D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmachfr<.f> 0,limm,limm 0010111000101101F111111110111110. */ +{ "dmachfr", 0x2E2D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmachfr<.f><.cc> 0,limm,limm 0010111011101101F1111111100QQQQQ. */ +{ "dmachfr", 0x2EED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmachu<.f> a,b,c 00101bbb00010011FBBBCCCCCCAAAAAA. */ +{ "dmachu", 0x28130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* dmachu<.f> 0,b,c 00101bbb00010011FBBBCCCCCC111110. */ +{ "dmachu", 0x2813003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* dmachu<.f><.cc> b,b,c 00101bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "dmachu", 0x28D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmachu<.f> a,b,u6 00101bbb01010011FBBBuuuuuuAAAAAA. */ +{ "dmachu", 0x28530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmachu<.f> 0,b,u6 00101bbb01010011FBBBuuuuuu111110. */ +{ "dmachu", 0x2853003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmachu<.f><.cc> b,b,u6 00101bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "dmachu", 0x28D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachu<.f> b,b,s12 00101bbb10010011FBBBssssssSSSSSS. */ +{ "dmachu", 0x28930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmachu<.f> a,limm,c 0010111000010011F111CCCCCCAAAAAA. */ +{ "dmachu", 0x2E137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* dmachu<.f> a,b,limm 00101bbb00010011FBBB111110AAAAAA. */ +{ "dmachu", 0x28130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* dmachu<.f> 0,limm,c 0010111000010011F111CCCCCC111110. */ +{ "dmachu", 0x2E13703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* dmachu<.f> 0,b,limm 00101bbb00010011FBBB111110111110. */ +{ "dmachu", 0x28130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* dmachu<.f><.cc> b,b,limm 00101bbb11010011FBBB1111100QQQQQ. */ +{ "dmachu", 0x28D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmachu<.f><.cc> 0,limm,c 0010111011010011F111CCCCCC0QQQQQ. */ +{ "dmachu", 0x2ED37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmachu<.f> a,limm,u6 0010111001010011F111uuuuuuAAAAAA. */ +{ "dmachu", 0x2E537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachu<.f> 0,limm,u6 0010111001010011F111uuuuuu111110. */ +{ "dmachu", 0x2E53703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmachu<.f><.cc> 0,limm,u6 0010111011010011F111uuuuuu1QQQQQ. */ +{ "dmachu", 0x2ED37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmachu<.f> 0,limm,s12 0010111010010011F111ssssssSSSSSS. */ +{ "dmachu", 0x2E937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmachu<.f> a,limm,limm 0010111000010011F111111110AAAAAA. */ +{ "dmachu", 0x2E137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmachu<.f> 0,limm,limm 0010111000010011F111111110111110. */ +{ "dmachu", 0x2E137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmachu<.f><.cc> 0,limm,limm 0010111011010011F1111111100QQQQQ. */ +{ "dmachu", 0x2ED37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmacpf<.f> a,b,c 00101bbb00111011FBBBCCCCCCAAAAAA. */ +{ "dmacpf", 0x283B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmacpf<.f><.cc> b,b,c 00101bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "dmacpf", 0x28FB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmacpf<.f> 0,b,c 00101bbb00111011FBBBCCCCCC111110. */ +{ "dmacpf", 0x283B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmacpf<.f> a,b,limm 00101bbb00111011FBBB111110AAAAAA. */ +{ "dmacpf", 0x283B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmacpf<.f><.cc> b,b,limm 00101bbb11111011FBBB1111100QQQQQ. */ +{ "dmacpf", 0x28FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmacwh<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ +{ "dmacwh", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* dmacwh<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ +{ "dmacwh", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "dmacwh", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmacwh<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ +{ "dmacwh", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmacwh<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ +{ "dmacwh", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "dmacwh", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwh<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ +{ "dmacwh", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmacwh<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ +{ "dmacwh", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* dmacwh<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ +{ "dmacwh", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* dmacwh<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ +{ "dmacwh", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* dmacwh<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ +{ "dmacwh", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* dmacwh<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ +{ "dmacwh", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmacwh<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ +{ "dmacwh", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmacwh<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ +{ "dmacwh", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmacwh<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ +{ "dmacwh", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmacwh<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ +{ "dmacwh", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwh<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ +{ "dmacwh", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmacwh<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ +{ "dmacwh", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmacwh<.f> 0,limm,limm 0010111000110110F111111110111110. */ +{ "dmacwh", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmacwh<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ +{ "dmacwh", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmacwhu<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ +{ "dmacwhu", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* dmacwhu<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ +{ "dmacwhu", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "dmacwhu", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmacwhu<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ +{ "dmacwhu", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ +{ "dmacwhu", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "dmacwhu", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhu<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ +{ "dmacwhu", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmacwhu<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ +{ "dmacwhu", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* dmacwhu<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ +{ "dmacwhu", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* dmacwhu<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ +{ "dmacwhu", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* dmacwhu<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ +{ "dmacwhu", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* dmacwhu<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ +{ "dmacwhu", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmacwhu<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ +{ "dmacwhu", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmacwhu<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ +{ "dmacwhu", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ +{ "dmacwhu", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmacwhu<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ +{ "dmacwhu", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmacwhu<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ +{ "dmacwhu", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmacwhu<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ +{ "dmacwhu", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmacwhu<.f> 0,limm,limm 0010111000110111F111111110111110. */ +{ "dmacwhu", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmacwhu<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ +{ "dmacwhu", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmb u3 00100011011011110001RRRuuu111111. */ +{ "dmb", 0x236F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM3_23 }, { 0 }}, + +/* dmpyh<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ +{ "dmpyh", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* dmpyh<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ +{ "dmpyh", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "dmpyh", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyh<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ +{ "dmpyh", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyh<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ +{ "dmpyh", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "dmpyh", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyh<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ +{ "dmpyh", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyh<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ +{ "dmpyh", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* dmpyh<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ +{ "dmpyh", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* dmpyh<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ +{ "dmpyh", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyh<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ +{ "dmpyh", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyh<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ +{ "dmpyh", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyh<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ +{ "dmpyh", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyh<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ +{ "dmpyh", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyh<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ +{ "dmpyh", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyh<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ +{ "dmpyh", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyh<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ +{ "dmpyh", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyh<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ +{ "dmpyh", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyh<.f> 0,limm,limm 0010111000010000F111111110111110. */ +{ "dmpyh", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyh<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ +{ "dmpyh", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ +{ "dmpyhbl", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmpyhbl<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ +{ "dmpyhbl", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "dmpyhbl", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ +{ "dmpyhbl", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ +{ "dmpyhbl", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "dmpyhbl", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbl<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ +{ "dmpyhbl", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhbl<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ +{ "dmpyhbl", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhbl<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ +{ "dmpyhbl", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ +{ "dmpyhbl", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhbl<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ +{ "dmpyhbl", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhbl<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ +{ "dmpyhbl", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhbl<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ +{ "dmpyhbl", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhbl<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ +{ "dmpyhbl", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ +{ "dmpyhbl", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhbl<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ +{ "dmpyhbl", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbl<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ +{ "dmpyhbl", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhbl<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ +{ "dmpyhbl", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhbl<.f> 0,limm,limm 0011011000010110F111111110111110. */ +{ "dmpyhbl", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhbl<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ +{ "dmpyhbl", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ +{ "dmpyhbm", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmpyhbm<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ +{ "dmpyhbm", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "dmpyhbm", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ +{ "dmpyhbm", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ +{ "dmpyhbm", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "dmpyhbm", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbm<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ +{ "dmpyhbm", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhbm<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ +{ "dmpyhbm", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhbm<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ +{ "dmpyhbm", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ +{ "dmpyhbm", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhbm<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ +{ "dmpyhbm", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhbm<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ +{ "dmpyhbm", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhbm<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ +{ "dmpyhbm", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhbm<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ +{ "dmpyhbm", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ +{ "dmpyhbm", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhbm<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ +{ "dmpyhbm", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhbm<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ +{ "dmpyhbm", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhbm<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ +{ "dmpyhbm", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhbm<.f> 0,limm,limm 0011011000010111F111111110111110. */ +{ "dmpyhbm", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhbm<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ +{ "dmpyhbm", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,b,c 00101bbb00101010FBBBCCCCCCAAAAAA. */ +{ "dmpyhf", 0x282A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmpyhf<.f> 0,b,c 00101bbb00101010FBBBCCCCCC111110. */ +{ "dmpyhf", 0x282A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,c 00101bbb11101010FBBBCCCCCC0QQQQQ. */ +{ "dmpyhf", 0x28EA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,b,u6 00101bbb01101010FBBBuuuuuuAAAAAA. */ +{ "dmpyhf", 0x286A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f> 0,b,u6 00101bbb01101010FBBBuuuuuu111110. */ +{ "dmpyhf", 0x286A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,u6 00101bbb11101010FBBBuuuuuu1QQQQQ. */ +{ "dmpyhf", 0x28EA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhf<.f> b,b,s12 00101bbb10101010FBBBssssssSSSSSS. */ +{ "dmpyhf", 0x28AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhf<.f> a,limm,c 0010111000101010F111CCCCCCAAAAAA. */ +{ "dmpyhf", 0x2E2A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhf<.f> a,b,limm 00101bbb00101010FBBB111110AAAAAA. */ +{ "dmpyhf", 0x282A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhf<.f> 0,limm,c 0010111001101010F111CCCCCC111110. */ +{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhf<.f> 0,b,limm 00101bbb00101010FBBB111110111110. */ +{ "dmpyhf", 0x282A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhf<.f><.cc> b,b,limm 00101bbb11101010FBBB1111100QQQQQ. */ +{ "dmpyhf", 0x28EA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhf<.f><.cc> 0,limm,c 0010111011101010F111CCCCCC0QQQQQ. */ +{ "dmpyhf", 0x2EEA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhf<.f> a,limm,u6 0010111001101010F111uuuuuuAAAAAA. */ +{ "dmpyhf", 0x2E6A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f> 0,limm,u6 0010111001101010F111uuuuuu111110. */ +{ "dmpyhf", 0x2E6A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhf<.f><.cc> 0,limm,u6 0010111011101010F111uuuuuu1QQQQQ. */ +{ "dmpyhf", 0x2EEA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhf<.f> 0,limm,s12 0010111010101010F111ssssssSSSSSS. */ +{ "dmpyhf", 0x2EAA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhf<.f> a,limm,limm 0010111000101010F111111110AAAAAA. */ +{ "dmpyhf", 0x2E2A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhf<.f> 0,limm,limm 0010111000101010F111111110111110. */ +{ "dmpyhf", 0x2E2A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhf<.f><.cc> 0,limm,limm 0010111011101010F1111111100QQQQQ. */ +{ "dmpyhf", 0x2EEA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ +{ "dmpyhfr", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmpyhfr<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ +{ "dmpyhfr", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ +{ "dmpyhfr", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ +{ "dmpyhfr", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ +{ "dmpyhfr", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ +{ "dmpyhfr", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhfr<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ +{ "dmpyhfr", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhfr<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ +{ "dmpyhfr", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhfr<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ +{ "dmpyhfr", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,c 0010111001101011F111CCCCCC111110. */ +{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhfr<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ +{ "dmpyhfr", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhfr<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ +{ "dmpyhfr", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhfr<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ +{ "dmpyhfr", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhfr<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ +{ "dmpyhfr", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ +{ "dmpyhfr", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhfr<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ +{ "dmpyhfr", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhfr<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ +{ "dmpyhfr", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhfr<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ +{ "dmpyhfr", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhfr<.f> 0,limm,limm 0010111000101011F111111110111110. */ +{ "dmpyhfr", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhfr<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ +{ "dmpyhfr", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ +{ "dmpyhu", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* dmpyhu<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ +{ "dmpyhu", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "dmpyhu", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ +{ "dmpyhu", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ +{ "dmpyhu", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "dmpyhu", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhu<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ +{ "dmpyhu", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhu<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ +{ "dmpyhu", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhu<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ +{ "dmpyhu", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhu<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ +{ "dmpyhu", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhu<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ +{ "dmpyhu", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhu<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ +{ "dmpyhu", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhu<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ +{ "dmpyhu", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhu<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ +{ "dmpyhu", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ +{ "dmpyhu", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhu<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ +{ "dmpyhu", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhu<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ +{ "dmpyhu", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhu<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ +{ "dmpyhu", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhu<.f> 0,limm,limm 0010111000010001F111111110111110. */ +{ "dmpyhu", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhu<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ +{ "dmpyhu", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,b,c 00101bbb00101000FBBBCCCCCCAAAAAA. */ +{ "dmpyhwf", 0x28280000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmpyhwf<.f> 0,b,c 00101bbb00101000FBBBCCCCCC111110. */ +{ "dmpyhwf", 0x2828003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,c 00101bbb11101000FBBBCCCCCC0QQQQQ. */ +{ "dmpyhwf", 0x28E80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,b,u6 00101bbb01101000FBBBuuuuuuAAAAAA. */ +{ "dmpyhwf", 0x28680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f> 0,b,u6 00101bbb01101000FBBBuuuuuu111110. */ +{ "dmpyhwf", 0x2868003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,u6 00101bbb11101000FBBBuuuuuu1QQQQQ. */ +{ "dmpyhwf", 0x28E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhwf<.f> b,b,s12 00101bbb10101000FBBBssssssSSSSSS. */ +{ "dmpyhwf", 0x28A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpyhwf<.f> a,limm,c 0010111000101000F111CCCCCCAAAAAA. */ +{ "dmpyhwf", 0x2E287000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* dmpyhwf<.f> a,b,limm 00101bbb00101000FBBB111110AAAAAA. */ +{ "dmpyhwf", 0x28280F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,c 0010111001101000F111CCCCCC111110. */ +{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* dmpyhwf<.f> 0,b,limm 00101bbb00101000FBBB111110111110. */ +{ "dmpyhwf", 0x28280FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* dmpyhwf<.f><.cc> b,b,limm 00101bbb11101000FBBB1111100QQQQQ. */ +{ "dmpyhwf", 0x28E80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpyhwf<.f><.cc> 0,limm,c 0010111011101000F111CCCCCC0QQQQQ. */ +{ "dmpyhwf", 0x2EE87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpyhwf<.f> a,limm,u6 0010111001101000F111uuuuuuAAAAAA. */ +{ "dmpyhwf", 0x2E687000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,u6 0010111001101000F111uuuuuu111110. */ +{ "dmpyhwf", 0x2E68703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpyhwf<.f><.cc> 0,limm,u6 0010111011101000F111uuuuuu1QQQQQ. */ +{ "dmpyhwf", 0x2EE87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpyhwf<.f> 0,limm,s12 0010111010101000F111ssssssSSSSSS. */ +{ "dmpyhwf", 0x2EA87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpyhwf<.f> a,limm,limm 0010111000101000F111111110AAAAAA. */ +{ "dmpyhwf", 0x2E287F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhwf<.f> 0,limm,limm 0010111000101000F111111110111110. */ +{ "dmpyhwf", 0x2E287FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpyhwf<.f><.cc> 0,limm,limm 0010111011101000F1111111100QQQQQ. */ +{ "dmpyhwf", 0x2EE87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpywh<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ +{ "dmpywh", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* dmpywh<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ +{ "dmpywh", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "dmpywh", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpywh<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ +{ "dmpywh", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpywh<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ +{ "dmpywh", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "dmpywh", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywh<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ +{ "dmpywh", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpywh<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ +{ "dmpywh", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* dmpywh<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ +{ "dmpywh", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* dmpywh<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ +{ "dmpywh", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* dmpywh<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ +{ "dmpywh", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* dmpywh<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ +{ "dmpywh", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpywh<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ +{ "dmpywh", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpywh<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ +{ "dmpywh", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpywh<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ +{ "dmpywh", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpywh<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ +{ "dmpywh", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywh<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ +{ "dmpywh", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpywh<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ +{ "dmpywh", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpywh<.f> 0,limm,limm 0010111000110010F111111110111110. */ +{ "dmpywh", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpywh<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ +{ "dmpywh", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ +{ "dmpywhu", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* dmpywhu<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ +{ "dmpywhu", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "dmpywhu", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ +{ "dmpywhu", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ +{ "dmpywhu", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "dmpywhu", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhu<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ +{ "dmpywhu", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmpywhu<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ +{ "dmpywhu", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* dmpywhu<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ +{ "dmpywhu", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* dmpywhu<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ +{ "dmpywhu", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* dmpywhu<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ +{ "dmpywhu", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* dmpywhu<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ +{ "dmpywhu", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmpywhu<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ +{ "dmpywhu", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmpywhu<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ +{ "dmpywhu", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ +{ "dmpywhu", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmpywhu<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ +{ "dmpywhu", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmpywhu<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ +{ "dmpywhu", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmpywhu<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ +{ "dmpywhu", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmpywhu<.f> 0,limm,limm 0010111000110011F111111110111110. */ +{ "dmpywhu", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmpywhu<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ +{ "dmpywhu", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,c 00110bbb00001000FBBBCCCCCCAAAAAA. */ +{ "dmulh11", 0x30080000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh11<.f> 0,b,c 00110bbb00001000FBBBCCCCCC111110. */ +{ "dmulh11", 0x3008003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,c 00110bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "dmulh11", 0x30C80000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,c 00110bbb00110000FBBBCCCCCCAAAAAA. */ +{ "dmulh11", 0x30300000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh11<.f> 0,b,c 00110bbb00110000FBBBCCCCCC111110. */ +{ "dmulh11", 0x3030003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,c 00110bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "dmulh11", 0x30F00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,u6 00110bbb01001000FBBBuuuuuuAAAAAA. */ +{ "dmulh11", 0x30480000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,b,u6 00110bbb01001000FBBBuuuuuu111110. */ +{ "dmulh11", 0x3048003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,u6 00110bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "dmulh11", 0x30C80020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> a,b,u6 00110bbb01110000FBBBuuuuuuAAAAAA. */ +{ "dmulh11", 0x30700000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,b,u6 00110bbb01110000FBBBuuuuuu111110. */ +{ "dmulh11", 0x3070003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> b,b,u6 00110bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "dmulh11", 0x30F00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> b,b,s12 00110bbb10001000FBBBssssssSSSSSS. */ +{ "dmulh11", 0x30880000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> b,b,s12 00110bbb10110000FBBBssssssSSSSSS. */ +{ "dmulh11", 0x30B00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> a,limm,c 0011011000001000F111CCCCCCAAAAAA. */ +{ "dmulh11", 0x36087000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh11<.f> a,b,limm 00110bbb00001000FBBB111110AAAAAA. */ +{ "dmulh11", 0x30080F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh11<.f> 0,limm,c 0011011000001000F111CCCCCC111110. */ +{ "dmulh11", 0x3608703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh11<.f> 0,b,limm 00110bbb00001000FBBB111110111110. */ +{ "dmulh11", 0x30080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,c 0011011011001000F111CCCCCC0QQQQQ. */ +{ "dmulh11", 0x36C87000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh11<.f><.cc> b,b,limm 00110bbb11001000FBBB1111100QQQQQ. */ +{ "dmulh11", 0x30C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,c 0011011000110000F111CCCCCCAAAAAA. */ +{ "dmulh11", 0x36307000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh11<.f> a,b,limm 00110bbb00110000FBBB111110AAAAAA. */ +{ "dmulh11", 0x30300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh11<.f> 0,limm,c 0011011000110000F111CCCCCC111110. */ +{ "dmulh11", 0x3630703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh11<.f> 0,b,limm 00110bbb00110000FBBB111110111110. */ +{ "dmulh11", 0x30300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,c 0011011011110000F111CCCCCC0QQQQQ. */ +{ "dmulh11", 0x36F07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh11<.f><.cc> b,b,limm 00110bbb11110000FBBB1111100QQQQQ. */ +{ "dmulh11", 0x30F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,u6 0011011001001000F111uuuuuuAAAAAA. */ +{ "dmulh11", 0x36487000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,u6 0011011001001000F111uuuuuu111110. */ +{ "dmulh11", 0x3648703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,u6 0011011011001000F111uuuuuu1QQQQQ. */ +{ "dmulh11", 0x36C87020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,u6 0011011001110000F111uuuuuuAAAAAA. */ +{ "dmulh11", 0x36707000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,u6 0011011001110000F111uuuuuu111110. */ +{ "dmulh11", 0x3670703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,u6 0011011011110000F111uuuuuu1QQQQQ. */ +{ "dmulh11", 0x36F07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh11<.f> 0,limm,s12 0011011010001000F111ssssssSSSSSS. */ +{ "dmulh11", 0x36887000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> 0,limm,s12 0011011010110000F111ssssssSSSSSS. */ +{ "dmulh11", 0x36B07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh11<.f> a,limm,limm 0011011000001000F111111110AAAAAA. */ +{ "dmulh11", 0x36087F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh11<.f> 0,limm,limm 0011011000001000F111111110111110. */ +{ "dmulh11", 0x36087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,limm 0011011011001000F1111111100QQQQQ. */ +{ "dmulh11", 0x36C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh11<.f> a,limm,limm 0011011000110000F111111110AAAAAA. */ +{ "dmulh11", 0x36307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh11<.f> 0,limm,limm 0011011000110000F111111110111110. */ +{ "dmulh11", 0x36307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh11<.f><.cc> 0,limm,limm 0011011011110000F1111111100QQQQQ. */ +{ "dmulh11", 0x36F07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,c 00110bbb00001001FBBBCCCCCCAAAAAA. */ +{ "dmulh12", 0x30090000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh12<.f> 0,b,c 00110bbb00001001FBBBCCCCCC111110. */ +{ "dmulh12", 0x3009003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,c 00110bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "dmulh12", 0x30C90000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,c 00110bbb00110001FBBBCCCCCCAAAAAA. */ +{ "dmulh12", 0x30310000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh12<.f> 0,b,c 00110bbb00110001FBBBCCCCCC111110. */ +{ "dmulh12", 0x3031003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,c 00110bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "dmulh12", 0x30F10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,u6 00110bbb01001001FBBBuuuuuuAAAAAA. */ +{ "dmulh12", 0x30490000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,b,u6 00110bbb01001001FBBBuuuuuu111110. */ +{ "dmulh12", 0x3049003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,u6 00110bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "dmulh12", 0x30C90020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> a,b,u6 00110bbb01110001FBBBuuuuuuAAAAAA. */ +{ "dmulh12", 0x30710000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,b,u6 00110bbb01110001FBBBuuuuuu111110. */ +{ "dmulh12", 0x3071003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> b,b,u6 00110bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "dmulh12", 0x30F10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> b,b,s12 00110bbb10001001FBBBssssssSSSSSS. */ +{ "dmulh12", 0x30890000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> b,b,s12 00110bbb10110001FBBBssssssSSSSSS. */ +{ "dmulh12", 0x30B10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> a,limm,c 0011011000001001F111CCCCCCAAAAAA. */ +{ "dmulh12", 0x36097000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh12<.f> a,b,limm 00110bbb00001001FBBB111110AAAAAA. */ +{ "dmulh12", 0x30090F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh12<.f> 0,limm,c 0011011000001001F111CCCCCC111110. */ +{ "dmulh12", 0x3609703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh12<.f> 0,b,limm 00110bbb00001001FBBB111110111110. */ +{ "dmulh12", 0x30090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,c 0011011011001001F111CCCCCC0QQQQQ. */ +{ "dmulh12", 0x36C97000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh12<.f><.cc> b,b,limm 00110bbb11001001FBBB1111100QQQQQ. */ +{ "dmulh12", 0x30C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,c 0011011000110001F111CCCCCCAAAAAA. */ +{ "dmulh12", 0x36317000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh12<.f> a,b,limm 00110bbb00110001FBBB111110AAAAAA. */ +{ "dmulh12", 0x30310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh12<.f> 0,limm,c 0011011000110001F111CCCCCC111110. */ +{ "dmulh12", 0x3631703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh12<.f> 0,b,limm 00110bbb00110001FBBB111110111110. */ +{ "dmulh12", 0x30310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,c 0011011011110001F111CCCCCC0QQQQQ. */ +{ "dmulh12", 0x36F17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh12<.f><.cc> b,b,limm 00110bbb11110001FBBB1111100QQQQQ. */ +{ "dmulh12", 0x30F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,u6 0011011001001001F111uuuuuuAAAAAA. */ +{ "dmulh12", 0x36497000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,u6 0011011001001001F111uuuuuu111110. */ +{ "dmulh12", 0x3649703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,u6 0011011011001001F111uuuuuu1QQQQQ. */ +{ "dmulh12", 0x36C97020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,u6 0011011001110001F111uuuuuuAAAAAA. */ +{ "dmulh12", 0x36717000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,u6 0011011001110001F111uuuuuu111110. */ +{ "dmulh12", 0x3671703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,u6 0011011011110001F111uuuuuu1QQQQQ. */ +{ "dmulh12", 0x36F17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh12<.f> 0,limm,s12 0011011010001001F111ssssssSSSSSS. */ +{ "dmulh12", 0x36897000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> 0,limm,s12 0011011010110001F111ssssssSSSSSS. */ +{ "dmulh12", 0x36B17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh12<.f> a,limm,limm 0011011000001001F111111110AAAAAA. */ +{ "dmulh12", 0x36097F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh12<.f> 0,limm,limm 0011011000001001F111111110111110. */ +{ "dmulh12", 0x36097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,limm 0011011011001001F1111111100QQQQQ. */ +{ "dmulh12", 0x36C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh12<.f> a,limm,limm 0011011000110001F111111110AAAAAA. */ +{ "dmulh12", 0x36317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh12<.f> 0,limm,limm 0011011000110001F111111110111110. */ +{ "dmulh12", 0x36317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh12<.f><.cc> 0,limm,limm 0011011011110001F1111111100QQQQQ. */ +{ "dmulh12", 0x36F17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ +{ "dmulh21", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh21<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ +{ "dmulh21", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "dmulh21", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,c 00110bbb00110010FBBBCCCCCCAAAAAA. */ +{ "dmulh21", 0x30320000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh21<.f> 0,b,c 00110bbb00110010FBBBCCCCCC111110. */ +{ "dmulh21", 0x3032003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,c 00110bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "dmulh21", 0x30F20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ +{ "dmulh21", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ +{ "dmulh21", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "dmulh21", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> a,b,u6 00110bbb01110010FBBBuuuuuuAAAAAA. */ +{ "dmulh21", 0x30720000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,b,u6 00110bbb01110010FBBBuuuuuu111110. */ +{ "dmulh21", 0x3072003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> b,b,u6 00110bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "dmulh21", 0x30F20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ +{ "dmulh21", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> b,b,s12 00110bbb10110010FBBBssssssSSSSSS. */ +{ "dmulh21", 0x30B20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ +{ "dmulh21", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh21<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ +{ "dmulh21", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh21<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ +{ "dmulh21", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh21<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ +{ "dmulh21", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ +{ "dmulh21", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh21<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ +{ "dmulh21", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,c 0011011000110010F111CCCCCCAAAAAA. */ +{ "dmulh21", 0x36327000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh21<.f> a,b,limm 00110bbb00110010FBBB111110AAAAAA. */ +{ "dmulh21", 0x30320F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh21<.f> 0,limm,c 0011011000110010F111CCCCCC111110. */ +{ "dmulh21", 0x3632703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh21<.f> 0,b,limm 00110bbb00110010FBBB111110111110. */ +{ "dmulh21", 0x30320FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,c 0011011011110010F111CCCCCC0QQQQQ. */ +{ "dmulh21", 0x36F27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh21<.f><.cc> b,b,limm 00110bbb11110010FBBB1111100QQQQQ. */ +{ "dmulh21", 0x30F20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ +{ "dmulh21", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ +{ "dmulh21", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ +{ "dmulh21", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,u6 0011011001110010F111uuuuuuAAAAAA. */ +{ "dmulh21", 0x36727000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,u6 0011011001110010F111uuuuuu111110. */ +{ "dmulh21", 0x3672703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,u6 0011011011110010F111uuuuuu1QQQQQ. */ +{ "dmulh21", 0x36F27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh21<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ +{ "dmulh21", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> 0,limm,s12 0011011010110010F111ssssssSSSSSS. */ +{ "dmulh21", 0x36B27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh21<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ +{ "dmulh21", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh21<.f> 0,limm,limm 0011011000001010F111111110111110. */ +{ "dmulh21", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ +{ "dmulh21", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh21<.f> a,limm,limm 0011011000110010F111111110AAAAAA. */ +{ "dmulh21", 0x36327F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh21<.f> 0,limm,limm 0011011000110010F111111110111110. */ +{ "dmulh21", 0x36327FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh21<.f><.cc> 0,limm,limm 0011011011110010F1111111100QQQQQ. */ +{ "dmulh21", 0x36F27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ +{ "dmulh22", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh22<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ +{ "dmulh22", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "dmulh22", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,c 00110bbb00110011FBBBCCCCCCAAAAAA. */ +{ "dmulh22", 0x30330000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dmulh22<.f> 0,b,c 00110bbb00110011FBBBCCCCCC111110. */ +{ "dmulh22", 0x3033003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,c 00110bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "dmulh22", 0x30F30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ +{ "dmulh22", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ +{ "dmulh22", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "dmulh22", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> a,b,u6 00110bbb01110011FBBBuuuuuuAAAAAA. */ +{ "dmulh22", 0x30730000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,b,u6 00110bbb01110011FBBBuuuuuu111110. */ +{ "dmulh22", 0x3073003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> b,b,u6 00110bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "dmulh22", 0x30F30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ +{ "dmulh22", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> b,b,s12 00110bbb10110011FBBBssssssSSSSSS. */ +{ "dmulh22", 0x30B30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ +{ "dmulh22", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh22<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ +{ "dmulh22", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh22<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ +{ "dmulh22", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh22<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ +{ "dmulh22", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ +{ "dmulh22", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh22<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ +{ "dmulh22", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,c 0011011000110011F111CCCCCCAAAAAA. */ +{ "dmulh22", 0x36337000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dmulh22<.f> a,b,limm 00110bbb00110011FBBB111110AAAAAA. */ +{ "dmulh22", 0x30330F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dmulh22<.f> 0,limm,c 0011011000110011F111CCCCCC111110. */ +{ "dmulh22", 0x3633703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dmulh22<.f> 0,b,limm 00110bbb00110011FBBB111110111110. */ +{ "dmulh22", 0x30330FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,c 0011011011110011F111CCCCCC0QQQQQ. */ +{ "dmulh22", 0x36F37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dmulh22<.f><.cc> b,b,limm 00110bbb11110011FBBB1111100QQQQQ. */ +{ "dmulh22", 0x30F30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ +{ "dmulh22", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ +{ "dmulh22", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ +{ "dmulh22", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,u6 0011011001110011F111uuuuuuAAAAAA. */ +{ "dmulh22", 0x36737000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,u6 0011011001110011F111uuuuuu111110. */ +{ "dmulh22", 0x3673703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,u6 0011011011110011F111uuuuuu1QQQQQ. */ +{ "dmulh22", 0x36F37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dmulh22<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ +{ "dmulh22", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> 0,limm,s12 0011011010110011F111ssssssSSSSSS. */ +{ "dmulh22", 0x36B37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dmulh22<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ +{ "dmulh22", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh22<.f> 0,limm,limm 0011011000001011F111111110111110. */ +{ "dmulh22", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ +{ "dmulh22", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulh22<.f> a,limm,limm 0011011000110011F111111110AAAAAA. */ +{ "dmulh22", 0x36337F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh22<.f> 0,limm,limm 0011011000110011F111111110111110. */ +{ "dmulh22", 0x36337FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dmulh22<.f><.cc> 0,limm,limm 0011011011110011F1111111100QQQQQ. */ +{ "dmulh22", 0x36F37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dmulpf<.f> a,b,c 00101bbb00111010FBBBCCCCCCAAAAAA. */ +{ "dmulpf", 0x283A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* dmulpf<.f><.cc> b,b,c 00101bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "dmulpf", 0x28FA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dmulpf<.f> 0,b,c 00101bbb00111010FBBBCCCCCC111110. */ +{ "dmulpf", 0x283A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* dmulpf<.f> a,b,limm 00101bbb00111010FBBB111110AAAAAA. */ +{ "dmulpf", 0x283A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* dmulpf<.f><.cc> b,b,limm 00101bbb11111010FBBB1111100QQQQQ. */ +{ "dmulpf", 0x28FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* drsubh11<.f> a,b,c 00110bbb00010100FBBBCCCCCCAAAAAA. */ +{ "drsubh11", 0x30140000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* drsubh11<.f> 0,b,c 00110bbb00010100FBBBCCCCCC111110. */ +{ "drsubh11", 0x3014003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* drsubh11<.f><.cc> b,b,c 00110bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "drsubh11", 0x30D40000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* drsubh11<.f> a,b,u6 00110bbb01010100FBBBuuuuuuAAAAAA. */ +{ "drsubh11", 0x30540000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh11<.f> 0,b,u6 00110bbb01010100FBBBuuuuuu111110. */ +{ "drsubh11", 0x3054003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh11<.f><.cc> b,b,u6 00110bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "drsubh11", 0x30D40020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh11<.f> b,b,s12 00110bbb10010100FBBBssssssSSSSSS. */ +{ "drsubh11", 0x30940000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* drsubh11<.f> a,limm,c 0011011000010100F111CCCCCCAAAAAA. */ +{ "drsubh11", 0x36147000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* drsubh11<.f> a,b,limm 00110bbb00010100FBBB111110AAAAAA. */ +{ "drsubh11", 0x30140F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* drsubh11<.f> 0,limm,c 0011011000010100F111CCCCCC111110. */ +{ "drsubh11", 0x3614703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* drsubh11<.f> 0,b,limm 00110bbb00010100FBBB111110111110. */ +{ "drsubh11", 0x30140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,c 0011011011010100F111CCCCCC0QQQQQ. */ +{ "drsubh11", 0x36D47000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* drsubh11<.f><.cc> b,b,limm 00110bbb11010100FBBB1111100QQQQQ. */ +{ "drsubh11", 0x30D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* drsubh11<.f> a,limm,u6 0011011001010100F111uuuuuuAAAAAA. */ +{ "drsubh11", 0x36547000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh11<.f> 0,limm,u6 0011011001010100F111uuuuuu111110. */ +{ "drsubh11", 0x3654703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,u6 0011011011010100F111uuuuuu1QQQQQ. */ +{ "drsubh11", 0x36D47020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh11<.f> 0,limm,s12 0011011010010100F111ssssssSSSSSS. */ +{ "drsubh11", 0x36947000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* drsubh11<.f> a,limm,limm 0011011000010100F111111110AAAAAA. */ +{ "drsubh11", 0x36147F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh11<.f> 0,limm,limm 0011011000010100F111111110111110. */ +{ "drsubh11", 0x36147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh11<.f><.cc> 0,limm,limm 0011011011010100F1111111100QQQQQ. */ +{ "drsubh11", 0x36D47F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* drsubh12<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ +{ "drsubh12", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* drsubh12<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ +{ "drsubh12", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* drsubh12<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "drsubh12", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* drsubh12<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ +{ "drsubh12", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh12<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ +{ "drsubh12", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh12<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "drsubh12", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh12<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ +{ "drsubh12", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* drsubh12<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ +{ "drsubh12", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* drsubh12<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ +{ "drsubh12", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* drsubh12<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ +{ "drsubh12", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* drsubh12<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ +{ "drsubh12", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,c 0011011011010101F111CCCCCC0QQQQQ. */ +{ "drsubh12", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* drsubh12<.f><.cc> b,b,limm 00110bbb11010101FBBB1111100QQQQQ. */ +{ "drsubh12", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* drsubh12<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ +{ "drsubh12", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh12<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ +{ "drsubh12", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ +{ "drsubh12", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh12<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ +{ "drsubh12", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* drsubh12<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ +{ "drsubh12", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh12<.f> 0,limm,limm 0011011000010101F111111110111110. */ +{ "drsubh12", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh12<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ +{ "drsubh12", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* drsubh21<.f> a,b,c 00110bbb00010110FBBBCCCCCCAAAAAA. */ +{ "drsubh21", 0x30160000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* drsubh21<.f> 0,b,c 00110bbb00010110FBBBCCCCCC111110. */ +{ "drsubh21", 0x3016003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* drsubh21<.f><.cc> b,b,c 00110bbb11010110FBBBCCCCCC0QQQQQ. */ +{ "drsubh21", 0x30D60000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* drsubh21<.f> a,b,u6 00110bbb01010110FBBBuuuuuuAAAAAA. */ +{ "drsubh21", 0x30560000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh21<.f> 0,b,u6 00110bbb01010110FBBBuuuuuu111110. */ +{ "drsubh21", 0x3056003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh21<.f><.cc> b,b,u6 00110bbb11010110FBBBuuuuuu1QQQQQ. */ +{ "drsubh21", 0x30D60020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh21<.f> b,b,s12 00110bbb10010110FBBBssssssSSSSSS. */ +{ "drsubh21", 0x30960000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* drsubh21<.f> a,limm,c 0011011000010110F111CCCCCCAAAAAA. */ +{ "drsubh21", 0x36167000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* drsubh21<.f> a,b,limm 00110bbb00010110FBBB111110AAAAAA. */ +{ "drsubh21", 0x30160F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* drsubh21<.f> 0,limm,c 0011011000010110F111CCCCCC111110. */ +{ "drsubh21", 0x3616703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* drsubh21<.f> 0,b,limm 00110bbb00010110FBBB111110111110. */ +{ "drsubh21", 0x30160FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,c 0011011011010110F111CCCCCC0QQQQQ. */ +{ "drsubh21", 0x36D67000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* drsubh21<.f><.cc> b,b,limm 00110bbb11010110FBBB1111100QQQQQ. */ +{ "drsubh21", 0x30D60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* drsubh21<.f> a,limm,u6 0011011001010110F111uuuuuuAAAAAA. */ +{ "drsubh21", 0x36567000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh21<.f> 0,limm,u6 0011011001010110F111uuuuuu111110. */ +{ "drsubh21", 0x3656703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,u6 0011011011010110F111uuuuuu1QQQQQ. */ +{ "drsubh21", 0x36D67020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh21<.f> 0,limm,s12 0011011010010110F111ssssssSSSSSS. */ +{ "drsubh21", 0x36967000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* drsubh21<.f> a,limm,limm 0011011000010110F111111110AAAAAA. */ +{ "drsubh21", 0x36167F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh21<.f> 0,limm,limm 0011011000010110F111111110111110. */ +{ "drsubh21", 0x36167FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh21<.f><.cc> 0,limm,limm 0011011011010110F1111111100QQQQQ. */ +{ "drsubh21", 0x36D67F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* drsubh22<.f> a,b,c 00110bbb00010111FBBBCCCCCCAAAAAA. */ +{ "drsubh22", 0x30170000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* drsubh22<.f> 0,b,c 00110bbb00010111FBBBCCCCCC111110. */ +{ "drsubh22", 0x3017003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* drsubh22<.f><.cc> b,b,c 00110bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "drsubh22", 0x30D70000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* drsubh22<.f> a,b,u6 00110bbb01010111FBBBuuuuuuAAAAAA. */ +{ "drsubh22", 0x30570000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh22<.f> 0,b,u6 00110bbb01010111FBBBuuuuuu111110. */ +{ "drsubh22", 0x3057003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* drsubh22<.f><.cc> b,b,u6 00110bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "drsubh22", 0x30D70020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh22<.f> b,b,s12 00110bbb10010111FBBBssssssSSSSSS. */ +{ "drsubh22", 0x30970000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* drsubh22<.f> a,limm,c 0011011000010111F111CCCCCCAAAAAA. */ +{ "drsubh22", 0x36177000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* drsubh22<.f> a,b,limm 00110bbb00010111FBBB111110AAAAAA. */ +{ "drsubh22", 0x30170F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* drsubh22<.f> 0,limm,c 0011011000010111F111CCCCCC111110. */ +{ "drsubh22", 0x3617703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* drsubh22<.f> 0,b,limm 00110bbb00010111FBBB111110111110. */ +{ "drsubh22", 0x30170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,c 0011011011010111F111CCCCCC0QQQQQ. */ +{ "drsubh22", 0x36D77000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* drsubh22<.f><.cc> b,b,limm 00110bbb11010111FBBB1111100QQQQQ. */ +{ "drsubh22", 0x30D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* drsubh22<.f> a,limm,u6 0011011001010111F111uuuuuuAAAAAA. */ +{ "drsubh22", 0x36577000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh22<.f> 0,limm,u6 0011011001010111F111uuuuuu111110. */ +{ "drsubh22", 0x3657703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,u6 0011011011010111F111uuuuuu1QQQQQ. */ +{ "drsubh22", 0x36D77020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* drsubh22<.f> 0,limm,s12 0011011010010111F111ssssssSSSSSS. */ +{ "drsubh22", 0x36977000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* drsubh22<.f> a,limm,limm 0011011000010111F111111110AAAAAA. */ +{ "drsubh22", 0x36177F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh22<.f> 0,limm,limm 0011011000010111F111111110111110. */ +{ "drsubh22", 0x36177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* drsubh22<.f><.cc> 0,limm,limm 0011011011010111F1111111100QQQQQ. */ +{ "drsubh22", 0x36D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,c 00110bbb00010000FBBBCCCCCCAAAAAA. */ +{ "dsubh11", 0x30100000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh11<.f> 0,b,c 00110bbb00010000FBBBCCCCCC111110. */ +{ "dsubh11", 0x3010003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,c 00110bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "dsubh11", 0x30D00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,c 00110bbb00111000FBBBCCCCCCAAAAAA. */ +{ "dsubh11", 0x30380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh11<.f> 0,b,c 00110bbb00111000FBBBCCCCCC111110. */ +{ "dsubh11", 0x3038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,c 00110bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "dsubh11", 0x30F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,u6 00110bbb01010000FBBBuuuuuuAAAAAA. */ +{ "dsubh11", 0x30500000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,b,u6 00110bbb01010000FBBBuuuuuu111110. */ +{ "dsubh11", 0x3050003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,u6 00110bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "dsubh11", 0x30D00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> a,b,u6 00110bbb01111000FBBBuuuuuuAAAAAA. */ +{ "dsubh11", 0x30780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,b,u6 00110bbb01111000FBBBuuuuuu111110. */ +{ "dsubh11", 0x3078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> b,b,u6 00110bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "dsubh11", 0x30F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> b,b,s12 00110bbb10010000FBBBssssssSSSSSS. */ +{ "dsubh11", 0x30900000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> b,b,s12 00110bbb10111000FBBBssssssSSSSSS. */ +{ "dsubh11", 0x30B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> a,limm,c 0011011000010000F111CCCCCCAAAAAA. */ +{ "dsubh11", 0x36107000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh11<.f> a,b,limm 00110bbb00010000FBBB111110AAAAAA. */ +{ "dsubh11", 0x30100F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh11<.f> 0,limm,c 0011011000010000F111CCCCCC111110. */ +{ "dsubh11", 0x3610703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh11<.f> 0,b,limm 00110bbb00010000FBBB111110111110. */ +{ "dsubh11", 0x30100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,c 0011011011010000F111CCCCCC0QQQQQ. */ +{ "dsubh11", 0x36D07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh11<.f><.cc> b,b,limm 00110bbb11010000FBBB1111100QQQQQ. */ +{ "dsubh11", 0x30D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,c 0011011000111000F111CCCCCCAAAAAA. */ +{ "dsubh11", 0x36387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh11<.f> a,b,limm 00110bbb00111000FBBB111110AAAAAA. */ +{ "dsubh11", 0x30380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh11<.f> 0,limm,c 0011011000111000F111CCCCCC111110. */ +{ "dsubh11", 0x3638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh11<.f> 0,b,limm 00110bbb00111000FBBB111110111110. */ +{ "dsubh11", 0x30380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,c 0011011011111000F111CCCCCC0QQQQQ. */ +{ "dsubh11", 0x36F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh11<.f><.cc> b,b,limm 00110bbb11111000FBBB1111100QQQQQ. */ +{ "dsubh11", 0x30F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,u6 0011011001010000F111uuuuuuAAAAAA. */ +{ "dsubh11", 0x36507000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,u6 0011011001010000F111uuuuuu111110. */ +{ "dsubh11", 0x3650703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,u6 0011011011010000F111uuuuuu1QQQQQ. */ +{ "dsubh11", 0x36D07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,u6 0011011001111000F111uuuuuuAAAAAA. */ +{ "dsubh11", 0x36787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,u6 0011011001111000F111uuuuuu111110. */ +{ "dsubh11", 0x3678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,u6 0011011011111000F111uuuuuu1QQQQQ. */ +{ "dsubh11", 0x36F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh11<.f> 0,limm,s12 0011011010010000F111ssssssSSSSSS. */ +{ "dsubh11", 0x36907000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> 0,limm,s12 0011011010111000F111ssssssSSSSSS. */ +{ "dsubh11", 0x36B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh11<.f> a,limm,limm 0011011000010000F111111110AAAAAA. */ +{ "dsubh11", 0x36107F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh11<.f> 0,limm,limm 0011011000010000F111111110111110. */ +{ "dsubh11", 0x36107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,limm 0011011011010000F1111111100QQQQQ. */ +{ "dsubh11", 0x36D07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh11<.f> a,limm,limm 0011011000111000F111111110AAAAAA. */ +{ "dsubh11", 0x36387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh11<.f> 0,limm,limm 0011011000111000F111111110111110. */ +{ "dsubh11", 0x36387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh11<.f><.cc> 0,limm,limm 0011011011111000F1111111100QQQQQ. */ +{ "dsubh11", 0x36F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,c 00110bbb00010001FBBBCCCCCCAAAAAA. */ +{ "dsubh12", 0x30110000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh12<.f> 0,b,c 00110bbb00010001FBBBCCCCCC111110. */ +{ "dsubh12", 0x3011003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,c 00110bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "dsubh12", 0x30D10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,c 00110bbb00111001FBBBCCCCCCAAAAAA. */ +{ "dsubh12", 0x30390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh12<.f> 0,b,c 00110bbb00111001FBBBCCCCCC111110. */ +{ "dsubh12", 0x3039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,c 00110bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "dsubh12", 0x30F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,u6 00110bbb01010001FBBBuuuuuuAAAAAA. */ +{ "dsubh12", 0x30510000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,b,u6 00110bbb01010001FBBBuuuuuu111110. */ +{ "dsubh12", 0x3051003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,u6 00110bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "dsubh12", 0x30D10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> a,b,u6 00110bbb01111001FBBBuuuuuuAAAAAA. */ +{ "dsubh12", 0x30790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,b,u6 00110bbb01111001FBBBuuuuuu111110. */ +{ "dsubh12", 0x3079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> b,b,u6 00110bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "dsubh12", 0x30F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> b,b,s12 00110bbb10010001FBBBssssssSSSSSS. */ +{ "dsubh12", 0x30910000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> b,b,s12 00110bbb10111001FBBBssssssSSSSSS. */ +{ "dsubh12", 0x30B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> a,limm,c 0011011000010001F111CCCCCCAAAAAA. */ +{ "dsubh12", 0x36117000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh12<.f> a,b,limm 00110bbb00010001FBBB111110AAAAAA. */ +{ "dsubh12", 0x30110F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh12<.f> 0,limm,c 0011011000010001F111CCCCCC111110. */ +{ "dsubh12", 0x3611703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh12<.f> 0,b,limm 00110bbb00010001FBBB111110111110. */ +{ "dsubh12", 0x30110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,c 0011011011010001F111CCCCCC0QQQQQ. */ +{ "dsubh12", 0x36D17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh12<.f><.cc> b,b,limm 00110bbb11010001FBBB1111100QQQQQ. */ +{ "dsubh12", 0x30D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,c 0011011000111001F111CCCCCCAAAAAA. */ +{ "dsubh12", 0x36397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh12<.f> a,b,limm 00110bbb00111001FBBB111110AAAAAA. */ +{ "dsubh12", 0x30390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh12<.f> 0,limm,c 0011011000111001F111CCCCCC111110. */ +{ "dsubh12", 0x3639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh12<.f> 0,b,limm 00110bbb00111001FBBB111110111110. */ +{ "dsubh12", 0x30390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,c 0011011011111001F111CCCCCC0QQQQQ. */ +{ "dsubh12", 0x36F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh12<.f><.cc> b,b,limm 00110bbb11111001FBBB1111100QQQQQ. */ +{ "dsubh12", 0x30F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,u6 0011011001010001F111uuuuuuAAAAAA. */ +{ "dsubh12", 0x36517000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,u6 0011011001010001F111uuuuuu111110. */ +{ "dsubh12", 0x3651703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,u6 0011011011010001F111uuuuuu1QQQQQ. */ +{ "dsubh12", 0x36D17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,u6 0011011001111001F111uuuuuuAAAAAA. */ +{ "dsubh12", 0x36797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,u6 0011011001111001F111uuuuuu111110. */ +{ "dsubh12", 0x3679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,u6 0011011011111001F111uuuuuu1QQQQQ. */ +{ "dsubh12", 0x36F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh12<.f> 0,limm,s12 0011011010010001F111ssssssSSSSSS. */ +{ "dsubh12", 0x36917000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> 0,limm,s12 0011011010111001F111ssssssSSSSSS. */ +{ "dsubh12", 0x36B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh12<.f> a,limm,limm 0011011000010001F111111110AAAAAA. */ +{ "dsubh12", 0x36117F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh12<.f> 0,limm,limm 0011011000010001F111111110111110. */ +{ "dsubh12", 0x36117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,limm 0011011011010001F1111111100QQQQQ. */ +{ "dsubh12", 0x36D17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh12<.f> a,limm,limm 0011011000111001F111111110AAAAAA. */ +{ "dsubh12", 0x36397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh12<.f> 0,limm,limm 0011011000111001F111111110111110. */ +{ "dsubh12", 0x36397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh12<.f><.cc> 0,limm,limm 0011011011111001F1111111100QQQQQ. */ +{ "dsubh12", 0x36F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ +{ "dsubh21", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh21<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ +{ "dsubh21", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "dsubh21", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,c 00110bbb00111010FBBBCCCCCCAAAAAA. */ +{ "dsubh21", 0x303A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh21<.f> 0,b,c 00110bbb00111010FBBBCCCCCC111110. */ +{ "dsubh21", 0x303A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,c 00110bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "dsubh21", 0x30FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ +{ "dsubh21", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ +{ "dsubh21", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "dsubh21", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> a,b,u6 00110bbb01111010FBBBuuuuuuAAAAAA. */ +{ "dsubh21", 0x307A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,b,u6 00110bbb01111010FBBBuuuuuu111110. */ +{ "dsubh21", 0x307A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> b,b,u6 00110bbb11111010FBBBuuuuuu1QQQQQ. */ +{ "dsubh21", 0x30FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ +{ "dsubh21", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> b,b,s12 00110bbb10111010FBBBssssssSSSSSS. */ +{ "dsubh21", 0x30BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ +{ "dsubh21", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh21<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ +{ "dsubh21", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh21<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ +{ "dsubh21", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh21<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ +{ "dsubh21", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ +{ "dsubh21", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh21<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ +{ "dsubh21", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,c 0011011000111010F111CCCCCCAAAAAA. */ +{ "dsubh21", 0x363A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh21<.f> a,b,limm 00110bbb00111010FBBB111110AAAAAA. */ +{ "dsubh21", 0x303A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh21<.f> 0,limm,c 0011011000111010F111CCCCCC111110. */ +{ "dsubh21", 0x363A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh21<.f> 0,b,limm 00110bbb00111010FBBB111110111110. */ +{ "dsubh21", 0x303A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,c 0011011011111010F111CCCCCC0QQQQQ. */ +{ "dsubh21", 0x36FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh21<.f><.cc> b,b,limm 00110bbb11111010FBBB1111100QQQQQ. */ +{ "dsubh21", 0x30FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ +{ "dsubh21", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ +{ "dsubh21", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ +{ "dsubh21", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,u6 0011011001111010F111uuuuuuAAAAAA. */ +{ "dsubh21", 0x367A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,u6 0011011001111010F111uuuuuu111110. */ +{ "dsubh21", 0x367A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,u6 0011011011111010F111uuuuuu1QQQQQ. */ +{ "dsubh21", 0x36FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh21<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ +{ "dsubh21", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> 0,limm,s12 0011011010111010F111ssssssSSSSSS. */ +{ "dsubh21", 0x36BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh21<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ +{ "dsubh21", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh21<.f> 0,limm,limm 0011011000010010F111111110111110. */ +{ "dsubh21", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ +{ "dsubh21", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh21<.f> a,limm,limm 0011011000111010F111111110AAAAAA. */ +{ "dsubh21", 0x363A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh21<.f> 0,limm,limm 0011011000111010F111111110111110. */ +{ "dsubh21", 0x363A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh21<.f><.cc> 0,limm,limm 0011011011111010F1111111100QQQQQ. */ +{ "dsubh21", 0x36FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ +{ "dsubh22", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh22<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ +{ "dsubh22", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "dsubh22", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,c 00110bbb00111011FBBBCCCCCCAAAAAA. */ +{ "dsubh22", 0x303B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, RC }, { C_F }}, + +/* dsubh22<.f> 0,b,c 00110bbb00111011FBBBCCCCCC111110. */ +{ "dsubh22", 0x303B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, RC }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,c 00110bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "dsubh22", 0x30FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ +{ "dsubh22", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ +{ "dsubh22", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "dsubh22", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> a,b,u6 00110bbb01111011FBBBuuuuuuAAAAAA. */ +{ "dsubh22", 0x307B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,b,u6 00110bbb01111011FBBBuuuuuu111110. */ +{ "dsubh22", 0x307B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> b,b,u6 00110bbb11111011FBBBuuuuuu1QQQQQ. */ +{ "dsubh22", 0x30FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ +{ "dsubh22", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> b,b,s12 00110bbb10111011FBBBssssssSSSSSS. */ +{ "dsubh22", 0x30BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ +{ "dsubh22", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh22<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ +{ "dsubh22", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh22<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ +{ "dsubh22", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh22<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ +{ "dsubh22", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ +{ "dsubh22", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh22<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ +{ "dsubh22", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,c 0011011000111011F111CCCCCCAAAAAA. */ +{ "dsubh22", 0x363B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, RC }, { C_F }}, + +/* dsubh22<.f> a,b,limm 00110bbb00111011FBBB111110AAAAAA. */ +{ "dsubh22", 0x303B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, RB, LIMM }, { C_F }}, + +/* dsubh22<.f> 0,limm,c 0011011000111011F111CCCCCC111110. */ +{ "dsubh22", 0x363B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F }}, + +/* dsubh22<.f> 0,b,limm 00110bbb00111011FBBB111110111110. */ +{ "dsubh22", 0x303B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, RB, LIMM }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,c 0011011011111011F111CCCCCC0QQQQQ. */ +{ "dsubh22", 0x36FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* dsubh22<.f><.cc> b,b,limm 00110bbb11111011FBBB1111100QQQQQ. */ +{ "dsubh22", 0x30FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ +{ "dsubh22", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ +{ "dsubh22", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ +{ "dsubh22", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,u6 0011011001111011F111uuuuuuAAAAAA. */ +{ "dsubh22", 0x367B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,u6 0011011001111011F111uuuuuu111110. */ +{ "dsubh22", 0x367B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,u6 0011011011111011F111uuuuuu1QQQQQ. */ +{ "dsubh22", 0x36FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* dsubh22<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ +{ "dsubh22", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> 0,limm,s12 0011011010111011F111ssssssSSSSSS. */ +{ "dsubh22", 0x36BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* dsubh22<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ +{ "dsubh22", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh22<.f> 0,limm,limm 0011011000010011F111111110111110. */ +{ "dsubh22", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ +{ "dsubh22", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsubh22<.f> a,limm,limm 0011011000111011F111111110AAAAAA. */ +{ "dsubh22", 0x363B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh22<.f> 0,limm,limm 0011011000111011F111111110111110. */ +{ "dsubh22", 0x363B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* dsubh22<.f><.cc> 0,limm,limm 0011011011111011F1111111100QQQQQ. */ +{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* dsync 00100010011011110001RRRRRR111111. */ +{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }}, + +/* ei_s u10 010111uuuuuuuuuu. */ +{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }}, + +/* enter_s u6 110000UU111uuuu0. */ +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, BRAKETdup }, { 0 }}, +{ "enter_s", 0x0000C0E0, 0x0000FCE1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM6_11_S }, { 0 }}, + +/* ex<.di> b,c 00100bbb00101111DBBBCCCCCC001100. */ +{ "ex", 0x202F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* ex<.di> b,u6 00100bbb01101111DBBBuuuuuu001100. */ +{ "ex", 0x206F000C, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* ex<.di> b,limm 00100bbb00101111DBBB111110001100. */ +{ "ex", 0x202F0F8C, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,c 0010011000101111D111CCCCCC001100. */ +{ "ex", 0x262F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,u6 0010011001101111D111uuuuuu001100. */ +{ "ex", 0x266F700C, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* ex<.di> limm,limm 0010011000101111D111111110001100. */ +{ "ex", 0x262F7F8C, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }}, + +/* extb<.f> b,c 00100bbb00101111FBBBCCCCCC000111. */ +{ "extb", 0x202F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, + +/* extb<.f> 0,c 0010011000101111F111CCCCCC000111. */ +{ "extb", 0x262F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* extb<.f> b,u6 00100bbb01101111FBBBuuuuuu000111. */ +{ "extb", 0x206F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* extb<.f> 0,u6 0010011001101111F111uuuuuu000111. */ +{ "extb", 0x266F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* extb<.f> b,limm 00100bbb00101111FBBB111110000111. */ +{ "extb", 0x202F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* extb<.f> 0,limm 0010011000101111F111111110000111. */ +{ "extb", 0x262F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* extb_s b,c 01111bbbccc01111. */ +{ "extb_s", 0x0000780F, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* exth<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ +{ "exth", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, + +/* exth<.f> 0,c 0010011000101111F111CCCCCC001000. */ +{ "exth", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* exth<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ +{ "exth", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* exth<.f> 0,u6 0010011001101111F111uuuuuu001000. */ +{ "exth", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* exth<.f> b,limm 00100bbb00101111FBBB111110001000. */ +{ "exth", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* exth<.f> 0,limm 0010011000101111F111111110001000. */ +{ "exth", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* exth_s b,c 01111bbbccc10000. */ +{ "exth_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* extw<.f> b,c 00100bbb00101111FBBBCCCCCC001000. */ +{ "extw", 0x202F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* extw<.f> 0,c 0010011000101111F111CCCCCC001000. */ +{ "extw", 0x262F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* extw<.f> b,u6 00100bbb01101111FBBBuuuuuu001000. */ +{ "extw", 0x206F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* extw<.f> 0,u6 0010011001101111F111uuuuuu001000. */ +{ "extw", 0x266F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* extw<.f> b,limm 00100bbb00101111FBBB111110001000. */ +{ "extw", 0x202F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* extw<.f> 0,limm 0010011000101111F111111110001000. */ +{ "extw", 0x262F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* extw_s b,c 01111bbbccc10000. */ +{ "extw_s", 0x00007810, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* fadd<.f> a,b,c 00110bbb00000001FBBBCCCCCCAAAAAA. */ +{ "fadd", 0x30010000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }}, + +/* fadd<.f> 0,b,c 00110bbb00000001FBBBCCCCCC111110. */ +{ "fadd", 0x3001003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }}, + +/* fadd<.f><.cc> b,b,c 00110bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "fadd", 0x30C10000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* fadd<.f> a,b,u6 00110bbb01000001FBBBuuuuuuAAAAAA. */ +{ "fadd", 0x30410000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* fadd<.f> 0,b,u6 00110bbb01000001FBBBuuuuuu111110. */ +{ "fadd", 0x3041003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* fadd<.f><.cc> b,b,u6 00110bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "fadd", 0x30C10020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* fadd<.f> b,b,s12 00110bbb10000001FBBBssssssSSSSSS. */ +{ "fadd", 0x30810000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* fadd<.f> a,limm,c 0011011000000001F111CCCCCCAAAAAA. */ +{ "fadd", 0x36017000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }}, + +/* fadd<.f> a,b,limm 00110bbb00000001FBBB111110AAAAAA. */ +{ "fadd", 0x30010F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }}, + +/* fadd<.f> 0,limm,c 0011011000000001F111CCCCCC111110. */ +{ "fadd", 0x3601703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }}, + +/* fadd<.f> 0,b,limm 00110bbb00000001FBBB111110111110. */ +{ "fadd", 0x30010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,c 0011011011000001F111CCCCCC0QQQQQ. */ +{ "fadd", 0x36C17000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* fadd<.f><.cc> b,b,limm 00110bbb11000001FBBB1111100QQQQQ. */ +{ "fadd", 0x30C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* fadd<.f> a,limm,u6 0011011001000001F111uuuuuuAAAAAA. */ +{ "fadd", 0x36417000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* fadd<.f> 0,limm,u6 0011011001000001F111uuuuuu111110. */ +{ "fadd", 0x3641703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,u6 0011011011000001F111uuuuuu1QQQQQ. */ +{ "fadd", 0x36C17020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* fadd<.f> 0,limm,s12 0011011010000001F111ssssssSSSSSS. */ +{ "fadd", 0x36817000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* fadd<.f> a,limm,limm 0011011000000001F111111110AAAAAA. */ +{ "fadd", 0x36017F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* fadd<.f> 0,limm,limm 0011011000000001F111111110111110. */ +{ "fadd", 0x36017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* fadd<.f><.cc> 0,limm,limm 0011011011000001F1111111100QQQQQ. */ +{ "fadd", 0x36C17F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* fbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ +{ "fbfdw", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, RC }, { C_F }}, + +/* fbfdw<.f> 0,c 0010111000101111F111CCCCCC001011. */ +{ "fbfdw", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RC }, { C_F }}, + +/* fbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ +{ "fbfdw", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* fbfdw<.f> 0,u6 0010111001101111F111uuuuuu001011. */ +{ "fbfdw", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* fbfdw<.f> b,limm 00101bbb00101111FBBB111110001011. */ +{ "fbfdw", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* fbfdw<.f> 0,limm 0010111000101111F111111110001011. */ +{ "fbfdw", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* fcvt32 a,b,c 00110bbb000010000BBBCCCCCCAAAAAA. */ +{ "fcvt32", 0x30080000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }}, + +/* fcvt32 0,b,c 00110bbb000010000BBBCCCCCC111110. */ +{ "fcvt32", 0x3008003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }}, + +/* fcvt32<.cc> b,b,c 00110bbb110010000BBBCCCCCC0QQQQQ. */ +{ "fcvt32", 0x30C80000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }}, + +/* fcvt32 a,b,u6 00110bbb010010000BBBuuuuuuAAAAAA. */ +{ "fcvt32", 0x30480000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt32 0,b,u6 00110bbb010010000BBBuuuuuu111110. */ +{ "fcvt32", 0x3048003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt32<.cc> b,b,u6 00110bbb110010000BBBuuuuuu1QQQQQ. */ +{ "fcvt32", 0x30C80020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fcvt32 b,b,s12 00110bbb100010000BBBssssssSSSSSS. */ +{ "fcvt32", 0x30880000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fcvt32 a,limm,c 00110110000010000111CCCCCCAAAAAA. */ +{ "fcvt32", 0x36087000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }}, + +/* fcvt32 a,b,limm 00110bbb000010000BBB111110AAAAAA. */ +{ "fcvt32", 0x30080F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }}, + +/* fcvt32 0,limm,c 00110110000010000111CCCCCC111110. */ +{ "fcvt32", 0x3608703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }}, + +/* fcvt32 0,b,limm 00110bbb000010000BBB111110111110. */ +{ "fcvt32", 0x30080FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }}, + +/* fcvt32<.cc> b,b,limm 00110bbb110010000BBB1111100QQQQQ. */ +{ "fcvt32", 0x30C80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }}, + +/* fcvt32<.cc> 0,limm,c 00110110110010000111CCCCCC0QQQQQ. */ +{ "fcvt32", 0x36C87000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }}, + +/* fcvt32 a,limm,u6 00110110010010000111uuuuuuAAAAAA. */ +{ "fcvt32", 0x36487000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt32 0,limm,u6 00110110010010000111uuuuuu111110. */ +{ "fcvt32", 0x3648703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt32<.cc> 0,limm,u6 00110110110010000111uuuuuu1QQQQQ. */ +{ "fcvt32", 0x36C87020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fcvt32 0,limm,s12 00110110100010000111ssssssSSSSSS. */ +{ "fcvt32", 0x36887000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fcvt32 a,limm,limm 00110110000010000111111110AAAAAA. */ +{ "fcvt32", 0x36087F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt32 0,limm,limm 00110110000010000111111110111110. */ +{ "fcvt32", 0x36087FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt32<.cc> 0,limm,limm 001101101100100001111111100QQQQQ. */ +{ "fcvt32", 0x36C87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fcvt32_64 a,b,c 00110bbb000010010BBBCCCCCCAAAAAA. */ +{ "fcvt32_64", 0x30090000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }}, + +/* fcvt32_64 0,b,c 00110bbb000010010BBBCCCCCC111110. */ +{ "fcvt32_64", 0x3009003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }}, + +/* fcvt32_64<.cc> b,b,c 00110bbb110010010BBBCCCCCC0QQQQQ. */ +{ "fcvt32_64", 0x30C90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }}, + +/* fcvt32_64 a,b,u6 00110bbb010010010BBBuuuuuuAAAAAA. */ +{ "fcvt32_64", 0x30490000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt32_64 0,b,u6 00110bbb010010010BBBuuuuuu111110. */ +{ "fcvt32_64", 0x3049003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt32_64<.cc> b,b,u6 00110bbb110010010BBBuuuuuu1QQQQQ. */ +{ "fcvt32_64", 0x30C90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fcvt32_64 b,b,s12 00110bbb100010010BBBssssssSSSSSS. */ +{ "fcvt32_64", 0x30890000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fcvt32_64 a,limm,c 00110110000010010111CCCCCCAAAAAA. */ +{ "fcvt32_64", 0x36097000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }}, + +/* fcvt32_64 a,b,limm 00110bbb000010010BBB111110AAAAAA. */ +{ "fcvt32_64", 0x30090F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }}, + +/* fcvt32_64 0,limm,c 00110110000010010111CCCCCC111110. */ +{ "fcvt32_64", 0x3609703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }}, + +/* fcvt32_64 0,b,limm 00110bbb000010010BBB111110111110. */ +{ "fcvt32_64", 0x30090FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }}, + +/* fcvt32_64<.cc> b,b,limm 00110bbb110010010BBB1111100QQQQQ. */ +{ "fcvt32_64", 0x30C90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }}, + +/* fcvt32_64<.cc> 0,limm,c 00110110110010010111CCCCCC0QQQQQ. */ +{ "fcvt32_64", 0x36C97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }}, + +/* fcvt32_64 a,limm,u6 00110110010010010111uuuuuuAAAAAA. */ +{ "fcvt32_64", 0x36497000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt32_64 0,limm,u6 00110110010010010111uuuuuu111110. */ +{ "fcvt32_64", 0x3649703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt32_64<.cc> 0,limm,u6 00110110110010010111uuuuuu1QQQQQ. */ +{ "fcvt32_64", 0x36C97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fcvt32_64 0,limm,s12 00110110100010010111ssssssSSSSSS. */ +{ "fcvt32_64", 0x36897000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fcvt32_64 a,limm,limm 00110110000010010111111110AAAAAA. */ +{ "fcvt32_64", 0x36097F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt32_64 0,limm,limm 00110110000010010111111110111110. */ +{ "fcvt32_64", 0x36097FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt32_64<.cc> 0,limm,limm 001101101100100101111111100QQQQQ. */ +{ "fcvt32_64", 0x36C97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fcvt64 a,b,c 00110bbb001110000BBBCCCCCCAAAAAA. */ +{ "fcvt64", 0x30380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }}, + +/* fcvt64 0,b,c 00110bbb001110000BBBCCCCCC111110. */ +{ "fcvt64", 0x3038003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }}, + +/* fcvt64<.cc> b,b,c 00110bbb111110000BBBCCCCCC0QQQQQ. */ +{ "fcvt64", 0x30F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }}, + +/* fcvt64 a,b,u6 00110bbb011110000BBBuuuuuuAAAAAA. */ +{ "fcvt64", 0x30780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt64 0,b,u6 00110bbb011110000BBBuuuuuu111110. */ +{ "fcvt64", 0x3078003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt64<.cc> b,b,u6 00110bbb111110000BBBuuuuuu1QQQQQ. */ +{ "fcvt64", 0x30F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fcvt64 b,b,s12 00110bbb101110000BBBssssssSSSSSS. */ +{ "fcvt64", 0x30B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fcvt64 a,limm,c 00110110001110000111CCCCCCAAAAAA. */ +{ "fcvt64", 0x36387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }}, + +/* fcvt64 a,b,limm 00110bbb001110000BBB111110AAAAAA. */ +{ "fcvt64", 0x30380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }}, + +/* fcvt64 0,limm,c 00110110001110000111CCCCCC111110. */ +{ "fcvt64", 0x3638703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }}, + +/* fcvt64 0,b,limm 00110bbb001110000BBB111110111110. */ +{ "fcvt64", 0x30380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }}, + +/* fcvt64<.cc> b,b,limm 00110bbb111110000BBB1111100QQQQQ. */ +{ "fcvt64", 0x30F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }}, + +/* fcvt64<.cc> 0,limm,c 00110110111110000111CCCCCC0QQQQQ. */ +{ "fcvt64", 0x36F87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }}, + +/* fcvt64 a,limm,u6 00110110011110000111uuuuuuAAAAAA. */ +{ "fcvt64", 0x36787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt64 0,limm,u6 00110110011110000111uuuuuu111110. */ +{ "fcvt64", 0x3678703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt64<.cc> 0,limm,u6 00110110111110000111uuuuuu1QQQQQ. */ +{ "fcvt64", 0x36F87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fcvt64 0,limm,s12 00110110101110000111ssssssSSSSSS. */ +{ "fcvt64", 0x36B87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fcvt64 a,limm,limm 00110110001110000111111110AAAAAA. */ +{ "fcvt64", 0x36387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt64 0,limm,limm 00110110001110000111111110111110. */ +{ "fcvt64", 0x36387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt64<.cc> 0,limm,limm 001101101111100001111111100QQQQQ. */ +{ "fcvt64", 0x36F87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fcvt64_32 a,b,c 00110bbb001110010BBBCCCCCCAAAAAA. */ +{ "fcvt64_32", 0x30390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, RC }, { 0 }}, + +/* fcvt64_32 0,b,c 00110bbb001110010BBBCCCCCC111110. */ +{ "fcvt64_32", 0x3039003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, RC }, { 0 }}, + +/* fcvt64_32<.cc> b,b,c 00110bbb111110010BBBCCCCCC0QQQQQ. */ +{ "fcvt64_32", 0x30F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, RC }, { C_CC }}, + +/* fcvt64_32 a,b,u6 00110bbb011110010BBBuuuuuuAAAAAA. */ +{ "fcvt64_32", 0x30790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt64_32 0,b,u6 00110bbb011110010BBBuuuuuu111110. */ +{ "fcvt64_32", 0x3079003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fcvt64_32<.cc> b,b,u6 00110bbb111110010BBBuuuuuu1QQQQQ. */ +{ "fcvt64_32", 0x30F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fcvt64_32 b,b,s12 00110bbb101110010BBBssssssSSSSSS. */ +{ "fcvt64_32", 0x30B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fcvt64_32 a,limm,c 00110110001110010111CCCCCCAAAAAA. */ +{ "fcvt64_32", 0x36397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, RC }, { 0 }}, + +/* fcvt64_32 a,b,limm 00110bbb001110010BBB111110AAAAAA. */ +{ "fcvt64_32", 0x30390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, RB, LIMM }, { 0 }}, + +/* fcvt64_32 0,limm,c 00110110001110010111CCCCCC111110. */ +{ "fcvt64_32", 0x3639703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { 0 }}, + +/* fcvt64_32 0,b,limm 00110bbb001110010BBB111110111110. */ +{ "fcvt64_32", 0x30390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, RB, LIMM }, { 0 }}, + +/* fcvt64_32<.cc> b,b,limm 00110bbb111110010BBB1111100QQQQQ. */ +{ "fcvt64_32", 0x30F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RB, RBdup, LIMM }, { C_CC }}, + +/* fcvt64_32<.cc> 0,limm,c 00110110111110010111CCCCCC0QQQQQ. */ +{ "fcvt64_32", 0x36F97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, RC }, { C_CC }}, + +/* fcvt64_32 a,limm,u6 00110110011110010111uuuuuuAAAAAA. */ +{ "fcvt64_32", 0x36797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt64_32 0,limm,u6 00110110011110010111uuuuuu111110. */ +{ "fcvt64_32", 0x3679703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fcvt64_32<.cc> 0,limm,u6 00110110111110010111uuuuuu1QQQQQ. */ +{ "fcvt64_32", 0x36F97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fcvt64_32 0,limm,s12 00110110101110010111ssssssSSSSSS. */ +{ "fcvt64_32", 0x36B97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fcvt64_32 a,limm,limm 00110110001110010111111110AAAAAA. */ +{ "fcvt64_32", 0x36397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt64_32 0,limm,limm 00110110001110010111111110111110. */ +{ "fcvt64_32", 0x36397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fcvt64_32<.cc> 0,limm,limm 001101101111100101111111100QQQQQ. */ +{ "fcvt64_32", 0x36F97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, CVT, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdadd a,b,c 00110bbb001100010BBBCCCCCCAAAAAA. */ +{ "fdadd", 0x30310000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fdadd 0,b,c 00110bbb001100010BBBCCCCCC111110. */ +{ "fdadd", 0x3031003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fdadd<.cc> b,b,c 00110bbb111100010BBBCCCCCC0QQQQQ. */ +{ "fdadd", 0x30F10000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fdadd a,b,u6 00110bbb011100010BBBuuuuuuAAAAAA. */ +{ "fdadd", 0x30710000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fdadd 0,b,u6 00110bbb011100010BBBuuuuuu111110. */ +{ "fdadd", 0x3071003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fdadd<.cc> b,b,u6 00110bbb111100010BBBuuuuuu1QQQQQ. */ +{ "fdadd", 0x30F10020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fdadd b,b,s12 00110bbb101100010BBBssssssSSSSSS. */ +{ "fdadd", 0x30B10000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fdadd a,limm,c 00110110001100010111CCCCCCAAAAAA. */ +{ "fdadd", 0x36317000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fdadd a,b,limm 00110bbb001100010BBB111110AAAAAA. */ +{ "fdadd", 0x30310F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fdadd 0,limm,c 00110110001100010111CCCCCC111110. */ +{ "fdadd", 0x3631703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fdadd 0,b,limm 00110bbb001100010BBB111110111110. */ +{ "fdadd", 0x30310FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fdadd<.cc> b,b,limm 00110bbb111100010BBB1111100QQQQQ. */ +{ "fdadd", 0x30F10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fdadd<.cc> 0,limm,c 00110110111100010111CCCCCC0QQQQQ. */ +{ "fdadd", 0x36F17000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fdadd a,limm,u6 00110110011100010111uuuuuuAAAAAA. */ +{ "fdadd", 0x36717000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdadd 0,limm,u6 00110110011100010111uuuuuu111110. */ +{ "fdadd", 0x3671703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdadd<.cc> 0,limm,u6 00110110111100010111uuuuuu1QQQQQ. */ +{ "fdadd", 0x36F17020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fdadd 0,limm,s12 00110110101100010111ssssssSSSSSS. */ +{ "fdadd", 0x36B17000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fdadd a,limm,limm 00110110001100010111111110AAAAAA. */ +{ "fdadd", 0x36317F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fdadd 0,limm,limm 00110110001100010111111110111110. */ +{ "fdadd", 0x36317FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fdadd<.cc> 0,limm,limm 001101101111000101111111100QQQQQ. */ +{ "fdadd", 0x36F17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdcmp b,c 00110bbb001100111BBBCCCCCC000000. */ +{ "fdcmp", 0x30338000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, + +/* fdcmp<.cc> b,c 00110bbb111100111BBBCCCCCC0QQQQQ. */ +{ "fdcmp", 0x30F38000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { C_CC }}, + +/* fdcmp b,u6 00110bbb011100111BBBuuuuuu000000. */ +{ "fdcmp", 0x30738000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }}, + +/* fdcmp<.cc> b,u6 00110bbb111100111BBBuuuuuu1QQQQQ. */ +{ "fdcmp", 0x30F38020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { C_CC }}, + +/* fdcmp b,s12 00110bbb101100111BBBssssssSSSSSS. */ +{ "fdcmp", 0x30B38000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, SIMM12_20 }, { 0 }}, + +/* fdcmp limm,c 00110110001100111111CCCCCC000000. */ +{ "fdcmp", 0x3633F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { 0 }}, + +/* fdcmp b,limm 00110bbb001100111BBB111110000000. */ +{ "fdcmp", 0x30338F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }}, + +/* fdcmp<.cc> b,limm 00110bbb111100111BBB1111100QQQQQ. */ +{ "fdcmp", 0x30F38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { C_CC }}, + +/* fdcmp<.cc> limm,c 00110110111100111111CCCCCC0QQQQQ. */ +{ "fdcmp", 0x36F3F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { C_CC }}, + +/* fdcmp limm,u6 00110110011100111111uuuuuu000000. */ +{ "fdcmp", 0x3673F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { 0 }}, + +/* fdcmp<.cc> limm,u6 00110110111100111111uuuuuu1QQQQQ. */ +{ "fdcmp", 0x36F3F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { C_CC }}, + +/* fdcmp limm,s12 00110110101100111111ssssssSSSSSS. */ +{ "fdcmp", 0x36B3F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, SIMM12_20 }, { 0 }}, + +/* fdcmp limm,limm 00110110001100111111111110000000. */ +{ "fdcmp", 0x3633FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { 0 }}, + +/* fdcmp<.cc> limm,limm 001101101111001111111111100QQQQQ. */ +{ "fdcmp", 0x36F3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { C_CC }}, + +/* fdcmpf b,c 00110bbb001101001BBBCCCCCC000000. */ +{ "fdcmpf", 0x30348000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, + +/* fdcmpf<.cc> b,c 00110bbb111101001BBBCCCCCC0QQQQQ. */ +{ "fdcmpf", 0x30F48000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { C_CC }}, + +/* fdcmpf b,u6 00110bbb011101001BBBuuuuuu000000. */ +{ "fdcmpf", 0x30748000, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }}, + +/* fdcmpf<.cc> b,u6 00110bbb111101001BBBuuuuuu1QQQQQ. */ +{ "fdcmpf", 0x30F48020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { C_CC }}, + +/* fdcmpf b,s12 00110bbb101101001BBBssssssSSSSSS. */ +{ "fdcmpf", 0x30B48000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, SIMM12_20 }, { 0 }}, + +/* fdcmpf limm,c 00110110001101001111CCCCCC000000. */ +{ "fdcmpf", 0x3634F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { 0 }}, + +/* fdcmpf b,limm 00110bbb001101001BBB111110000000. */ +{ "fdcmpf", 0x30348F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }}, + +/* fdcmpf<.cc> b,limm 00110bbb111101001BBB1111100QQQQQ. */ +{ "fdcmpf", 0x30F48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { C_CC }}, + +/* fdcmpf<.cc> limm,c 00110110111101001111CCCCCC0QQQQQ. */ +{ "fdcmpf", 0x36F4F000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, RC }, { C_CC }}, + +/* fdcmpf limm,u6 00110110011101001111uuuuuu000000. */ +{ "fdcmpf", 0x3674F000, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { 0 }}, + +/* fdcmpf<.cc> limm,u6 00110110111101001111uuuuuu1QQQQQ. */ +{ "fdcmpf", 0x36F4F020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, UIMM6_20 }, { C_CC }}, + +/* fdcmpf limm,s12 00110110101101001111ssssssSSSSSS. */ +{ "fdcmpf", 0x36B4F000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, SIMM12_20 }, { 0 }}, + +/* fdcmpf limm,limm 00110110001101001111111110000000. */ +{ "fdcmpf", 0x3634FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { 0 }}, + +/* fdcmpf<.cc> limm,limm 001101101111010011111111100QQQQQ. */ +{ "fdcmpf", 0x36F4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { LIMM, LIMMdup }, { C_CC }}, + +/* fddiv a,b,c 00110bbb001101110BBBCCCCCCAAAAAA. */ +{ "fddiv", 0x30370000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fddiv 0,b,c 00110bbb001101110BBBCCCCCC111110. */ +{ "fddiv", 0x3037003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fddiv<.cc> b,b,c 00110bbb111101110BBBCCCCCC0QQQQQ. */ +{ "fddiv", 0x30F70000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fddiv a,b,u6 00110bbb011101110BBBuuuuuuAAAAAA. */ +{ "fddiv", 0x30770000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fddiv 0,b,u6 00110bbb011101110BBBuuuuuu111110. */ +{ "fddiv", 0x3077003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fddiv<.cc> b,b,u6 00110bbb111101110BBBuuuuuu1QQQQQ. */ +{ "fddiv", 0x30F70020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fddiv b,b,s12 00110bbb101101110BBBssssssSSSSSS. */ +{ "fddiv", 0x30B70000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fddiv a,limm,c 00110110001101110111CCCCCCAAAAAA. */ +{ "fddiv", 0x36377000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fddiv a,b,limm 00110bbb001101110BBB111110AAAAAA. */ +{ "fddiv", 0x30370F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fddiv 0,limm,c 00110110001101110111CCCCCC111110. */ +{ "fddiv", 0x3637703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fddiv 0,b,limm 00110bbb001101110BBB111110111110. */ +{ "fddiv", 0x30370FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fddiv<.cc> b,b,limm 00110bbb111101110BBB1111100QQQQQ. */ +{ "fddiv", 0x30F70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fddiv<.cc> 0,limm,c 00110110111101110111CCCCCC0QQQQQ. */ +{ "fddiv", 0x36F77000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fddiv a,limm,u6 00110110011101110111uuuuuuAAAAAA. */ +{ "fddiv", 0x36777000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fddiv 0,limm,u6 00110110011101110111uuuuuu111110. */ +{ "fddiv", 0x3677703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fddiv<.cc> 0,limm,u6 00110110111101110111uuuuuu1QQQQQ. */ +{ "fddiv", 0x36F77020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fddiv 0,limm,s12 00110110101101110111ssssssSSSSSS. */ +{ "fddiv", 0x36B77000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fddiv a,limm,limm 00110110001101110111111110AAAAAA. */ +{ "fddiv", 0x36377F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fddiv 0,limm,limm 00110110001101110111111110111110. */ +{ "fddiv", 0x36377FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fddiv<.cc> 0,limm,limm 001101101111011101111111100QQQQQ. */ +{ "fddiv", 0x36F77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdmadd a,b,c 00110bbb001101010BBBCCCCCCAAAAAA. */ +{ "fdmadd", 0x30350000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fdmadd 0,b,c 00110bbb001101010BBBCCCCCC111110. */ +{ "fdmadd", 0x3035003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fdmadd<.cc> b,b,c 00110bbb111101010BBBCCCCCC0QQQQQ. */ +{ "fdmadd", 0x30F50000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fdmadd a,b,u6 00110bbb011101010BBBuuuuuuAAAAAA. */ +{ "fdmadd", 0x30750000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fdmadd 0,b,u6 00110bbb011101010BBBuuuuuu111110. */ +{ "fdmadd", 0x3075003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fdmadd<.cc> b,b,u6 00110bbb111101010BBBuuuuuu1QQQQQ. */ +{ "fdmadd", 0x30F50020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fdmadd b,b,s12 00110bbb101101010BBBssssssSSSSSS. */ +{ "fdmadd", 0x30B50000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fdmadd a,limm,c 00110110001101010111CCCCCCAAAAAA. */ +{ "fdmadd", 0x36357000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fdmadd a,b,limm 00110bbb001101010BBB111110AAAAAA. */ +{ "fdmadd", 0x30350F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fdmadd 0,limm,c 00110110001101010111CCCCCC111110. */ +{ "fdmadd", 0x3635703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fdmadd 0,b,limm 00110bbb001101010BBB111110111110. */ +{ "fdmadd", 0x30350FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fdmadd<.cc> b,b,limm 00110bbb111101010BBB1111100QQQQQ. */ +{ "fdmadd", 0x30F50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fdmadd<.cc> 0,limm,c 00110110111101010111CCCCCC0QQQQQ. */ +{ "fdmadd", 0x36F57000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fdmadd a,limm,u6 00110110011101010111uuuuuuAAAAAA. */ +{ "fdmadd", 0x36757000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmadd 0,limm,u6 00110110011101010111uuuuuu111110. */ +{ "fdmadd", 0x3675703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmadd<.cc> 0,limm,u6 00110110111101010111uuuuuu1QQQQQ. */ +{ "fdmadd", 0x36F57020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fdmadd 0,limm,s12 00110110101101010111ssssssSSSSSS. */ +{ "fdmadd", 0x36B57000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fdmadd a,limm,limm 00110110001101010111111110AAAAAA. */ +{ "fdmadd", 0x36357F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fdmadd 0,limm,limm 00110110001101010111111110111110. */ +{ "fdmadd", 0x36357FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fdmadd<.cc> 0,limm,limm 001101101111010101111111100QQQQQ. */ +{ "fdmadd", 0x36F57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdmsub a,b,c 00110bbb001101100BBBCCCCCCAAAAAA. */ +{ "fdmsub", 0x30360000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fdmsub 0,b,c 00110bbb001101100BBBCCCCCC111110. */ +{ "fdmsub", 0x3036003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fdmsub<.cc> b,b,c 00110bbb111101100BBBCCCCCC0QQQQQ. */ +{ "fdmsub", 0x30F60000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fdmsub a,b,u6 00110bbb011101100BBBuuuuuuAAAAAA. */ +{ "fdmsub", 0x30760000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fdmsub 0,b,u6 00110bbb011101100BBBuuuuuu111110. */ +{ "fdmsub", 0x3076003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fdmsub<.cc> b,b,u6 00110bbb111101100BBBuuuuuu1QQQQQ. */ +{ "fdmsub", 0x30F60020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fdmsub b,b,s12 00110bbb101101100BBBssssssSSSSSS. */ +{ "fdmsub", 0x30B60000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fdmsub a,limm,c 00110110001101100111CCCCCCAAAAAA. */ +{ "fdmsub", 0x36367000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fdmsub a,b,limm 00110bbb001101100BBB111110AAAAAA. */ +{ "fdmsub", 0x30360F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fdmsub 0,limm,c 00110110001101100111CCCCCC111110. */ +{ "fdmsub", 0x3636703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fdmsub 0,b,limm 00110bbb001101100BBB111110111110. */ +{ "fdmsub", 0x30360FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fdmsub<.cc> b,b,limm 00110bbb111101100BBB1111100QQQQQ. */ +{ "fdmsub", 0x30F60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fdmsub<.cc> 0,limm,c 00110110111101100111CCCCCC0QQQQQ. */ +{ "fdmsub", 0x36F67000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fdmsub a,limm,u6 00110110011101100111uuuuuuAAAAAA. */ +{ "fdmsub", 0x36767000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmsub 0,limm,u6 00110110011101100111uuuuuu111110. */ +{ "fdmsub", 0x3676703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmsub<.cc> 0,limm,u6 00110110111101100111uuuuuu1QQQQQ. */ +{ "fdmsub", 0x36F67020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fdmsub 0,limm,s12 00110110101101100111ssssssSSSSSS. */ +{ "fdmsub", 0x36B67000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fdmsub a,limm,limm 00110110001101100111111110AAAAAA. */ +{ "fdmsub", 0x36367F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fdmsub 0,limm,limm 00110110001101100111111110111110. */ +{ "fdmsub", 0x36367FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fdmsub<.cc> 0,limm,limm 001101101111011001111111100QQQQQ. */ +{ "fdmsub", 0x36F67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdmul a,b,c 00110bbb001100000BBBCCCCCCAAAAAA. */ +{ "fdmul", 0x30300000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fdmul 0,b,c 00110bbb001100000BBBCCCCCC111110. */ +{ "fdmul", 0x3030003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fdmul<.cc> b,b,c 00110bbb111100000BBBCCCCCC0QQQQQ. */ +{ "fdmul", 0x30F00000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fdmul a,b,u6 00110bbb011100000BBBuuuuuuAAAAAA. */ +{ "fdmul", 0x30700000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fdmul 0,b,u6 00110bbb011100000BBBuuuuuu111110. */ +{ "fdmul", 0x3070003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fdmul<.cc> b,b,u6 00110bbb111100000BBBuuuuuu1QQQQQ. */ +{ "fdmul", 0x30F00020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fdmul b,b,s12 00110bbb101100000BBBssssssSSSSSS. */ +{ "fdmul", 0x30B00000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fdmul a,limm,c 00110110001100000111CCCCCCAAAAAA. */ +{ "fdmul", 0x36307000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fdmul a,b,limm 00110bbb001100000BBB111110AAAAAA. */ +{ "fdmul", 0x30300F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fdmul 0,limm,c 00110110001100000111CCCCCC111110. */ +{ "fdmul", 0x3630703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fdmul 0,b,limm 00110bbb001100000BBB111110111110. */ +{ "fdmul", 0x30300FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fdmul<.cc> b,b,limm 00110bbb111100000BBB1111100QQQQQ. */ +{ "fdmul", 0x30F00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fdmul<.cc> 0,limm,c 00110110111100000111CCCCCC0QQQQQ. */ +{ "fdmul", 0x36F07000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fdmul a,limm,u6 00110110011100000111uuuuuuAAAAAA. */ +{ "fdmul", 0x36707000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmul 0,limm,u6 00110110011100000111uuuuuu111110. */ +{ "fdmul", 0x3670703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdmul<.cc> 0,limm,u6 00110110111100000111uuuuuu1QQQQQ. */ +{ "fdmul", 0x36F07020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fdmul 0,limm,s12 00110110101100000111ssssssSSSSSS. */ +{ "fdmul", 0x36B07000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fdmul a,limm,limm 00110110001100000111111110AAAAAA. */ +{ "fdmul", 0x36307F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fdmul 0,limm,limm 00110110001100000111111110111110. */ +{ "fdmul", 0x36307FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fdmul<.cc> 0,limm,limm 001101101111000001111111100QQQQQ. */ +{ "fdmul", 0x36F07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fdsqrt b,c 00110bbb001011110BBBCCCCCC000001. */ +{ "fdsqrt", 0x302F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RC }, { 0 }}, + +/* fdsqrt 0,c 00110110001011110111CCCCCC000001. */ +{ "fdsqrt", 0x362F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RC }, { 0 }}, + +/* fdsqrt b,u6 00110bbb011011110BBBuuuuuu000001. */ +{ "fdsqrt", 0x306F0001, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, UIMM6_20 }, { 0 }}, + +/* fdsqrt 0,u6 00110110011011110111uuuuuu000001. */ +{ "fdsqrt", 0x366F7001, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, UIMM6_20 }, { 0 }}, + +/* fdsqrt b,limm 00110bbb001011110BBB111110000001. */ +{ "fdsqrt", 0x302F0F81, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, LIMM }, { 0 }}, + +/* fdsqrt 0,limm 00110110001011110111111110000001. */ +{ "fdsqrt", 0x362F7F81, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM }, { 0 }}, + +/* fdsub a,b,c 00110bbb001100100BBBCCCCCCAAAAAA. */ +{ "fdsub", 0x30320000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, RC }, { 0 }}, + +/* fdsub 0,b,c 00110bbb001100100BBBCCCCCC111110. */ +{ "fdsub", 0x3032003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, RC }, { 0 }}, + +/* fdsub<.cc> b,b,c 00110bbb111100100BBBCCCCCC0QQQQQ. */ +{ "fdsub", 0x30F20000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, RC }, { C_CC }}, + +/* fdsub a,b,u6 00110bbb011100100BBBuuuuuuAAAAAA. */ +{ "fdsub", 0x30720000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fdsub 0,b,u6 00110bbb011100100BBBuuuuuu111110. */ +{ "fdsub", 0x3072003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fdsub<.cc> b,b,u6 00110bbb111100100BBBuuuuuu1QQQQQ. */ +{ "fdsub", 0x30F20020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fdsub b,b,s12 00110bbb101100100BBBssssssSSSSSS. */ +{ "fdsub", 0x30B20000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fdsub a,limm,c 00110110001100100111CCCCCCAAAAAA. */ +{ "fdsub", 0x36327000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, RC }, { 0 }}, + +/* fdsub a,b,limm 00110bbb001100100BBB111110AAAAAA. */ +{ "fdsub", 0x30320F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, RB, LIMM }, { 0 }}, + +/* fdsub 0,limm,c 00110110001100100111CCCCCC111110. */ +{ "fdsub", 0x3632703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { 0 }}, + +/* fdsub 0,b,limm 00110bbb001100100BBB111110111110. */ +{ "fdsub", 0x30320FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, RB, LIMM }, { 0 }}, + +/* fdsub<.cc> b,b,limm 00110bbb111100100BBB1111100QQQQQ. */ +{ "fdsub", 0x30F20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fdsub<.cc> 0,limm,c 00110110111100100111CCCCCC0QQQQQ. */ +{ "fdsub", 0x36F27000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, RC }, { C_CC }}, + +/* fdsub a,limm,u6 00110110011100100111uuuuuuAAAAAA. */ +{ "fdsub", 0x36727000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdsub 0,limm,u6 00110110011100100111uuuuuu111110. */ +{ "fdsub", 0x3672703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fdsub<.cc> 0,limm,u6 00110110111100100111uuuuuu1QQQQQ. */ +{ "fdsub", 0x36F27020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fdsub 0,limm,s12 00110110101100100111ssssssSSSSSS. */ +{ "fdsub", 0x36B27000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fdsub a,limm,limm 00110110001100100111111110AAAAAA. */ +{ "fdsub", 0x36327F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fdsub 0,limm,limm 00110110001100100111111110111110. */ +{ "fdsub", 0x36327FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fdsub<.cc> 0,limm,limm 001101101111001001111111100QQQQQ. */ +{ "fdsub", 0x36F27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* ffs<.f> b,c 00101bbb00101111FBBBCCCCCC010010. */ +{ "ffs", 0x282F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }}, + +/* ffs<.f> 0,c 0010111000101111F111CCCCCC010010. */ +{ "ffs", 0x2E2F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }}, + +/* ffs<.f> b,u6 00101bbb01101111FBBBuuuuuu010010. */ +{ "ffs", 0x286F0012, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }}, + +/* ffs<.f> 0,u6 0010111001101111F111uuuuuu010010. */ +{ "ffs", 0x2E6F7012, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }}, + +/* ffs<.f> b,limm 00101bbb00101111FBBB111110010010. */ +{ "ffs", 0x282F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }}, + +/* ffs<.f> 0,limm 0010111000101111F111111110010010. */ +{ "ffs", 0x2E2F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }}, + +/* flag c 00100RRR001010010RRRCCCCCCRRRRRR. */ +{ "flag", 0x20290000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }}, + +/* flag<.cc> c 00100RRR111010010RRRCCCCCC0QQQQQ. */ +{ "flag", 0x20E90000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { C_CC }}, + +/* flag u6 00100RRR011010010RRRuuuuuuRRRRRR. */ +{ "flag", 0x20690000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }}, + +/* flag<.cc> u6 00100RRR111010010RRRuuuuuu1QQQQQ. */ +{ "flag", 0x20E90020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { C_CC }}, + +/* flag s12 00100RRR101010010RRRssssssSSSSSS. */ +{ "flag", 0x20A90000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { SIMM12_20 }, { 0 }}, + +/* flag limm 00100RRR001010010RRR111110RRRRRR. */ +{ "flag", 0x20290F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }}, + +/* flag<.cc> limm 00100RRR111010010RRR1111100QQQQQ. */ +{ "flag", 0x20E90F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { C_CC }}, + +/* flagacc c 00101100001011111000CCCCCC111111. */ +{ "flagacc", 0x2C2F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }}, + +/* flagacc u6 00101100011011111000uuuuuu111111. */ +{ "flagacc", 0x2C6F803F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }}, + +/* fls<.f> b,c 00101bbb00101111FBBBCCCCCC010011. */ +{ "fls", 0x282F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }}, + +/* fls<.f> 0,c 0010111000101111F111CCCCCC010011. */ +{ "fls", 0x2E2F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }}, + +/* fls<.f> b,u6 00101bbb01101111FBBBuuuuuu010011. */ +{ "fls", 0x286F0013, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }}, + +/* fls<.f> 0,u6 0010111001101111F111uuuuuu010011. */ +{ "fls", 0x2E6F7013, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }}, + +/* fls<.f> b,limm 00101bbb00101111FBBB111110010011. */ +{ "fls", 0x282F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }}, + +/* fls<.f> 0,limm 0010111000101111F111111110010011. */ +{ "fls", 0x2E2F7F93, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }}, + +/* fmul<.f> a,b,c 00110bbb00000000FBBBCCCCCCAAAAAA. */ +{ "fmul", 0x30000000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }}, + +/* fmul<.f> 0,b,c 00110bbb00000000FBBBCCCCCC111110. */ +{ "fmul", 0x3000003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }}, + +/* fmul<.f><.cc> b,b,c 00110bbb11000000FBBBCCCCCC0QQQQQ. */ +{ "fmul", 0x30C00000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* fmul<.f> a,b,u6 00110bbb01000000FBBBuuuuuuAAAAAA. */ +{ "fmul", 0x30400000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* fmul<.f> 0,b,u6 00110bbb01000000FBBBuuuuuu111110. */ +{ "fmul", 0x3040003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* fmul<.f><.cc> b,b,u6 00110bbb11000000FBBBuuuuuu1QQQQQ. */ +{ "fmul", 0x30C00020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* fmul<.f> b,b,s12 00110bbb10000000FBBBssssssSSSSSS. */ +{ "fmul", 0x30800000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* fmul<.f> a,limm,c 0011011000000000F111CCCCCCAAAAAA. */ +{ "fmul", 0x36007000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }}, + +/* fmul<.f> a,b,limm 00110bbb00000000FBBB111110AAAAAA. */ +{ "fmul", 0x30000F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }}, + +/* fmul<.f> 0,limm,c 0011011000000000F111CCCCCC111110. */ +{ "fmul", 0x3600703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }}, + +/* fmul<.f> 0,b,limm 00110bbb00000000FBBB111110111110. */ +{ "fmul", 0x30000FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,c 0011011011000000F111CCCCCC0QQQQQ. */ +{ "fmul", 0x36C07000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* fmul<.f><.cc> b,b,limm 00110bbb11000000FBBB1111100QQQQQ. */ +{ "fmul", 0x30C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* fmul<.f> a,limm,u6 0011011001000000F111uuuuuuAAAAAA. */ +{ "fmul", 0x36407000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* fmul<.f> 0,limm,u6 0011011001000000F111uuuuuu111110. */ +{ "fmul", 0x3640703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,u6 0011011011000000F111uuuuuu1QQQQQ. */ +{ "fmul", 0x36C07020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* fmul<.f> 0,limm,s12 0011011010000000F111ssssssSSSSSS. */ +{ "fmul", 0x36807000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* fmul<.f> a,limm,limm 0011011000000000F111111110AAAAAA. */ +{ "fmul", 0x36007F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* fmul<.f> 0,limm,limm 0011011000000000F111111110111110. */ +{ "fmul", 0x36007FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* fmul<.f><.cc> 0,limm,limm 0011011011000000F1111111100QQQQQ. */ +{ "fmul", 0x36C07F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* fsadd a,b,c 00110bbb000000010BBBCCCCCCAAAAAA. */ +{ "fsadd", 0x30010000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fsadd 0,b,c 00110bbb000000010BBBCCCCCC111110. */ +{ "fsadd", 0x3001003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fsadd<.cc> b,b,c 00110bbb110000010BBBCCCCCC0QQQQQ. */ +{ "fsadd", 0x30C10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fsadd a,b,u6 00110bbb010000010BBBuuuuuuAAAAAA. */ +{ "fsadd", 0x30410000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fsadd 0,b,u6 00110bbb010000010BBBuuuuuu111110. */ +{ "fsadd", 0x3041003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fsadd<.cc> b,b,u6 00110bbb110000010BBBuuuuuu1QQQQQ. */ +{ "fsadd", 0x30C10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fsadd b,b,s12 00110bbb100000010BBBssssssSSSSSS. */ +{ "fsadd", 0x30810000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fsadd a,limm,c 00110110000000010111CCCCCCAAAAAA. */ +{ "fsadd", 0x36017000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fsadd a,b,limm 00110bbb000000010BBB111110AAAAAA. */ +{ "fsadd", 0x30010F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fsadd 0,limm,c 00110110000000010111CCCCCC111110. */ +{ "fsadd", 0x3601703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fsadd 0,b,limm 00110bbb000000010BBB111110111110. */ +{ "fsadd", 0x30010FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fsadd<.cc> b,b,limm 00110bbb110000010BBB1111100QQQQQ. */ +{ "fsadd", 0x30C10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fsadd<.cc> 0,limm,c 00110110110000010111CCCCCC0QQQQQ. */ +{ "fsadd", 0x36C17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fsadd a,limm,u6 00110110010000010111uuuuuuAAAAAA. */ +{ "fsadd", 0x36417000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsadd 0,limm,u6 00110110010000010111uuuuuu111110. */ +{ "fsadd", 0x3641703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsadd<.cc> 0,limm,u6 00110110110000010111uuuuuu1QQQQQ. */ +{ "fsadd", 0x36C17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fsadd 0,limm,s12 00110110100000010111ssssssSSSSSS. */ +{ "fsadd", 0x36817000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fsadd a,limm,limm 00110110000000010111111110AAAAAA. */ +{ "fsadd", 0x36017F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fsadd 0,limm,limm 00110110000000010111111110111110. */ +{ "fsadd", 0x36017FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fsadd<.cc> 0,limm,limm 001101101100000101111111100QQQQQ. */ +{ "fsadd", 0x36C17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fscmp b,c 00110bbb000000111BBBCCCCCC000000. */ +{ "fscmp", 0x30038000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }}, + +/* fscmp<.cc> b,c 00110bbb110000111BBBCCCCCC0QQQQQ. */ +{ "fscmp", 0x30C38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { C_CC }}, + +/* fscmp b,u6 00110bbb010000111BBBuuuuuu000000. */ +{ "fscmp", 0x30438000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }}, + +/* fscmp<.cc> b,u6 00110bbb110000111BBBuuuuuu1QQQQQ. */ +{ "fscmp", 0x30C38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { C_CC }}, + +/* fscmp b,s12 00110bbb100000111BBBssssssSSSSSS. */ +{ "fscmp", 0x30838000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, SIMM12_20 }, { 0 }}, + +/* fscmp limm,c 00110110000000111111CCCCCC000000. */ +{ "fscmp", 0x3603F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { 0 }}, + +/* fscmp b,limm 00110bbb000000111BBB111110000000. */ +{ "fscmp", 0x30038F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }}, + +/* fscmp<.cc> b,limm 00110bbb110000111BBB1111100QQQQQ. */ +{ "fscmp", 0x30C38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { C_CC }}, + +/* fscmp<.cc> limm,c 00110110110000111111CCCCCC0QQQQQ. */ +{ "fscmp", 0x36C3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { C_CC }}, + +/* fscmp limm,u6 00110110010000111111uuuuuu000000. */ +{ "fscmp", 0x3643F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { 0 }}, + +/* fscmp<.cc> limm,u6 00110110110000111111uuuuuu1QQQQQ. */ +{ "fscmp", 0x36C3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { C_CC }}, + +/* fscmp limm,s12 00110110100000111111ssssssSSSSSS. */ +{ "fscmp", 0x3683F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, SIMM12_20 }, { 0 }}, + +/* fscmp limm,limm 00110110000000111111111110000000. */ +{ "fscmp", 0x3603FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { 0 }}, + +/* fscmp<.cc> limm,limm 001101101100001111111111100QQQQQ. */ +{ "fscmp", 0x36C3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { C_CC }}, + +/* fscmpf b,c 00110bbb000001001BBBCCCCCC000000. */ +{ "fscmpf", 0x30048000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }}, + +/* fscmpf<.cc> b,c 00110bbb110001001BBBCCCCCC0QQQQQ. */ +{ "fscmpf", 0x30C48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { C_CC }}, + +/* fscmpf b,u6 00110bbb010001001BBBuuuuuu000000. */ +{ "fscmpf", 0x30448000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }}, + +/* fscmpf<.cc> b,u6 00110bbb110001001BBBuuuuuu1QQQQQ. */ +{ "fscmpf", 0x30C48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { C_CC }}, + +/* fscmpf b,s12 00110bbb100001001BBBssssssSSSSSS. */ +{ "fscmpf", 0x30848000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, SIMM12_20 }, { 0 }}, + +/* fscmpf limm,c 00110110000001001111CCCCCC000000. */ +{ "fscmpf", 0x3604F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { 0 }}, + +/* fscmpf b,limm 00110bbb000001001BBB111110000000. */ +{ "fscmpf", 0x30048F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }}, + +/* fscmpf<.cc> b,limm 00110bbb110001001BBB1111100QQQQQ. */ +{ "fscmpf", 0x30C48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { C_CC }}, + +/* fscmpf<.cc> limm,c 00110110110001001111CCCCCC0QQQQQ. */ +{ "fscmpf", 0x36C4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, RC }, { C_CC }}, + +/* fscmpf limm,u6 00110110010001001111uuuuuu000000. */ +{ "fscmpf", 0x3644F000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { 0 }}, + +/* fscmpf<.cc> limm,u6 00110110110001001111uuuuuu1QQQQQ. */ +{ "fscmpf", 0x36C4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, UIMM6_20 }, { C_CC }}, + +/* fscmpf limm,s12 00110110100001001111ssssssSSSSSS. */ +{ "fscmpf", 0x3684F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, SIMM12_20 }, { 0 }}, + +/* fscmpf limm,limm 00110110000001001111111110000000. */ +{ "fscmpf", 0x3604FF80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { 0 }}, + +/* fscmpf<.cc> limm,limm 001101101100010011111111100QQQQQ. */ +{ "fscmpf", 0x36C4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { LIMM, LIMMdup }, { C_CC }}, + +/* fsdiv a,b,c 00110bbb000001110BBBCCCCCCAAAAAA. */ +{ "fsdiv", 0x30070000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fsdiv 0,b,c 00110bbb000001110BBBCCCCCC111110. */ +{ "fsdiv", 0x3007003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fsdiv<.cc> b,b,c 00110bbb110001110BBBCCCCCC0QQQQQ. */ +{ "fsdiv", 0x30C70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fsdiv a,b,u6 00110bbb010001110BBBuuuuuuAAAAAA. */ +{ "fsdiv", 0x30470000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fsdiv 0,b,u6 00110bbb010001110BBBuuuuuu111110. */ +{ "fsdiv", 0x3047003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fsdiv<.cc> b,b,u6 00110bbb110001110BBBuuuuuu1QQQQQ. */ +{ "fsdiv", 0x30C70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fsdiv b,b,s12 00110bbb100001110BBBssssssSSSSSS. */ +{ "fsdiv", 0x30870000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fsdiv a,limm,c 00110110000001110111CCCCCCAAAAAA. */ +{ "fsdiv", 0x36077000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fsdiv a,b,limm 00110bbb000001110BBB111110AAAAAA. */ +{ "fsdiv", 0x30070F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fsdiv 0,limm,c 00110110000001110111CCCCCC111110. */ +{ "fsdiv", 0x3607703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fsdiv 0,b,limm 00110bbb000001110BBB111110111110. */ +{ "fsdiv", 0x30070FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fsdiv<.cc> b,b,limm 00110bbb110001110BBB1111100QQQQQ. */ +{ "fsdiv", 0x30C70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fsdiv<.cc> 0,limm,c 00110110110001110111CCCCCC0QQQQQ. */ +{ "fsdiv", 0x36C77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fsdiv a,limm,u6 00110110010001110111uuuuuuAAAAAA. */ +{ "fsdiv", 0x36477000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsdiv 0,limm,u6 00110110010001110111uuuuuu111110. */ +{ "fsdiv", 0x3647703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsdiv<.cc> 0,limm,u6 00110110110001110111uuuuuu1QQQQQ. */ +{ "fsdiv", 0x36C77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fsdiv 0,limm,s12 00110110100001110111ssssssSSSSSS. */ +{ "fsdiv", 0x36877000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fsdiv a,limm,limm 00110110000001110111111110AAAAAA. */ +{ "fsdiv", 0x36077F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fsdiv 0,limm,limm 00110110000001110111111110111110. */ +{ "fsdiv", 0x36077FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fsdiv<.cc> 0,limm,limm 001101101100011101111111100QQQQQ. */ +{ "fsdiv", 0x36C77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fsmadd a,b,c 00110bbb000001010BBBCCCCCCAAAAAA. */ +{ "fsmadd", 0x30050000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fsmadd 0,b,c 00110bbb000001010BBBCCCCCC111110. */ +{ "fsmadd", 0x3005003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fsmadd<.cc> b,b,c 00110bbb110001010BBBCCCCCC0QQQQQ. */ +{ "fsmadd", 0x30C50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fsmadd a,b,u6 00110bbb010001010BBBuuuuuuAAAAAA. */ +{ "fsmadd", 0x30450000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fsmadd 0,b,u6 00110bbb010001010BBBuuuuuu111110. */ +{ "fsmadd", 0x3045003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fsmadd<.cc> b,b,u6 00110bbb110001010BBBuuuuuu1QQQQQ. */ +{ "fsmadd", 0x30C50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fsmadd b,b,s12 00110bbb100001010BBBssssssSSSSSS. */ +{ "fsmadd", 0x30850000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fsmadd a,limm,c 00110110000001010111CCCCCCAAAAAA. */ +{ "fsmadd", 0x36057000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fsmadd a,b,limm 00110bbb000001010BBB111110AAAAAA. */ +{ "fsmadd", 0x30050F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fsmadd 0,limm,c 00110110000001010111CCCCCC111110. */ +{ "fsmadd", 0x3605703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fsmadd 0,b,limm 00110bbb000001010BBB111110111110. */ +{ "fsmadd", 0x30050FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fsmadd<.cc> b,b,limm 00110bbb110001010BBB1111100QQQQQ. */ +{ "fsmadd", 0x30C50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fsmadd<.cc> 0,limm,c 00110110110001010111CCCCCC0QQQQQ. */ +{ "fsmadd", 0x36C57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fsmadd a,limm,u6 00110110010001010111uuuuuuAAAAAA. */ +{ "fsmadd", 0x36457000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmadd 0,limm,u6 00110110010001010111uuuuuu111110. */ +{ "fsmadd", 0x3645703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmadd<.cc> 0,limm,u6 00110110110001010111uuuuuu1QQQQQ. */ +{ "fsmadd", 0x36C57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fsmadd 0,limm,s12 00110110100001010111ssssssSSSSSS. */ +{ "fsmadd", 0x36857000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fsmadd a,limm,limm 00110110000001010111111110AAAAAA. */ +{ "fsmadd", 0x36057F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fsmadd 0,limm,limm 00110110000001010111111110111110. */ +{ "fsmadd", 0x36057FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fsmadd<.cc> 0,limm,limm 001101101100010101111111100QQQQQ. */ +{ "fsmadd", 0x36C57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fsmsub a,b,c 00110bbb000001100BBBCCCCCCAAAAAA. */ +{ "fsmsub", 0x30060000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fsmsub 0,b,c 00110bbb000001100BBBCCCCCC111110. */ +{ "fsmsub", 0x3006003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fsmsub<.cc> b,b,c 00110bbb110001100BBBCCCCCC0QQQQQ. */ +{ "fsmsub", 0x30C60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fsmsub a,b,u6 00110bbb010001100BBBuuuuuuAAAAAA. */ +{ "fsmsub", 0x30460000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fsmsub 0,b,u6 00110bbb010001100BBBuuuuuu111110. */ +{ "fsmsub", 0x3046003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fsmsub<.cc> b,b,u6 00110bbb110001100BBBuuuuuu1QQQQQ. */ +{ "fsmsub", 0x30C60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fsmsub b,b,s12 00110bbb100001100BBBssssssSSSSSS. */ +{ "fsmsub", 0x30860000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fsmsub a,limm,c 00110110000001100111CCCCCCAAAAAA. */ +{ "fsmsub", 0x36067000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fsmsub a,b,limm 00110bbb000001100BBB111110AAAAAA. */ +{ "fsmsub", 0x30060F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fsmsub 0,limm,c 00110110000001100111CCCCCC111110. */ +{ "fsmsub", 0x3606703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fsmsub 0,b,limm 00110bbb000001100BBB111110111110. */ +{ "fsmsub", 0x30060FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fsmsub<.cc> b,b,limm 00110bbb110001100BBB1111100QQQQQ. */ +{ "fsmsub", 0x30C60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fsmsub<.cc> 0,limm,c 00110110110001100111CCCCCC0QQQQQ. */ +{ "fsmsub", 0x36C67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fsmsub a,limm,u6 00110110010001100111uuuuuuAAAAAA. */ +{ "fsmsub", 0x36467000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmsub 0,limm,u6 00110110010001100111uuuuuu111110. */ +{ "fsmsub", 0x3646703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmsub<.cc> 0,limm,u6 00110110110001100111uuuuuu1QQQQQ. */ +{ "fsmsub", 0x36C67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fsmsub 0,limm,s12 00110110100001100111ssssssSSSSSS. */ +{ "fsmsub", 0x36867000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fsmsub a,limm,limm 00110110000001100111111110AAAAAA. */ +{ "fsmsub", 0x36067F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fsmsub 0,limm,limm 00110110000001100111111110111110. */ +{ "fsmsub", 0x36067FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fsmsub<.cc> 0,limm,limm 001101101100011001111111100QQQQQ. */ +{ "fsmsub", 0x36C67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fsmul a,b,c 00110bbb000000000BBBCCCCCCAAAAAA. */ +{ "fsmul", 0x30000000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fsmul 0,b,c 00110bbb000000000BBBCCCCCC111110. */ +{ "fsmul", 0x3000003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fsmul<.cc> b,b,c 00110bbb110000000BBBCCCCCC0QQQQQ. */ +{ "fsmul", 0x30C00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fsmul a,b,u6 00110bbb010000000BBBuuuuuuAAAAAA. */ +{ "fsmul", 0x30400000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fsmul 0,b,u6 00110bbb010000000BBBuuuuuu111110. */ +{ "fsmul", 0x3040003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fsmul<.cc> b,b,u6 00110bbb110000000BBBuuuuuu1QQQQQ. */ +{ "fsmul", 0x30C00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fsmul b,b,s12 00110bbb100000000BBBssssssSSSSSS. */ +{ "fsmul", 0x30800000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fsmul a,limm,c 00110110000000000111CCCCCCAAAAAA. */ +{ "fsmul", 0x36007000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fsmul a,b,limm 00110bbb000000000BBB111110AAAAAA. */ +{ "fsmul", 0x30000F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fsmul 0,limm,c 00110110000000000111CCCCCC111110. */ +{ "fsmul", 0x3600703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fsmul 0,b,limm 00110bbb000000000BBB111110111110. */ +{ "fsmul", 0x30000FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fsmul<.cc> b,b,limm 00110bbb110000000BBB1111100QQQQQ. */ +{ "fsmul", 0x30C00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fsmul<.cc> 0,limm,c 00110110110000000111CCCCCC0QQQQQ. */ +{ "fsmul", 0x36C07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fsmul a,limm,u6 00110110010000000111uuuuuuAAAAAA. */ +{ "fsmul", 0x36407000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmul 0,limm,u6 00110110010000000111uuuuuu111110. */ +{ "fsmul", 0x3640703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fsmul<.cc> 0,limm,u6 00110110110000000111uuuuuu1QQQQQ. */ +{ "fsmul", 0x36C07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fsmul 0,limm,s12 00110110100000000111ssssssSSSSSS. */ +{ "fsmul", 0x36807000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fsmul a,limm,limm 00110110000000000111111110AAAAAA. */ +{ "fsmul", 0x36007F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fsmul 0,limm,limm 00110110000000000111111110111110. */ +{ "fsmul", 0x36007FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fsmul<.cc> 0,limm,limm 001101101100000001111111100QQQQQ. */ +{ "fsmul", 0x36C07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fssqrt b,c 00110bbb001011110BBBCCCCCC000000. */ +{ "fssqrt", 0x302F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RC }, { 0 }}, + +/* fssqrt 0,c 00110110001011110111CCCCCC000000. */ +{ "fssqrt", 0x362F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RC }, { 0 }}, + +/* fssqrt b,u6 00110bbb011011110BBBuuuuuu000000. */ +{ "fssqrt", 0x306F0000, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, UIMM6_20 }, { 0 }}, + +/* fssqrt 0,u6 00110110011011110111uuuuuu000000. */ +{ "fssqrt", 0x366F7000, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, UIMM6_20 }, { 0 }}, + +/* fssqrt b,limm 00110bbb001011110BBB111110000000. */ +{ "fssqrt", 0x302F0F80, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, LIMM }, { 0 }}, + +/* fssqrt 0,limm 00110110001011110111111110000000. */ +{ "fssqrt", 0x362F7F80, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM }, { 0 }}, + +/* fssub a,b,c 00110bbb000000100BBBCCCCCCAAAAAA. */ +{ "fssub", 0x30020000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, RC }, { 0 }}, + +/* fssub 0,b,c 00110bbb000000100BBBCCCCCC111110. */ +{ "fssub", 0x3002003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, RC }, { 0 }}, + +/* fssub<.cc> b,b,c 00110bbb110000100BBBCCCCCC0QQQQQ. */ +{ "fssub", 0x30C20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, RC }, { C_CC }}, + +/* fssub a,b,u6 00110bbb010000100BBBuuuuuuAAAAAA. */ +{ "fssub", 0x30420000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, UIMM6_20 }, { 0 }}, + +/* fssub 0,b,u6 00110bbb010000100BBBuuuuuu111110. */ +{ "fssub", 0x3042003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* fssub<.cc> b,b,u6 00110bbb110000100BBBuuuuuu1QQQQQ. */ +{ "fssub", 0x30C20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* fssub b,b,s12 00110bbb100000100BBBssssssSSSSSS. */ +{ "fssub", 0x30820000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* fssub a,limm,c 00110110000000100111CCCCCCAAAAAA. */ +{ "fssub", 0x36027000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, RC }, { 0 }}, + +/* fssub a,b,limm 00110bbb000000100BBB111110AAAAAA. */ +{ "fssub", 0x30020F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, RB, LIMM }, { 0 }}, + +/* fssub 0,limm,c 00110110000000100111CCCCCC111110. */ +{ "fssub", 0x3602703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { 0 }}, + +/* fssub 0,b,limm 00110bbb000000100BBB111110111110. */ +{ "fssub", 0x30020FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, RB, LIMM }, { 0 }}, + +/* fssub<.cc> b,b,limm 00110bbb110000100BBB1111100QQQQQ. */ +{ "fssub", 0x30C20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RB, RBdup, LIMM }, { C_CC }}, + +/* fssub<.cc> 0,limm,c 00110110110000100111CCCCCC0QQQQQ. */ +{ "fssub", 0x36C27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, RC }, { C_CC }}, + +/* fssub a,limm,u6 00110110010000100111uuuuuuAAAAAA. */ +{ "fssub", 0x36427000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* fssub 0,limm,u6 00110110010000100111uuuuuu111110. */ +{ "fssub", 0x3642703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* fssub<.cc> 0,limm,u6 00110110110000100111uuuuuu1QQQQQ. */ +{ "fssub", 0x36C27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* fssub 0,limm,s12 00110110100000100111ssssssSSSSSS. */ +{ "fssub", 0x36827000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* fssub a,limm,limm 00110110000000100111111110AAAAAA. */ +{ "fssub", 0x36027F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { RA, LIMM, LIMMdup }, { 0 }}, + +/* fssub 0,limm,limm 00110110000000100111111110111110. */ +{ "fssub", 0x36027FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* fssub<.cc> 0,limm,limm 001101101100001001111111100QQQQQ. */ +{ "fssub", 0x36C27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* fsub<.f> a,b,c 00110bbb00000010FBBBCCCCCCAAAAAA. */ +{ "fsub", 0x30020000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, RC }, { C_F }}, + +/* fsub<.f> 0,b,c 00110bbb00000010FBBBCCCCCC111110. */ +{ "fsub", 0x3002003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, RC }, { C_F }}, + +/* fsub<.f><.cc> b,b,c 00110bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "fsub", 0x30C20000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* fsub<.f> a,b,u6 00110bbb01000010FBBBuuuuuuAAAAAA. */ +{ "fsub", 0x30420000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, UIMM6_20 }, { C_F }}, + +/* fsub<.f> 0,b,u6 00110bbb01000010FBBBuuuuuu111110. */ +{ "fsub", 0x3042003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* fsub<.f><.cc> b,b,u6 00110bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "fsub", 0x30C20020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* fsub<.f> b,b,s12 00110bbb10000010FBBBssssssSSSSSS. */ +{ "fsub", 0x30820000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* fsub<.f> a,limm,c 0011011000000010F111CCCCCCAAAAAA. */ +{ "fsub", 0x36027000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, RC }, { C_F }}, + +/* fsub<.f> a,b,limm 00110bbb00000010FBBB111110AAAAAA. */ +{ "fsub", 0x30020F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, RB, LIMM }, { C_F }}, + +/* fsub<.f> 0,limm,c 0011011000000010F111CCCCCC111110. */ +{ "fsub", 0x3602703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F }}, + +/* fsub<.f> 0,b,limm 00110bbb00000010FBBB111110111110. */ +{ "fsub", 0x30020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, RB, LIMM }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,c 0011011011000010F111CCCCCC0QQQQQ. */ +{ "fsub", 0x36C27000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* fsub<.f><.cc> b,b,limm 00110bbb11000010FBBB1111100QQQQQ. */ +{ "fsub", 0x30C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* fsub<.f> a,limm,u6 0011011001000010F111uuuuuuAAAAAA. */ +{ "fsub", 0x36427000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* fsub<.f> 0,limm,u6 0011011001000010F111uuuuuu111110. */ +{ "fsub", 0x3642703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,u6 0011011011000010F111uuuuuu1QQQQQ. */ +{ "fsub", 0x36C27020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* fsub<.f> 0,limm,s12 0011011010000010F111ssssssSSSSSS. */ +{ "fsub", 0x36827000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* fsub<.f> a,limm,limm 0011011000000010F111111110AAAAAA. */ +{ "fsub", 0x36027F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { RA, LIMM, LIMMdup }, { C_F }}, + +/* fsub<.f> 0,limm,limm 0011011000000010F111111110111110. */ +{ "fsub", 0x36027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* fsub<.f><.cc> 0,limm,limm 0011011011000010F1111111100QQQQQ. */ +{ "fsub", 0x36C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, SP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* fxtr<.f> a,b,c 00110bbb00100110FBBBCCCCCCAAAAAA. */ +{ "fxtr", 0x30260000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* fxtr<.f><.cc> b,b,c 00110bbb11100110FBBBCCCCCC0QQQQQ. */ +{ "fxtr", 0x30E60000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* fxtr<.f> a,b,u6 00110bbb01100110FBBBuuuuuuAAAAAA. */ +{ "fxtr", 0x30660000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* fxtr<.f><.cc> b,b,u6 00110bbb11100110FBBBuuuuuu1QQQQQ. */ +{ "fxtr", 0x30E60020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* fxtr<.f> b,b,s12 00110bbb10100110FBBBssssssSSSSSS. */ +{ "fxtr", 0x30A60000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* fxtr<.f> a,limm,c 0011011000100110F111CCCCCCAAAAAA. */ +{ "fxtr", 0x36267000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* fxtr<.f> a,b,limm 00110bbb00100110FBBB111110AAAAAA. */ +{ "fxtr", 0x30260F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* fxtr<.f><.cc> b,b,limm 00110bbb11100110FBBB1111100QQQQQ. */ +{ "fxtr", 0x30E60F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* getacc b,c 00101bbb001011110BBBCCCCCC011000. */ +{ "getacc", 0x282F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* getacc 0,c 00101110001011110111CCCCCC011000. */ +{ "getacc", 0x2E2F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* getacc b,u6 00101bbb011011110BBBuuuuuu011000. */ +{ "getacc", 0x286F0018, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* getacc 0,u6 00101110011011110111uuuuuu011000. */ +{ "getacc", 0x2E6F7018, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* getacc b,limm 00101bbb001011110BBB111110011000. */ +{ "getacc", 0x282F0F98, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* getacc 0,limm 00101110001011110111111110011000. */ +{ "getacc", 0x2E2F7F98, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* iaddr<.f> a,b,c 00110bbb00100111FBBBCCCCCCAAAAAA. */ +{ "iaddr", 0x30270000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* iaddr<.f><.cc> b,b,c 00110bbb11100111FBBBCCCCCC0QQQQQ. */ +{ "iaddr", 0x30E70000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* iaddr<.f> a,b,u6 00110bbb01100111FBBBuuuuuuAAAAAA. */ +{ "iaddr", 0x30670000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* iaddr<.f><.cc> b,b,u6 00110bbb11100111FBBBuuuuuu1QQQQQ. */ +{ "iaddr", 0x30E70020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* iaddr<.f> b,b,s12 00110bbb10100111FBBBssssssSSSSSS. */ +{ "iaddr", 0x30A70000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* iaddr<.f> a,limm,c 0011011000100111F111CCCCCCAAAAAA. */ +{ "iaddr", 0x36277000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* iaddr<.f> a,b,limm 00110bbb00100111FBBB111110AAAAAA. */ +{ "iaddr", 0x30270F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */ +{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* invld042e 00100RRRRR101110RRRRRRRRRRRRRRRR. */ +{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f0e 00100RRRRR101111RRRRRRRRRR00111R. */ +{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f12 00100RRRRR101111RRRRRRRRRR01001R. */ +{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f14 00100RRRRR101111RRRRRRRRRR0101RR. */ +{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f18 00100RRRRR101111RRRRRRRRRR011RRR. */ +{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f20 00100RRRRR101111RRRRRRRRRR10RRRR. */ +{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f30 00100RRRRR101111RRRRRRRRRR110RRR. */ +{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f38 00100RRRRR101111RRRRRRRRRR1110RR. */ +{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f3c 00100RRRRR101111RRRRRRRRRR11110R. */ +{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f3e 00100RRRRR101111RRRRRRRRRR111110. */ +{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f3f08 00100RRRRR101111R001RRRRRR111111. */ +{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f3f10 00100RRRRR101111R01RRRRRRR111111. */ +{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld042f3f20 00100RRRRR101111R1RRRRRRRR111111. */ +{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld0506 00101RRRRR00011RRRRRRRRRRRRRRRRR. */ +{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld050a 00101RRRRR00101RRRRRRRRRRRRRRRRR. */ +{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld050c 00101RRRRR00110RRRRRRRRRRRRRRRRR. */ +{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld051e 00101RRRRR01111RRRRRRRRRRRRRRRRR. */ +{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld0520 00101RRRRR100RRRRRRRRRRRRRRRRRRR. */ +{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld0528 00101RRRRR1010RRRRRRRRRRRRRRRRRR. */ +{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052c 00101RRRRR10110RRRRRRRRRRRRRRRRR. */ +{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052e 00101RRRRR101110RRRRRRRRRRRRRRRR. */ +{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f02 00101RRRRR101111RRRRRRRRRR00001R. */ +{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f04 00101RRRRR101111RRRRRRRRRR0001RR. */ +{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f14 00101RRRRR101111RRRRRRRRRR0101RR. */ +{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f18 00101RRRRR101111RRRRRRRRRR011RRR. */ +{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f20 00101RRRRR101111RRRRRRRRRR10RRRR. */ +{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f30 00101RRRRR101111RRRRRRRRRR110RRR. */ +{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f38 00101RRRRR101111RRRRRRRRRR1110RR. */ +{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f3c 00101RRRRR101111RRRRRRRRRR11110R. */ +{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f3e 00101RRRRR101111RRRRRRRRRR111110. */ +{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld052f3f00 00101RRRRR101111RRRRRRRRRR111111. */ +{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* invld07 00111RRRRRRRRRRRRRRRRRRRRRRRRRRR. */ +{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }}, + +/* j c 00100RRR001000000RRRCCCCCCRRRRRR. */ +{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* j BLINK 00100RRR001000000RRR011111RRRRRR. */ +{ "j", 0x202007C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }}, + +/* j.F ILINK1 00100RRR001000001RRR011101RRRRRR. */ +{ "j", 0x20208740, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK1, BRAKETdup }, { C_FHARD }}, + +/* j.F ILINK2 00100RRR001000001RRR011110RRRRRR. */ +{ "j", 0x20208780, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK2, BRAKETdup }, { C_FHARD }}, + +/* jcc c 00100RRR111000000RRRCCCCCC0QQQQQ. */ +{ "j", 0x20E00000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* jcc BLINK 00100RRR111000000RRR0111110QQQQQ. */ +{ "j", 0x20E007C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC }}, + +/* j.Fcc ILINK1 00100RRR111000001RRR0111010QQQQQ. */ +{ "j", 0x20E08740, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK1, BRAKETdup }, { C_FHARD, C_CC }}, + +/* j.Fcc ILINK2 00100RRR111000001RRR0111100QQQQQ. */ +{ "j", 0x20E08780, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, ILINK2, BRAKETdup }, { C_FHARD, C_CC }}, + +/* j.D c 00100RRR001000010RRRCCCCCCRRRRRR. */ +{ "j", 0x20210000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }}, + +/* j.D BLINK 00100RRR001000010RRR011111RRRRRR. */ +{ "j", 0x202107C0, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }}, + +/* jcc.D c 00100RRR111000010RRRCCCCCC0QQQQQ. */ +{ "j", 0x20E10000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }}, + +/* jcc.D BLINK 00100RRR111000010RRR0111110QQQQQ. */ +{ "j", 0x20E107C0, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }}, + +/* j c 00100RRR00100000RRRRCCCCCCRRRRRR. */ +{ "j", 0x20200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* j BLINK 00100RRR00100000RRRR011111RRRRRR. */ +{ "j", 0x202007C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { 0 }}, + +/* jcc c 00100RRR11100000RRRRCCCCCC0QQQQQ. */ +{ "j", 0x20E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* jcc BLINK 00100RRR11100000RRRR0111110QQQQQ. */ +{ "j", 0x20E007C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC }}, + +/* j.D c 00100RRR00100001RRRRCCCCCCRRRRRR. */ +{ "j", 0x20210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }}, + +/* j.D BLINK 00100RRR00100001RRRR011111RRRRRR. */ +{ "j", 0x202107C0, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_DHARD }}, + +/* jcc.D c 00100RRR11100001RRRRCCCCCC0QQQQQ. */ +{ "j", 0x20E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }}, + +/* jcc.D BLINK 00100RRR11100001RRRR0111110QQQQQ. */ +{ "j", 0x20E107C0, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK, BRAKETdup }, { C_CC, C_DHARD }}, + +/* j s12 00100RRR101000000RRRssssssSSSSSS. */ +{ "j", 0x20A00000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { 0 }}, + +/* j.D s12 00100RRR101000010RRRssssssSSSSSS. */ +{ "j", 0x20A10000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { C_DHARD }}, + +/* j s12 00100RRR10100000RRRRssssssSSSSSS. */ +{ "j", 0x20A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { 0 }}, + +/* j.D s12 00100RRR10100001RRRRssssssSSSSSS. */ +{ "j", 0x20A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { C_DHARD }}, + +/* j u6 00100RRR011000000RRRuuuuuuRRRRRR. */ +{ "j", 0x20600000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { 0 }}, + +/* jcc u6 00100RRR111000000RRRuuuuuu1QQQQQ. */ +{ "j", 0x20E00020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC }}, + +/* j.D u6 00100RRR011000010RRRuuuuuuRRRRRR. */ +{ "j", 0x20610000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_DHARD }}, + +/* jcc.D u6 00100RRR111000010RRRuuuuuu1QQQQQ. */ +{ "j", 0x20E10020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }}, + +/* j u6 00100RRR01100000RRRRuuuuuuRRRRRR. */ +{ "j", 0x20600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { 0 }}, + +/* jcc u6 00100RRR11100000RRRRuuuuuu1QQQQQ. */ +{ "j", 0x20E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC }}, + +/* j.D u6 00100RRR01100001RRRRuuuuuuRRRRRR. */ +{ "j", 0x20610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_DHARD }}, + +/* jcc.D u6 00100RRR11100001RRRRuuuuuu1QQQQQ. */ +{ "j", 0x20E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }}, + +/* j limm 00100RRR001000000RRR111110RRRRRR. */ +{ "j", 0x20200F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { 0 }}, + +/* jcc limm 00100RRR111000000RRR1111100QQQQQ. */ +{ "j", 0x20E00F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { C_CC }}, + +/* j limm 00100RRR00100000RRRR111110RRRRRR. */ +{ "j", 0x20200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { 0 }}, + +/* jcc limm 00100RRR11100000RRRR1111100QQQQQ. */ +{ "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }}, + +/* jeq_s BLINK 0111110011100000. */ +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* jeq_s BLINK 0111110011100000. */ +{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* jl c 00100RRR001000100RRRCCCCCCRRRRRR. */ +{ "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* jlcc c 00100RRR111000100RRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E20000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* jl.D c 00100RRR001000110RRRCCCCCCRRRRRR. */ +{ "jl", 0x20230000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }}, + +/* jlcc.D c 00100RRR111000110RRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E30000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }}, + +/* jl c 00100RRR00100010RRRRCCCCCCRRRRRR. */ +{ "jl", 0x20220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, + +/* jlcc c 00100RRR11100010RRRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC }}, + +/* jl.D c 00100RRR00100011RRRRCCCCCCRRRRRR. */ +{ "jl", 0x20230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_DHARD }}, + +/* jlcc.D c 00100RRR11100011RRRRCCCCCC0QQQQQ. */ +{ "jl", 0x20E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { C_CC, C_DHARD }}, + +/* jl s12 00100RRR101000100RRRssssssSSSSSS. */ +{ "jl", 0x20A20000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { 0 }}, + +/* jl.D s12 00100RRR101000110RRRssssssSSSSSS. */ +{ "jl", 0x20A30000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { SIMM12_20 }, { C_DHARD }}, + +/* jl s12 00100RRR10100010RRRRssssssSSSSSS. */ +{ "jl", 0x20A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { 0 }}, + +/* jl.D s12 00100RRR10100011RRRRssssssSSSSSS. */ +{ "jl", 0x20A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { SIMM12_20 }, { C_DHARD }}, + +/* jl u6 00100RRR011000100RRRuuuuuuRRRRRR. */ +{ "jl", 0x20620000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { 0 }}, + +/* jlcc u6 00100RRR111000100RRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E20020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC }}, + +/* jl.D u6 00100RRR011000110RRRuuuuuuRRRRRR. */ +{ "jl", 0x20630000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_DHARD }}, + +/* jlcc.D u6 00100RRR111000110RRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E30020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }}, + +/* jl u6 00100RRR01100010RRRRuuuuuuRRRRRR. */ +{ "jl", 0x20620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { 0 }}, + +/* jlcc u6 00100RRR11100010RRRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC }}, + +/* jl.D u6 00100RRR01100011RRRRuuuuuuRRRRRR. */ +{ "jl", 0x20630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_DHARD }}, + +/* jlcc.D u6 00100RRR11100011RRRRuuuuuu1QQQQQ. */ +{ "jl", 0x20E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { UIMM6_20 }, { C_CC, C_DHARD }}, + +/* jl limm 00100RRR001000100RRR111110RRRRRR. */ +{ "jl", 0x20220F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { 0 }}, + +/* jlcc limm 00100RRR111000100RRR1111100QQQQQ. */ +{ "jl", 0x20E20F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { LIMM }, { C_CC }}, + +/* jl limm 00100RRR00100010RRRR111110RRRRRR. */ +{ "jl", 0x20220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { 0 }}, + +/* jlcc limm 00100RRR11100010RRRR1111100QQQQQ. */ +{ "jl", 0x20E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }}, + +/* jli_s u10 010110uuuuuuuuuu. */ +{ "jli_s", 0x00005800, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD1, { UIMM10_6_S }, { 0 }}, + +/* jl_s b 01111bbb01000000. */ +{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, + +/* jl_s.D b 01111bbb01100000. */ +{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }}, + +/* jl_s b 01111bbb01000000. */ +{ "jl_s", 0x00007840, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, + +/* jl_s.D b 01111bbb01100000. */ +{ "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }}, + +/* jne_s BLINK 0111110111100000. */ +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* jne_s BLINK 0111110111100000. */ +{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* j_s b 01111bbb00000000. */ +{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, + +/* j_s.D b 01111bbb00100000. */ +{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }}, + +/* j_s BLINK 0111111011100000. */ +{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* j_s.D BLINK 0111111111100000. */ +{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }}, + +/* j_s b 01111bbb00000000. */ +{ "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }}, + +/* j_s.D b 01111bbb00100000. */ +{ "j_s", 0x00007820, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }}, + +/* j_s BLINK 0111111011100000. */ +{ "j_s", 0x00007EE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }}, + +/* j_s.D BLINK 0111111111100000. */ +{ "j_s", 0x00007FE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { C_DHARD }}, + +/* kflag c 00100RRR001010011RRRCCCCCCRRRRRR. */ +{ "kflag", 0x20298000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }}, + +/* kflag<.cc> c 00100RRR111010011RRRCCCCCC0QQQQQ. */ +{ "kflag", 0x20E98000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { C_CC }}, + +/* kflag u6 00100RRR011010011RRRuuuuuuRRRRRR. */ +{ "kflag", 0x20698000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }}, + +/* kflag<.cc> u6 00100RRR111010011RRRuuuuuu1QQQQQ. */ +{ "kflag", 0x20E98020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { C_CC }}, + +/* kflag s12 00100RRR101010011RRRssssssSSSSSS. */ +{ "kflag", 0x20A98000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { SIMM12_20 }, { 0 }}, + +/* kflag limm 00100RRR001010011RRR111110RRRRRR. */ +{ "kflag", 0x20298F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }}, + +/* kflag<.cc> limm 00100RRR111010011RRR1111100QQQQQ. */ +{ "kflag", 0x20E98F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { C_CC }}, + +/* ld<.di><.aa><.x><zz> a,b 00010bbb000000000BBBDaaZZXAAAAAA. */ +{ "ld", 0x10000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x><zz> a,b,c 00100bbbaa110ZZXDBBBCCCCCCAAAAAA. */ +{ "ld", 0x20300000, 0xF8380000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x><zz> 0,b 00010bbb000000000BBBDaaZZX111110. */ +{ "ld", 0x1000003E, 0xF8FF803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x><zz> 0,b,c 00100bbbaa110ZZXDBBBCCCCCC111110. */ +{ "ld", 0x2030003E, 0xF838003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x><zz> a,b,s9 00010bbbssssssssSBBBDaaZZXAAAAAA. */ +{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x><zz> 0,b,s9 00010bbbssssssssSBBBDaaZZX111110. */ +{ "ld", 0x1000003E, 0xF800003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.x><zz> a,limm 00010110000000000111DRRZZXAAAAAA. */ +{ "ld", 0x16007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, + +/* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */ +{ "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x><zz> a,limm,c 00100110aa110ZZXD111CCCCCCAAAAAA. */ +{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.x><zz> a,limm,c 00100110RR110ZZXD111CCCCCCAAAAAA. */ +{ "ld", 0x26307000, 0xFF387000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, + +/* ld<.di><.x><zz> 0,limm 00010110000000000111DRRZZX111110. */ +{ "ld", 0x1600703E, 0xFFFFF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_ZZ23, C_DI20, C_X25 }}, + +/* ld<.di><.aa><.x><zz> 0,b,limm 00100bbbaa110ZZXDBBB111110111110. */ +{ "ld", 0x20300FBE, 0xF8380FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x><zz> 0,limm,c 00100110aa110ZZXD111CCCCCC111110. */ +{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.x><zz> 0,limm,c 00100110RR110ZZXD111CCCCCC111110. */ +{ "ld", 0x2630703E, 0xFF38703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_ZZ13, C_DI16, C_X15 }}, + +/* ld<.di><.aa><.x><zz> a,limm,s9 00010110ssssssssS111DaaZZXAAAAAA. */ +{ "ld", 0x16007000, 0xFF007000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x><zz> 0,limm,s9 00010110ssssssssS111DaaZZX111110. */ +{ "ld", 0x1600703E, 0xFF00703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ23, C_DI20, C_AA21, C_X25 }}, + +/* ld<.di><.aa><.x><zz> a,limm,limm 00100110aa110ZZXD111111110AAAAAA. */ +{ "ld", 0x26307F80, 0xFF387FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ld<.di><.aa><.x><zz> 0,limm,limm 00100110aa110ZZXD111111110111110. */ +{ "ld", 0x26307FBE, 0xFF387FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_ZZ13, C_DI16, C_AA8, C_X15 }}, + +/* ldb_s a,b,c 01100bbbccc01aaa. */ +{ "ldb_s", 0x00006008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, + +/* ldb_s c,b,u5 10001bbbcccuuuuu. */ +{ "ldb_s", 0x00008800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }}, + +/* ldb_s b,SP,u7 11000bbb001uuuuu. */ +{ "ldb_s", 0x0000C020, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* ldb_s R0,GP,s9 1100101sssssssss. */ +{ "ldb_s", 0x0000CA00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM9_7_S, BRAKETdup }, { 0 }}, + +/* ldd<.di><.aa> a,b 00010bbb000000000BBBDaa110AAAAAA. */ +{ "ldd", 0x10000180, 0xF8FF81C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldd<.di><.aa> a,b,c 00100bbbaa110110DBBBCCCCCCAAAAAA. */ +{ "ldd", 0x20360000, 0xF83F0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }}, + +/* ldd<.di><.aa> 0,b 00010bbb000000000BBBDaa110111110. */ +{ "ldd", 0x100001BE, 0xF8FF81FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldd<.di><.aa> 0,b,c 00100bbbaa110110DBBBCCCCCC111110. */ +{ "ldd", 0x2036003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, RC, BRAKETdup }, { C_DI16, C_AA8 }}, + +/* ldd<.di><.aa> a,b,s9 00010bbbssssssssSBBBDaa110AAAAAA. */ +{ "ldd", 0x10000180, 0xF80001C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldd<.di><.aa> 0,b,s9 00010bbbssssssssSBBBDaa110111110. */ +{ "ldd", 0x100001BE, 0xF80001FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldd<.di> a,limm 00010110000000000111DRR110AAAAAA. */ +{ "ldd", 0x16007180, 0xFFFFF1C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, BRAKETdup }, { C_DI20 }}, + +/* ldd<.di><.aa> a,b,limm 00100bbbaa110110DBBB111110AAAAAA. */ +{ "ldd", 0x20360F80, 0xF83F0FC0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }}, + +/* ldd<.di> a,limm,c 00100110RR110110D111CCCCCCAAAAAA. */ +{ "ldd", 0x26367000, 0xFF3F7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }}, + +/* ldd<.di> 0,limm 00010110000000000111DRR110111110. */ +{ "ldd", 0x160071BE, 0xFFFFF1FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI20 }}, + +/* ldd<.di><.aa> 0,b,limm 00100bbbaa110110DBBB111110111110. */ +{ "ldd", 0x20360FBE, 0xF83F0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RB, LIMM, BRAKETdup }, { C_DI16, C_AA8 }}, + +/* ldd<.di> 0,limm,c 00100110RR110110D111CCCCCC111110. */ +{ "ldd", 0x2636703E, 0xFF3F703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, RC, BRAKETdup }, { C_DI16 }}, + +/* ldd<.di><.aa> a,limm,s9 00010110ssssssssS111Daa110AAAAAA. */ +{ "ldd", 0x16007180, 0xFF0071C0, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RAD, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldd<.di><.aa> 0,limm,s9 00010110ssssssssS111Daa110111110. */ +{ "ldd", 0x160071BE, 0xFF0071FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI20, C_AA21 }}, + +/* ldh_s a,b,c 01100bbbccc10aaa. */ +{ "ldh_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, + +/* ldh_s c,b,u6 10010bbbcccuuuuu. */ +{ "ldh_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, + +/* ldh_s.X c,b,u6 10011bbbcccuuuuu. */ +{ "ldh_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }}, + +/* ldh_s R0,GP,s10 1100110sssssssss. */ +{ "ldh_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }}, + +/* ldi b,c 00100bbb00100110RBBBCCCCCCRRRRRR. */ +{ "ldi", 0x20260000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* ldi 0,c 0010011000100110R111CCCCCCRRRRRR. */ +{ "ldi", 0x26267000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* ldi b,u6 00100bbb01100110RBBBuuuuuu000000. */ +{ "ldi", 0x20660000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* ldi 0,u6 0010011001100110R111uuuuuu000000. */ +{ "ldi", 0x26667000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* ldi<.cc> b,u6 00100bbb11100110RBBBuuuuuu1QQQQQ. */ +{ "ldi", 0x20E60020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, MEMORY, CD2, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }}, + +/* ldi<.cc> 0,u6 0010011011100110R111uuuuuu1QQQQQ. */ +{ "ldi", 0x26E67020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, MEMORY, CD2, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_CC }}, + +/* ldi b,s12 00100bbb10100110RBBBssssssSSSSSS. */ +{ "ldi", 0x20A60000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* ldi 0,s12 0010011010100110R111ssssssSSSSSS. */ +{ "ldi", 0x26A67000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* ldi b,limm 00100bbb00100110RBBB111110RRRRRR. */ +{ "ldi", 0x20260F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* ldi 0,limm 0010011000100110R111111110RRRRRR. */ +{ "ldi", 0x26267F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* ldi_s b,u7 01010bbbUUUU1uuu. */ +{ "ldi_s", 0x00005008, 0x0000F808, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RB_S, BRAKET, UIMM7_13_S, BRAKETdup }, { 0 }}, + +/* ldm a,u6,b 00101bbb01001100RBBBRuuuuuAAAAAA. */ +{ "ldm", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, RB }, { 0 }}, + +/* ldm 0,u6,b 00101bbb01001100RBBBRuuuuu111110. */ +{ "ldm", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, RB }, { 0 }}, + +/* ldm a,u6,limm 0010111001001100R111RuuuuuAAAAAA. */ +{ "ldm", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, LIMM }, { 0 }}, + +/* ldm 0,u6,limm 0010111001001100R111Ruuuuu111110. */ +{ "ldm", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }}, + +/* ldw_s a,b,c 01100bbbccc10aaa. */ +{ "ldw_s", 0x00006010, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, + +/* ldw_s c,b,u6 10010bbbcccuuuuu. */ +{ "ldw_s", 0x00009000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, + +/* ldw_s.X c,b,u6 10011bbbcccuuuuu. */ +{ "ldw_s", 0x00009800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { C_XHARD }}, + +/* ldw_s R0,GP,s10 1100110sssssssss. */ +{ "ldw_s", 0x0000CC00, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM10_A16_7_Sbis, BRAKETdup }, { 0 }}, + +/* ld_s a,b,c 01100bbbccc00aaa. */ +{ "ld_s", 0x00006000, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { 0 }}, + +/* ld_s.AS a,b,c 01001bbbccc00aaa. */ +{ "ld_s", 0x00004800, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { RA_S, BRAKET, RB_S, RC_S, BRAKETdup }, { C_AS }}, + +/* ld_s R0,h,u5 01000U00hhhuu1HH. */ +{ "ld_s", 0x00004004, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R0_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s R1,h,u5 01000U01hhhuu1HH. */ +{ "ld_s", 0x00004104, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R1_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s R2,h,u5 01000U10hhhuu1HH. */ +{ "ld_s", 0x00004204, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R2_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s R3,h,u5 01000U11hhhuu1HH. */ +{ "ld_s", 0x00004304, 0x0000FB04, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R3_S, BRAKET, RH_S, UIMM5_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s b,SP,u7 11000bbb000uuuuu. */ +{ "ld_s", 0x0000C000, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s c,b,u7 10000bbbcccuuuuu. */ +{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* ld_s b,PCL,u10 11010bbbuuuuuuuu. */ +{ "ld_s", 0x0000D000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, PCL_S, UIMM10_A32_8_S, BRAKETdup }, { 0 }}, + +/* ld_s R0,GP,s11 1100100sssssssss. */ +{ "ld_s", 0x0000C800, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { R0_S, BRAKET, GP_S, SIMM11_A32_7_S, BRAKETdup }, { 0 }}, + +/* ld_s R1,GP,s11 01010SSSSSS00sss. */ +{ "ld_s", 0x00005000, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R1_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }}, + +/* leave_s u7 11000UUU110uuuu0. */ +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RRANGE_EL, FP_EL, BLINK_EL, PCL_EL, BRAKETdup }, { 0 }}, +{ "leave_s", 0x0000C0C0, 0x0000F8E1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD1, { UIMM7_11_S }, { 0 }}, + +/* llock<.di> b,c 00100bbb00101111DBBBCCCCCC010000. */ +{ "llock", 0x202F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,c 0010011000101111D111CCCCCC010000. */ +{ "llock", 0x262F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* llock<.di> b,u6 00100bbb01101111DBBBuuuuuu010000. */ +{ "llock", 0x206F0010, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,u6 0010011001101111D111uuuuuu010000. */ +{ "llock", 0x266F7010, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* llock<.di> b,limm 00100bbb00101111DBBB111110010000. */ +{ "llock", 0x202F0F90, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* llock<.di> 0,limm 0010011000101111D111111110010000. */ +{ "llock", 0x262F7F90, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,c 00100bbb00101111DBBBCCCCCC010010. */ +{ "llockd", 0x202F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,c 0010011000101111D111CCCCCC010010. */ +{ "llockd", 0x262F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,u6 00100bbb01101111DBBBuuuuuu010010. */ +{ "llockd", 0x206F0012, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,u6 0010011001101111D111uuuuuu010010. */ +{ "llockd", 0x266F7012, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> b,limm 00100bbb00101111DBBB111110010010. */ +{ "llockd", 0x202F0F92, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* llockd<.di> 0,limm 0010011000101111D111111110010010. */ +{ "llockd", 0x262F7F92, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* lp s13 00100RRR101010000RRRssssssSSSSSS. */ +{ "lp", 0x20A80000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }}, + +/* lp s13 00100RRR10101000RRRRssssssSSSSSS. */ +{ "lp", 0x20A80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A16_20 }, { 0 }}, + +/* lp<cc> u7 00100RRR111010000RRRuuuuuu1QQQQQ. */ +{ "lp", 0x20E80020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }}, + +/* lp u7 00100RRR011010000RRRuuuuuuRRRRRR. */ +{ "lp", 0x20680000, 0xF8FF8000, ARC_OPCODE_ARC600, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }}, + +/* lp<cc> u7 00100RRR11101000RRRRuuuuuu1QQQQQ. */ +{ "lp", 0x20E80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { C_CC }}, + +/* lp u7 00100RRR01101000RRRRuuuuuuRRRRRR. */ +{ "lp", 0x20680000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { UIMM7_A16_20 }, { 0 }}, + +/* lr b,c 00100bbb001010100BBBCCCCCCRRRRRR. */ +{ "lr", 0x202A0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* lr 0,c 00100110001010100111CCCCCCRRRRRR. */ +{ "lr", 0x262A7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* lr b,c 00100bbb00101010RBBBCCCCCCRRRRRR. */ +{ "lr", 0x202A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* lr 0,c 0010011000101010R111CCCCCCRRRRRR. */ +{ "lr", 0x262A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* lr b,u6 00100bbb011010100BBBuuuuuu000000. */ +{ "lr", 0x206A0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* lr 0,u6 00100110011010100111uuuuuu000000. */ +{ "lr", 0x266A7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* lr b,u6 00100bbb01101010RBBBuuuuuu000000. */ +{ "lr", 0x206A0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* lr 0,u6 0010011001101010R111uuuuuu000000. */ +{ "lr", 0x266A7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* lr b,s12 00100bbb101010100BBBssssssSSSSSS. */ +{ "lr", 0x20AA0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* lr 0,s12 00100110101010100111ssssssSSSSSS. */ +{ "lr", 0x26AA7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* lr b,s12 00100bbb10101010RBBBssssssSSSSSS. */ +{ "lr", 0x20AA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* lr 0,s12 0010011010101010R111ssssssSSSSSS. */ +{ "lr", 0x26AA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* lr b,limm 00100bbb001010100BBB111110RRRRRR. */ +{ "lr", 0x202A0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* lr 0,limm 00100110001010100111111110RRRRRR. */ +{ "lr", 0x262A7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* lr b,limm 00100bbb00101010RBBB111110RRRRRR. */ +{ "lr", 0x202A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* lr 0,limm 0010011000101010R111111110RRRRRR. */ +{ "lr", 0x262A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { ZA, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* lsl16<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ +{ "lsl16", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }}, + +/* lsl16<.f> 0,c 0010111000101111F111CCCCCC001010. */ +{ "lsl16", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }}, + +/* lsl16<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ +{ "lsl16", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }}, + +/* lsl16<.f> 0,u6 0010111001101111F111uuuuuu001010. */ +{ "lsl16", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }}, + +/* lsl16<.f> b,limm 00101bbb00101111FBBB111110001010. */ +{ "lsl16", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }}, + +/* lsl16<.f> 0,limm 0010111000101111F111111110001010. */ +{ "lsl16", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }}, + +/* lsl8<.f> b,c 00101bbb00101111FBBBCCCCCC001111. */ +{ "lsl8", 0x282F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }}, + +/* lsl8<.f> 0,c 0010111000101111F111CCCCCC001111. */ +{ "lsl8", 0x2E2F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }}, + +/* lsl8<.f> b,u6 00101bbb01101111FBBBuuuuuu001111. */ +{ "lsl8", 0x286F000F, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* lsl8<.f> 0,u6 0010111001101111F111uuuuuu001111. */ +{ "lsl8", 0x2E6F700F, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* lsl8<.f> b,limm 00101bbb00101111FBBB111110001111. */ +{ "lsl8", 0x282F0F8F, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }}, + +/* lsl8<.f> 0,limm 0010111000101111F111111110001111. */ +{ "lsl8", 0x2E2F7F8F, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }}, + +/* lsr<.f> b,c 00100bbb00101111FBBBCCCCCC000010. */ +{ "lsr", 0x202F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* lsr<.f> 0,c 0010011000101111F111CCCCCC000010. */ +{ "lsr", 0x262F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* lsr<.f> a,b,c 00101bbb00000001FBBBCCCCCCAAAAAA. */ +{ "lsr", 0x28010000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }}, + +/* lsr<.f> 0,b,c 00101bbb00000001FBBBCCCCCC111110. */ +{ "lsr", 0x2801003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }}, + +/* lsr<.f><.cc> b,b,c 00101bbb11000001FBBBCCCCCC0QQQQQ. */ +{ "lsr", 0x28C10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* lsr<.f> b,u6 00100bbb01101111FBBBuuuuuu000010. */ +{ "lsr", 0x206F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,u6 0010011001101111F111uuuuuu000010. */ +{ "lsr", 0x266F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* lsr<.f> a,b,u6 00101bbb01000001FBBBuuuuuuAAAAAA. */ +{ "lsr", 0x28410000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,b,u6 00101bbb01000001FBBBuuuuuu111110. */ +{ "lsr", 0x2841003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* lsr<.f><.cc> b,b,u6 00101bbb11000001FBBBuuuuuu1QQQQQ. */ +{ "lsr", 0x28C10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* lsr<.f> b,b,s12 00101bbb10000001FBBBssssssSSSSSS. */ +{ "lsr", 0x28810000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* lsr<.f> b,limm 00100bbb00101111FBBB111110000010. */ +{ "lsr", 0x202F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* lsr<.f> 0,limm 0010011000101111F111111110000010. */ +{ "lsr", 0x262F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* lsr<.f> a,limm,c 0010111000000001F111CCCCCCAAAAAA. */ +{ "lsr", 0x2E017000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }}, + +/* lsr<.f> a,b,limm 00101bbb00000001FBBB111110AAAAAA. */ +{ "lsr", 0x28010F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }}, + +/* lsr<.f> 0,limm,c 0010111000000001F111CCCCCC111110. */ +{ "lsr", 0x2E01703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }}, + +/* lsr<.f> 0,b,limm 00101bbb00000001FBBB111110111110. */ +{ "lsr", 0x28010FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }}, + +/* lsr<.f><.cc> b,b,limm 00101bbb11000001FBBB1111100QQQQQ. */ +{ "lsr", 0x28C10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* lsr<.f><.cc> 0,limm,c 0010111011000001F111CCCCCC0QQQQQ. */ +{ "lsr", 0x2EC17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* lsr<.f> a,limm,u6 0010111001000001F111uuuuuuAAAAAA. */ +{ "lsr", 0x2E417000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* lsr<.f> 0,limm,u6 0010111001000001F111uuuuuu111110. */ +{ "lsr", 0x2E41703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* lsr<.f><.cc> 0,limm,u6 0010111011000001F111uuuuuu1QQQQQ. */ +{ "lsr", 0x2EC17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* lsr<.f> 0,limm,s12 0010111010000001F111ssssssSSSSSS. */ +{ "lsr", 0x2E817000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* lsr<.f> a,limm,limm 0010111000000001F111111110AAAAAA. */ +{ "lsr", 0x2E017F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }}, + +/* lsr<.f> 0,limm,limm 0010111000000001F111111110111110. */ +{ "lsr", 0x2E017FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* lsr<.f><.cc> 0,limm,limm 0010111011000001F1111111100QQQQQ. */ +{ "lsr", 0x2EC17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* lsr16<.f> b,c 00101bbb00101111FBBBCCCCCC001011. */ +{ "lsr16", 0x282F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }}, + +/* lsr16<.f> 0,c 0010111000101111F111CCCCCC001011. */ +{ "lsr16", 0x2E2F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }}, + +/* lsr16<.f> b,u6 00101bbb01101111FBBBuuuuuu001011. */ +{ "lsr16", 0x286F000B, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }}, + +/* lsr16<.f> 0,u6 0010111001101111F111uuuuuu001011. */ +{ "lsr16", 0x2E6F700B, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }}, + +/* lsr16<.f> b,limm 00101bbb00101111FBBB111110001011. */ +{ "lsr16", 0x282F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }}, + +/* lsr16<.f> 0,limm 0010111000101111F111111110001011. */ +{ "lsr16", 0x2E2F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }}, + +/* lsr8<.f> b,c 00101bbb00101111FBBBCCCCCC001110. */ +{ "lsr8", 0x282F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, RC }, { C_F }}, + +/* lsr8<.f> 0,c 0010111000101111F111CCCCCC001110. */ +{ "lsr8", 0x2E2F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, RC }, { C_F }}, + +/* lsr8<.f> b,u6 00101bbb01101111FBBBuuuuuu001110. */ +{ "lsr8", 0x286F000E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* lsr8<.f> 0,u6 0010111001101111F111uuuuuu001110. */ +{ "lsr8", 0x2E6F700E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* lsr8<.f> b,limm 00101bbb00101111FBBB111110001110. */ +{ "lsr8", 0x282F0F8E, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { RB, LIMM }, { C_F }}, + +/* lsr8<.f> 0,limm 0010111000101111F111111110001110. */ +{ "lsr8", 0x2E2F7F8E, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SHFT1, { ZA, LIMM }, { C_F }}, + +/* lsrdw<.f> a,b,c 00101bbb00100011FBBBCCCCCCAAAAAA. */ +{ "lsrdw", 0x28230000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* lsrdw<.f> 0,b,c 00101bbb00100011FBBBCCCCCC111110. */ +{ "lsrdw", 0x2823003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* lsrdw<.f><.cc> b,b,c 00101bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "lsrdw", 0x28E30000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* lsrdw<.f> a,b,u6 00101bbb01100011FBBBuuuuuuAAAAAA. */ +{ "lsrdw", 0x28630000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* lsrdw<.f> 0,b,u6 00101bbb01100011FBBBuuuuuu111110. */ +{ "lsrdw", 0x2863003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* lsrdw<.f><.cc> b,b,u6 00101bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "lsrdw", 0x28E30020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* lsrdw<.f> b,b,s12 00101bbb10100011FBBBssssssSSSSSS. */ +{ "lsrdw", 0x28A30000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* lsrdw<.f> a,limm,c 0010111000100011F111CCCCCCAAAAAA. */ +{ "lsrdw", 0x2E237000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* lsrdw<.f> a,b,limm 00101bbb00100011FBBB111110AAAAAA. */ +{ "lsrdw", 0x28230F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* lsrdw<.f> 0,limm,c 0010111000100011F111CCCCCC111110. */ +{ "lsrdw", 0x2E23703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* lsrdw<.f> 0,b,limm 00101bbb00100011FBBB111110111110. */ +{ "lsrdw", 0x28230FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,c 0010111011100011F111CCCCCC0QQQQQ. */ +{ "lsrdw", 0x2EE37000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* lsrdw<.f><.cc> b,b,limm 00101bbb11100011FBBB1111100QQQQQ. */ +{ "lsrdw", 0x28E30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* lsrdw<.f> a,limm,u6 0010111001100011F111uuuuuuAAAAAA. */ +{ "lsrdw", 0x2E637000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* lsrdw<.f> 0,limm,u6 0010111001100011F111uuuuuu111110. */ +{ "lsrdw", 0x2E63703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,u6 0010111011100011F111uuuuuu1QQQQQ. */ +{ "lsrdw", 0x2EE37020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* lsrdw<.f> 0,limm,s12 0010111010100011F111ssssssSSSSSS. */ +{ "lsrdw", 0x2EA37000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* lsrdw<.f> a,limm,limm 0010111000100011F111111110AAAAAA. */ +{ "lsrdw", 0x2E237F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* lsrdw<.f> 0,limm,limm 0010111000100011F111111110111110. */ +{ "lsrdw", 0x2E237FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* lsrdw<.f><.cc> 0,limm,limm 0010111011100011F1111111100QQQQQ. */ +{ "lsrdw", 0x2EE37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* lsr_s b,c 01111bbbccc11101. */ +{ "lsr_s", 0x0000781D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }}, + +/* lsr_s b,b,c 01111bbbccc11001. */ +{ "lsr_s", 0x00007819, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* lsr_s b,b,u5 10111bbb001uuuuu. */ +{ "lsr_s", 0x0000B820, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* mac<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ +{ "mac", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* mac<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ +{ "mac", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* mac<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "mac", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mac<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ +{ "mac", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mac<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ +{ "mac", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mac<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "mac", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mac<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ +{ "mac", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mac<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ +{ "mac", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* mac<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ +{ "mac", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* mac<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ +{ "mac", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* mac<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ +{ "mac", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* mac<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ +{ "mac", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mac<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ +{ "mac", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mac<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ +{ "mac", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mac<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ +{ "mac", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mac<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ +{ "mac", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mac<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ +{ "mac", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mac<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ +{ "mac", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mac<.f> 0,limm,limm 0010111000001110F111111110111110. */ +{ "mac", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mac<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ +{ "mac", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macd<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ +{ "macd", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }}, + +/* macd<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ +{ "macd", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }}, + +/* macd<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "macd", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macd<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ +{ "macd", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macd<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ +{ "macd", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macd<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "macd", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macd<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ +{ "macd", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macd<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ +{ "macd", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }}, + +/* macd<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ +{ "macd", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }}, + +/* macd<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ +{ "macd", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }}, + +/* macd<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ +{ "macd", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }}, + +/* macd<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ +{ "macd", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macd<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ +{ "macd", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macd<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ +{ "macd", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macd<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ +{ "macd", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macd<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ +{ "macd", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macd<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ +{ "macd", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macd<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ +{ "macd", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macd<.f> 0,limm,limm 0010111000011010F111111110111110. */ +{ "macd", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macd<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ +{ "macd", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macdf<.f> a,b,c 00110bbb00010011FBBBCCCCCCAAAAAA. */ +{ "macdf", 0x30130000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* macdf<.f> 0,b,c 00110bbb00010011FBBBCCCCCC111110. */ +{ "macdf", 0x3013003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* macdf<.f><.cc> b,b,c 00110bbb11010011FBBBCCCCCC0QQQQQ. */ +{ "macdf", 0x30D30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macdf<.f> a,b,u6 00110bbb01010011FBBBuuuuuuAAAAAA. */ +{ "macdf", 0x30530000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macdf<.f> 0,b,u6 00110bbb01010011FBBBuuuuuu111110. */ +{ "macdf", 0x3053003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macdf<.f><.cc> b,b,u6 00110bbb11010011FBBBuuuuuu1QQQQQ. */ +{ "macdf", 0x30D30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macdf<.f> b,b,s12 00110bbb10010011FBBBssssssSSSSSS. */ +{ "macdf", 0x30930000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macdf<.f> a,limm,c 0011011000010011F111CCCCCCAAAAAA. */ +{ "macdf", 0x36137000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macdf<.f> a,b,limm 00110bbb00010011FBBB111110AAAAAA. */ +{ "macdf", 0x30130F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macdf<.f> 0,limm,c 0011011000010011F111CCCCCC111110. */ +{ "macdf", 0x3613703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macdf<.f> 0,b,limm 00110bbb00010011FBBB111110111110. */ +{ "macdf", 0x30130FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macdf<.f><.cc> b,b,limm 00110bbb11010011FBBB1111100QQQQQ. */ +{ "macdf", 0x30D30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macdf<.f><.cc> 0,limm,c 0011011011010011F111CCCCCC0QQQQQ. */ +{ "macdf", 0x36D37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macdf<.f> a,limm,u6 0011011001010011F111uuuuuuAAAAAA. */ +{ "macdf", 0x36537000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdf<.f> 0,limm,u6 0011011001010011F111uuuuuu111110. */ +{ "macdf", 0x3653703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdf<.f><.cc> 0,limm,u6 0011011011010011F111uuuuuu1QQQQQ. */ +{ "macdf", 0x36D37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macdf<.f> 0,limm,s12 0011011010010011F111ssssssSSSSSS. */ +{ "macdf", 0x36937000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macdf<.f> a,limm,limm 0011011000010011F111111110AAAAAA. */ +{ "macdf", 0x36137F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macdf<.f> 0,limm,limm 0011011000010011F111111110111110. */ +{ "macdf", 0x36137FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macdf<.f><.cc> 0,limm,limm 0011011011010011F1111111100QQQQQ. */ +{ "macdf", 0x36D37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macdu<.f> a,b,c 00101bbb00011011FBBBCCCCCCAAAAAA. */ +{ "macdu", 0x281B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }}, + +/* macdu<.f> 0,b,c 00101bbb00011011FBBBCCCCCC111110. */ +{ "macdu", 0x281B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }}, + +/* macdu<.f><.cc> b,b,c 00101bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "macdu", 0x28DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macdu<.f> a,b,u6 00101bbb01011011FBBBuuuuuuAAAAAA. */ +{ "macdu", 0x285B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macdu<.f> 0,b,u6 00101bbb01011011FBBBuuuuuu111110. */ +{ "macdu", 0x285B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macdu<.f><.cc> b,b,u6 00101bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "macdu", 0x28DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macdu<.f> b,b,s12 00101bbb10011011FBBBssssssSSSSSS. */ +{ "macdu", 0x289B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macdu<.f> a,limm,c 0010111000011011F111CCCCCCAAAAAA. */ +{ "macdu", 0x2E1B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }}, + +/* macdu<.f> a,b,limm 00101bbb00011011FBBB111110AAAAAA. */ +{ "macdu", 0x281B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }}, + +/* macdu<.f> 0,limm,c 0010111000011011F111CCCCCC111110. */ +{ "macdu", 0x2E1B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }}, + +/* macdu<.f> 0,b,limm 00101bbb00011011FBBB111110111110. */ +{ "macdu", 0x281B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }}, + +/* macdu<.f><.cc> b,b,limm 00101bbb11011011FBBB1111100QQQQQ. */ +{ "macdu", 0x28DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macdu<.f><.cc> 0,limm,c 0010111011011011F111CCCCCC0QQQQQ. */ +{ "macdu", 0x2EDB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macdu<.f> a,limm,u6 0010111001011011F111uuuuuuAAAAAA. */ +{ "macdu", 0x2E5B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdu<.f> 0,limm,u6 0010111001011011F111uuuuuu111110. */ +{ "macdu", 0x2E5B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdu<.f><.cc> 0,limm,u6 0010111011011011F111uuuuuu1QQQQQ. */ +{ "macdu", 0x2EDB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macdu<.f> 0,limm,s12 0010111010011011F111ssssssSSSSSS. */ +{ "macdu", 0x2E9B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macdu<.f> a,limm,limm 0010111000011011F111111110AAAAAA. */ +{ "macdu", 0x2E1B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macdu<.f> 0,limm,limm 0010111000011011F111111110111110. */ +{ "macdu", 0x2E1B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macdu<.f><.cc> 0,limm,limm 0010111011011011F1111111100QQQQQ. */ +{ "macdu", 0x2EDB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macdw<.f> a,b,c 00101bbb00010000FBBBCCCCCCAAAAAA. */ +{ "macdw", 0x28100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macdw<.f> 0,b,c 00101bbb00010000FBBBCCCCCC111110. */ +{ "macdw", 0x2810003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macdw<.f><.cc> b,b,c 00101bbb11010000FBBBCCCCCC0QQQQQ. */ +{ "macdw", 0x28D00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macdw<.f> a,b,u6 00101bbb01010000FBBBuuuuuuAAAAAA. */ +{ "macdw", 0x28500000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macdw<.f> 0,b,u6 00101bbb01010000FBBBuuuuuu111110. */ +{ "macdw", 0x2850003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macdw<.f><.cc> b,b,u6 00101bbb11010000FBBBuuuuuu1QQQQQ. */ +{ "macdw", 0x28D00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macdw<.f> b,b,s12 00101bbb10010000FBBBssssssSSSSSS. */ +{ "macdw", 0x28900000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macdw<.f> a,limm,c 0010111000010000F111CCCCCCAAAAAA. */ +{ "macdw", 0x2E107000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macdw<.f> a,b,limm 00101bbb00010000FBBB111110AAAAAA. */ +{ "macdw", 0x28100F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macdw<.f> 0,limm,c 0010111000010000F111CCCCCC111110. */ +{ "macdw", 0x2E10703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macdw<.f> 0,b,limm 00101bbb00010000FBBB111110111110. */ +{ "macdw", 0x28100FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,c 0010111011010000F111CCCCCC0QQQQQ. */ +{ "macdw", 0x2ED07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macdw<.f><.cc> b,b,limm 00101bbb11010000FBBB1111100QQQQQ. */ +{ "macdw", 0x28D00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macdw<.f> a,limm,u6 0010111001010000F111uuuuuuAAAAAA. */ +{ "macdw", 0x2E507000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdw<.f> 0,limm,u6 0010111001010000F111uuuuuu111110. */ +{ "macdw", 0x2E50703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,u6 0010111011010000F111uuuuuu1QQQQQ. */ +{ "macdw", 0x2ED07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macdw<.f> 0,limm,s12 0010111010010000F111ssssssSSSSSS. */ +{ "macdw", 0x2E907000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macdw<.f> a,limm,limm 0010111000010000F111111110AAAAAA. */ +{ "macdw", 0x2E107F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macdw<.f> 0,limm,limm 0010111000010000F111111110111110. */ +{ "macdw", 0x2E107FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macdw<.f><.cc> 0,limm,limm 0010111011010000F1111111100QQQQQ. */ +{ "macdw", 0x2ED07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macf<.f> a,b,c 00110bbb00001100FBBBCCCCCCAAAAAA. */ +{ "macf", 0x300C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macf<.f> 0,b,c 00110bbb00001100FBBBCCCCCC111110. */ +{ "macf", 0x300C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macf<.f><.cc> b,b,c 00110bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "macf", 0x30CC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macf<.f> a,b,u6 00110bbb01001100FBBBuuuuuuAAAAAA. */ +{ "macf", 0x304C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macf<.f> 0,b,u6 00110bbb01001100FBBBuuuuuu111110. */ +{ "macf", 0x304C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macf<.f><.cc> b,b,u6 00110bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "macf", 0x30CC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macf<.f> b,b,s12 00110bbb10001100FBBBssssssSSSSSS. */ +{ "macf", 0x308C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macf<.f> a,limm,c 0011011000001100F111CCCCCCAAAAAA. */ +{ "macf", 0x360C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macf<.f> a,b,limm 00110bbb00001100FBBB111110AAAAAA. */ +{ "macf", 0x300C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macf<.f> 0,limm,c 0011011000001100F111CCCCCC111110. */ +{ "macf", 0x360C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macf<.f> 0,b,limm 00110bbb00001100FBBB111110111110. */ +{ "macf", 0x300C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macf<.f><.cc> 0,limm,c 00110bbb11001100FBBB1111100QQQQQ. */ +{ "macf", 0x30CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macf<.f><.cc> b,b,limm 0011011011001100F111CCCCCC0QQQQQ. */ +{ "macf", 0x36CC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macf<.f> a,limm,u6 0011011001001100F111uuuuuuAAAAAA. */ +{ "macf", 0x364C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macf<.f> 0,limm,u6 0011011001001100F111uuuuuu111110. */ +{ "macf", 0x364C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macf<.f><.cc> 0,limm,u6 0011011011001100F111uuuuuu1QQQQQ. */ +{ "macf", 0x36CC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macf<.f> 0,limm,s12 0011011010001100F111ssssssSSSSSS. */ +{ "macf", 0x368C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macf<.f> a,limm,limm 0011011000001100F111111110AAAAAA. */ +{ "macf", 0x360C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macf<.f> 0,limm,limm 0011011000001100F111111110111110. */ +{ "macf", 0x360C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macf<.f><.cc> 0,limm,limm 0011011011001100F1111111100QQQQQ. */ +{ "macf", 0x36CC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macflw<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ +{ "macflw", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macflw<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ +{ "macflw", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macflw<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "macflw", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macflw<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ +{ "macflw", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macflw<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ +{ "macflw", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macflw<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "macflw", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macflw<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ +{ "macflw", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macflw<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ +{ "macflw", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macflw<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ +{ "macflw", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macflw<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ +{ "macflw", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macflw<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ +{ "macflw", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ +{ "macflw", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macflw<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ +{ "macflw", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macflw<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ +{ "macflw", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macflw<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ +{ "macflw", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ +{ "macflw", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macflw<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ +{ "macflw", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macflw<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ +{ "macflw", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macflw<.f> 0,limm,limm 0010111000110100F111111110111110. */ +{ "macflw", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macflw<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ +{ "macflw", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macfr<.f> a,b,c 00110bbb00001101FBBBCCCCCCAAAAAA. */ +{ "macfr", 0x300D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macfr<.f> 0,b,c 00110bbb00001101FBBBCCCCCC111110. */ +{ "macfr", 0x300D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macfr<.f><.cc> b,b,c 00110bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "macfr", 0x30CD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macfr<.f> a,b,u6 00110bbb01001101FBBBuuuuuuAAAAAA. */ +{ "macfr", 0x304D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macfr<.f> 0,b,u6 00110bbb01001101FBBBuuuuuu111110. */ +{ "macfr", 0x304D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macfr<.f><.cc> b,b,u6 00110bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "macfr", 0x30CD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macfr<.f> b,b,s12 00110bbb10001101FBBBssssssSSSSSS. */ +{ "macfr", 0x308D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macfr<.f> a,limm,c 0011011000001101F111CCCCCCAAAAAA. */ +{ "macfr", 0x360D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macfr<.f> a,b,limm 00110bbb00001101FBBB111110AAAAAA. */ +{ "macfr", 0x300D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macfr<.f> 0,limm,c 0011011000001101F111CCCCCC111110. */ +{ "macfr", 0x360D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macfr<.f> 0,b,limm 00110bbb00001101FBBB111110111110. */ +{ "macfr", 0x300D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,c 00110bbb11001101FBBB1111100QQQQQ. */ +{ "macfr", 0x30CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macfr<.f><.cc> b,b,limm 0011011011001101F111CCCCCC0QQQQQ. */ +{ "macfr", 0x36CD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macfr<.f> a,limm,u6 0011011001001101F111uuuuuuAAAAAA. */ +{ "macfr", 0x364D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macfr<.f> 0,limm,u6 0011011001001101F111uuuuuu111110. */ +{ "macfr", 0x364D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,u6 0011011011001101F111uuuuuu1QQQQQ. */ +{ "macfr", 0x36CD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macfr<.f> 0,limm,s12 0011011010001101F111ssssssSSSSSS. */ +{ "macfr", 0x368D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macfr<.f> a,limm,limm 0011011000001101F111111110AAAAAA. */ +{ "macfr", 0x360D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macfr<.f> 0,limm,limm 0011011000001101F111111110111110. */ +{ "macfr", 0x360D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macfr<.f><.cc> 0,limm,limm 0011011011001101F1111111100QQQQQ. */ +{ "macfr", 0x36CD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* machflw<.f> a,b,c 00101bbb00110111FBBBCCCCCCAAAAAA. */ +{ "machflw", 0x28370000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* machflw<.f> 0,b,c 00101bbb00110111FBBBCCCCCC111110. */ +{ "machflw", 0x2837003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* machflw<.f><.cc> b,b,c 00101bbb11110111FBBBCCCCCC0QQQQQ. */ +{ "machflw", 0x28F70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* machflw<.f> a,b,u6 00101bbb01110111FBBBuuuuuuAAAAAA. */ +{ "machflw", 0x28770000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* machflw<.f> 0,b,u6 00101bbb01110111FBBBuuuuuu111110. */ +{ "machflw", 0x2877003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* machflw<.f><.cc> b,b,u6 00101bbb11110111FBBBuuuuuu1QQQQQ. */ +{ "machflw", 0x28F70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* machflw<.f> b,b,s12 00101bbb10110111FBBBssssssSSSSSS. */ +{ "machflw", 0x28B70000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* machflw<.f> a,limm,c 0010111000110111F111CCCCCCAAAAAA. */ +{ "machflw", 0x2E377000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* machflw<.f> a,b,limm 00101bbb00110111FBBB111110AAAAAA. */ +{ "machflw", 0x28370F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* machflw<.f> 0,limm,c 0010111000110111F111CCCCCC111110. */ +{ "machflw", 0x2E37703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* machflw<.f> 0,b,limm 00101bbb00110111FBBB111110111110. */ +{ "machflw", 0x28370FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,c 0010111011110111F111CCCCCC0QQQQQ. */ +{ "machflw", 0x2EF77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* machflw<.f><.cc> b,b,limm 00101bbb11110111FBBB1111100QQQQQ. */ +{ "machflw", 0x28F70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* machflw<.f> a,limm,u6 0010111001110111F111uuuuuuAAAAAA. */ +{ "machflw", 0x2E777000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* machflw<.f> 0,limm,u6 0010111001110111F111uuuuuu111110. */ +{ "machflw", 0x2E77703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,u6 0010111011110111F111uuuuuu1QQQQQ. */ +{ "machflw", 0x2EF77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* machflw<.f> 0,limm,s12 0010111010110111F111ssssssSSSSSS. */ +{ "machflw", 0x2EB77000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* machflw<.f> a,limm,limm 0010111000110111F111111110AAAAAA. */ +{ "machflw", 0x2E377F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* machflw<.f> 0,limm,limm 0010111000110111F111111110111110. */ +{ "machflw", 0x2E377FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* machflw<.f><.cc> 0,limm,limm 0010111011110111F1111111100QQQQQ. */ +{ "machflw", 0x2EF77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* machlw<.f> a,b,c 00101bbb00110110FBBBCCCCCCAAAAAA. */ +{ "machlw", 0x28360000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* machlw<.f> 0,b,c 00101bbb00110110FBBBCCCCCC111110. */ +{ "machlw", 0x2836003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* machlw<.f><.cc> b,b,c 00101bbb11110110FBBBCCCCCC0QQQQQ. */ +{ "machlw", 0x28F60000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* machlw<.f> a,b,u6 00101bbb01110110FBBBuuuuuuAAAAAA. */ +{ "machlw", 0x28760000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* machlw<.f> 0,b,u6 00101bbb01110110FBBBuuuuuu111110. */ +{ "machlw", 0x2876003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* machlw<.f><.cc> b,b,u6 00101bbb11110110FBBBuuuuuu1QQQQQ. */ +{ "machlw", 0x28F60020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* machlw<.f> b,b,s12 00101bbb10110110FBBBssssssSSSSSS. */ +{ "machlw", 0x28B60000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* machlw<.f> a,limm,c 0010111000110110F111CCCCCCAAAAAA. */ +{ "machlw", 0x2E367000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* machlw<.f> a,b,limm 00101bbb00110110FBBB111110AAAAAA. */ +{ "machlw", 0x28360F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* machlw<.f> 0,limm,c 0010111000110110F111CCCCCC111110. */ +{ "machlw", 0x2E36703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* machlw<.f> 0,b,limm 00101bbb00110110FBBB111110111110. */ +{ "machlw", 0x28360FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,c 0010111011110110F111CCCCCC0QQQQQ. */ +{ "machlw", 0x2EF67000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* machlw<.f><.cc> b,b,limm 00101bbb11110110FBBB1111100QQQQQ. */ +{ "machlw", 0x28F60F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* machlw<.f> a,limm,u6 0010111001110110F111uuuuuuAAAAAA. */ +{ "machlw", 0x2E767000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* machlw<.f> 0,limm,u6 0010111001110110F111uuuuuu111110. */ +{ "machlw", 0x2E76703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,u6 0010111011110110F111uuuuuu1QQQQQ. */ +{ "machlw", 0x2EF67020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* machlw<.f> 0,limm,s12 0010111010110110F111ssssssSSSSSS. */ +{ "machlw", 0x2EB67000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* machlw<.f> a,limm,limm 0010111000110110F111111110AAAAAA. */ +{ "machlw", 0x2E367F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* machlw<.f> 0,limm,limm 0010111000110110F111111110111110. */ +{ "machlw", 0x2E367FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* machlw<.f><.cc> 0,limm,limm 0010111011110110F1111111100QQQQQ. */ +{ "machlw", 0x2EF67F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* machulw<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ +{ "machulw", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* machulw<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ +{ "machulw", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* machulw<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "machulw", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* machulw<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ +{ "machulw", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* machulw<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ +{ "machulw", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* machulw<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "machulw", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* machulw<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ +{ "machulw", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* machulw<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ +{ "machulw", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* machulw<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ +{ "machulw", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* machulw<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ +{ "machulw", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* machulw<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ +{ "machulw", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ +{ "machulw", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* machulw<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ +{ "machulw", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* machulw<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ +{ "machulw", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* machulw<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ +{ "machulw", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ +{ "machulw", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* machulw<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ +{ "machulw", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* machulw<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ +{ "machulw", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* machulw<.f> 0,limm,limm 0010111000110101F111111110111110. */ +{ "machulw", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* machulw<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ +{ "machulw", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* maclw<.f> a,b,c 00101bbb00110011FBBBCCCCCCAAAAAA. */ +{ "maclw", 0x28330000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* maclw<.f> 0,b,c 00101bbb00110011FBBBCCCCCC111110. */ +{ "maclw", 0x2833003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* maclw<.f><.cc> b,b,c 00101bbb11110011FBBBCCCCCC0QQQQQ. */ +{ "maclw", 0x28F30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* maclw<.f> a,b,u6 00101bbb01110011FBBBuuuuuuAAAAAA. */ +{ "maclw", 0x28730000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* maclw<.f> 0,b,u6 00101bbb01110011FBBBuuuuuu111110. */ +{ "maclw", 0x2873003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* maclw<.f><.cc> b,b,u6 00101bbb11110011FBBBuuuuuu1QQQQQ. */ +{ "maclw", 0x28F30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* maclw<.f> b,b,s12 00101bbb10110011FBBBssssssSSSSSS. */ +{ "maclw", 0x28B30000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* maclw<.f> a,limm,c 0010111000110011F111CCCCCCAAAAAA. */ +{ "maclw", 0x2E337000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* maclw<.f> a,b,limm 00101bbb00110011FBBB111110AAAAAA. */ +{ "maclw", 0x28330F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* maclw<.f> 0,limm,c 0010111000110011F111CCCCCC111110. */ +{ "maclw", 0x2E33703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* maclw<.f> 0,b,limm 00101bbb00110011FBBB111110111110. */ +{ "maclw", 0x28330FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,c 0010111011110011F111CCCCCC0QQQQQ. */ +{ "maclw", 0x2EF37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* maclw<.f><.cc> b,b,limm 00101bbb11110011FBBB1111100QQQQQ. */ +{ "maclw", 0x28F30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* maclw<.f> a,limm,u6 0010111001110011F111uuuuuuAAAAAA. */ +{ "maclw", 0x2E737000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* maclw<.f> 0,limm,u6 0010111001110011F111uuuuuu111110. */ +{ "maclw", 0x2E73703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,u6 0010111011110011F111uuuuuu1QQQQQ. */ +{ "maclw", 0x2EF37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* maclw<.f> 0,limm,s12 0010111010110011F111ssssssSSSSSS. */ +{ "maclw", 0x2EB37000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* maclw<.f> a,limm,limm 0010111000110011F111111110AAAAAA. */ +{ "maclw", 0x2E337F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* maclw<.f> 0,limm,limm 0010111000110011F111111110111110. */ +{ "maclw", 0x2E337FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* maclw<.f><.cc> 0,limm,limm 0010111011110011F1111111100QQQQQ. */ +{ "maclw", 0x2EF37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macrdw<.f> a,b,c 00101bbb00010010FBBBCCCCCCAAAAAA. */ +{ "macrdw", 0x28120000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macrdw<.f> 0,b,c 00101bbb00010010FBBBCCCCCC111110. */ +{ "macrdw", 0x2812003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macrdw<.f><.cc> b,b,c 00101bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "macrdw", 0x28D20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macrdw<.f> a,b,u6 00101bbb01010010FBBBuuuuuuAAAAAA. */ +{ "macrdw", 0x28520000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macrdw<.f> 0,b,u6 00101bbb01010010FBBBuuuuuu111110. */ +{ "macrdw", 0x2852003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macrdw<.f><.cc> b,b,u6 00101bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "macrdw", 0x28D20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macrdw<.f> b,b,s12 00101bbb10010010FBBBssssssSSSSSS. */ +{ "macrdw", 0x28920000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macrdw<.f> a,limm,c 0010111000010010F111CCCCCCAAAAAA. */ +{ "macrdw", 0x2E127000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macrdw<.f> a,b,limm 00101bbb00010010FBBB111110AAAAAA. */ +{ "macrdw", 0x28120F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macrdw<.f> 0,limm,c 0010111000010010F111CCCCCC111110. */ +{ "macrdw", 0x2E12703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macrdw<.f> 0,b,limm 00101bbb00010010FBBB111110111110. */ +{ "macrdw", 0x28120FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,c 0010111011010010F111CCCCCC0QQQQQ. */ +{ "macrdw", 0x2ED27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macrdw<.f><.cc> b,b,limm 00101bbb11010010FBBB1111100QQQQQ. */ +{ "macrdw", 0x28D20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macrdw<.f> a,limm,u6 0010111001010010F111uuuuuuAAAAAA. */ +{ "macrdw", 0x2E527000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macrdw<.f> 0,limm,u6 0010111001010010F111uuuuuu111110. */ +{ "macrdw", 0x2E52703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,u6 0010111011010010F111uuuuuu1QQQQQ. */ +{ "macrdw", 0x2ED27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macrdw<.f> 0,limm,s12 0010111010010010F111ssssssSSSSSS. */ +{ "macrdw", 0x2E927000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macrdw<.f> a,limm,limm 0010111000010010F111111110AAAAAA. */ +{ "macrdw", 0x2E127F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macrdw<.f> 0,limm,limm 0010111000010010F111111110111110. */ +{ "macrdw", 0x2E127FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macrdw<.f><.cc> 0,limm,limm 0010111011010010F1111111100QQQQQ. */ +{ "macrdw", 0x2ED27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macrt<.f> a,b,c 00101bbb00011110FBBBCCCCCCAAAAAA. */ +{ "macrt", 0x281E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macrt<.f> 0,b,c 00101bbb00011110FBBBCCCCCC111110. */ +{ "macrt", 0x281E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macrt<.f><.cc> b,b,c 00101bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "macrt", 0x28DE0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macrt<.f> a,b,u6 00101bbb01011110FBBBuuuuuuAAAAAA. */ +{ "macrt", 0x285E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macrt<.f> 0,b,u6 00101bbb01011110FBBBuuuuuu111110. */ +{ "macrt", 0x285E003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macrt<.f><.cc> b,b,u6 00101bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "macrt", 0x28DE0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macrt<.f> b,b,s12 00101bbb10011110FBBBssssssSSSSSS. */ +{ "macrt", 0x289E0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macrt<.f> a,limm,c 0010111000011110F111CCCCCCAAAAAA. */ +{ "macrt", 0x2E1E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macrt<.f> a,b,limm 00101bbb00011110FBBB111110AAAAAA. */ +{ "macrt", 0x281E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macrt<.f> 0,limm,c 0010111000011110F111CCCCCC111110. */ +{ "macrt", 0x2E1E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macrt<.f> 0,b,limm 00101bbb00011110FBBB111110111110. */ +{ "macrt", 0x281E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,c 0010111011011110F111CCCCCC0QQQQQ. */ +{ "macrt", 0x2EDE7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macrt<.f><.cc> b,b,limm 00101bbb11011110FBBB1111100QQQQQ. */ +{ "macrt", 0x28DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macrt<.f> a,limm,u6 0010111001011110F111uuuuuuAAAAAA. */ +{ "macrt", 0x2E5E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macrt<.f> 0,limm,u6 0010111001011110F111uuuuuu111110. */ +{ "macrt", 0x2E5E703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,u6 0010111011011110F111uuuuuu1QQQQQ. */ +{ "macrt", 0x2EDE7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macrt<.f> 0,limm,s12 0010111010011110F111ssssssSSSSSS. */ +{ "macrt", 0x2E9E7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macrt<.f> a,limm,limm 0010111000011110F111111110AAAAAA. */ +{ "macrt", 0x2E1E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macrt<.f> 0,limm,limm 0010111000011110F111111110111110. */ +{ "macrt", 0x2E1E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macrt<.f><.cc> 0,limm,limm 0010111011011110F1111111100QQQQQ. */ +{ "macrt", 0x2EDE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mact<.f> a,b,c 00101bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mact", 0x281C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mact<.f> 0,b,c 00101bbb00011100FBBBCCCCCC111110. */ +{ "mact", 0x281C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mact<.f><.cc> b,b,c 00101bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mact", 0x28DC0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mact<.f> a,b,u6 00101bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mact", 0x285C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mact<.f> 0,b,u6 00101bbb01011100FBBBuuuuuu111110. */ +{ "mact", 0x285C003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mact<.f><.cc> b,b,u6 00101bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mact", 0x28DC0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mact<.f> b,b,s12 00101bbb10011100FBBBssssssSSSSSS. */ +{ "mact", 0x289C0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mact<.f> a,limm,c 0010111000011100F111CCCCCCAAAAAA. */ +{ "mact", 0x2E1C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mact<.f> a,b,limm 00101bbb00011100FBBB111110AAAAAA. */ +{ "mact", 0x281C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mact<.f> 0,limm,c 0010111000011100F111CCCCCC111110. */ +{ "mact", 0x2E1C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mact<.f> 0,b,limm 00101bbb00011100FBBB111110111110. */ +{ "mact", 0x281C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mact<.f><.cc> 0,limm,c 0010111011011100F111CCCCCC0QQQQQ. */ +{ "mact", 0x2EDC7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mact<.f><.cc> b,b,limm 00101bbb11011100FBBB1111100QQQQQ. */ +{ "mact", 0x28DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mact<.f> a,limm,u6 0010111001011100F111uuuuuuAAAAAA. */ +{ "mact", 0x2E5C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mact<.f> 0,limm,u6 0010111001011100F111uuuuuu111110. */ +{ "mact", 0x2E5C703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mact<.f><.cc> 0,limm,u6 0010111011011100F111uuuuuu1QQQQQ. */ +{ "mact", 0x2EDC7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mact<.f> 0,limm,s12 0010111010011100F111ssssssSSSSSS. */ +{ "mact", 0x2E9C7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mact<.f> a,limm,limm 0010111000011100F111111110AAAAAA. */ +{ "mact", 0x2E1C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mact<.f> 0,limm,limm 0010111000011100F111111110111110. */ +{ "mact", 0x2E1C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mact<.f><.cc> 0,limm,limm 0010111011011100F1111111100QQQQQ. */ +{ "mact", 0x2EDC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macu<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ +{ "macu", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { C_F }}, + +/* macu<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ +{ "macu", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { C_F }}, + +/* macu<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "macu", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macu<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ +{ "macu", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macu<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ +{ "macu", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macu<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "macu", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macu<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ +{ "macu", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macu<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ +{ "macu", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { C_F }}, + +/* macu<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ +{ "macu", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { C_F }}, + +/* macu<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ +{ "macu", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F }}, + +/* macu<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ +{ "macu", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { C_F }}, + +/* macu<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ +{ "macu", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macu<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ +{ "macu", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macu<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ +{ "macu", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macu<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ +{ "macu", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macu<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ +{ "macu", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macu<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ +{ "macu", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macu<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ +{ "macu", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macu<.f> 0,limm,limm 0010111000001111F111111110111110. */ +{ "macu", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macu<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ +{ "macu", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macudw<.f> a,b,c 00101bbb00010001FBBBCCCCCCAAAAAA. */ +{ "macudw", 0x28110000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macudw<.f> 0,b,c 00101bbb00010001FBBBCCCCCC111110. */ +{ "macudw", 0x2811003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macudw<.f><.cc> b,b,c 00101bbb11010001FBBBCCCCCC0QQQQQ. */ +{ "macudw", 0x28D10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macudw<.f> a,b,u6 00101bbb01010001FBBBuuuuuuAAAAAA. */ +{ "macudw", 0x28510000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macudw<.f> 0,b,u6 00101bbb01010001FBBBuuuuuu111110. */ +{ "macudw", 0x2851003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macudw<.f><.cc> b,b,u6 00101bbb11010001FBBBuuuuuu1QQQQQ. */ +{ "macudw", 0x28D10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macudw<.f> b,b,s12 00101bbb10010001FBBBssssssSSSSSS. */ +{ "macudw", 0x28910000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macudw<.f> a,limm,c 0010111000010001F111CCCCCCAAAAAA. */ +{ "macudw", 0x2E117000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macudw<.f> a,b,limm 00101bbb00010001FBBB111110AAAAAA. */ +{ "macudw", 0x28110F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macudw<.f> 0,limm,c 0010111000010001F111CCCCCC111110. */ +{ "macudw", 0x2E11703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macudw<.f> 0,b,limm 00101bbb00010001FBBB111110111110. */ +{ "macudw", 0x28110FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,c 0010111011010001F111CCCCCC0QQQQQ. */ +{ "macudw", 0x2ED17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macudw<.f><.cc> b,b,limm 00101bbb11010001FBBB1111100QQQQQ. */ +{ "macudw", 0x28D10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macudw<.f> a,limm,u6 0010111001010001F111uuuuuuAAAAAA. */ +{ "macudw", 0x2E517000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macudw<.f> 0,limm,u6 0010111001010001F111uuuuuu111110. */ +{ "macudw", 0x2E51703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,u6 0010111011010001F111uuuuuu1QQQQQ. */ +{ "macudw", 0x2ED17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macudw<.f> 0,limm,s12 0010111010010001F111ssssssSSSSSS. */ +{ "macudw", 0x2E917000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macudw<.f> a,limm,limm 0010111000010001F111111110AAAAAA. */ +{ "macudw", 0x2E117F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macudw<.f> 0,limm,limm 0010111000010001F111111110111110. */ +{ "macudw", 0x2E117FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macudw<.f><.cc> 0,limm,limm 0010111011010001F1111111100QQQQQ. */ +{ "macudw", 0x2ED17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macwhfm<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ +{ "macwhfm", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macwhfm<.f> 0,b,c 00110bbb00100010FBBBCCCCCC111110. */ +{ "macwhfm", 0x3022003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macwhfm<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "macwhfm", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macwhfm<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ +{ "macwhfm", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macwhfm<.f> 0,b,u6 00110bbb01100010FBBBuuuuuu111110. */ +{ "macwhfm", 0x3062003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macwhfm<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "macwhfm", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfm<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ +{ "macwhfm", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macwhfm<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ +{ "macwhfm", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macwhfm<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ +{ "macwhfm", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macwhfm<.f> 0,limm,c 0011011001100010F111CCCCCC111110. */ +{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macwhfm<.f> 0,b,limm 00110bbb00100010FBBB111110111110. */ +{ "macwhfm", 0x30220FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,c 00110bbb11100010FBBB1111100QQQQQ. */ +{ "macwhfm", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macwhfm<.f><.cc> b,b,limm 0011011011100010F111CCCCCC0QQQQQ. */ +{ "macwhfm", 0x36E27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macwhfm<.f> a,limm,u6 0011011001100010F111uuuuuuAAAAAA. */ +{ "macwhfm", 0x36627000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhfm<.f> 0,limm,u6 0011011001100010F111uuuuuu111110. */ +{ "macwhfm", 0x3662703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,u6 0011011011100010F111uuuuuu1QQQQQ. */ +{ "macwhfm", 0x36E27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfm<.f> 0,limm,s12 0011011010100010F111ssssssSSSSSS. */ +{ "macwhfm", 0x36A27000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macwhfm<.f> a,limm,limm 0011011000100010F111111110AAAAAA. */ +{ "macwhfm", 0x36227F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macwhfm<.f> 0,limm,limm 0011011000100010F111111110111110. */ +{ "macwhfm", 0x36227FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macwhfm<.f><.cc> 0,limm,limm 0011011011100010F1111111100QQQQQ. */ +{ "macwhfm", 0x36E27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,b,c 00110bbb00100011FBBBCCCCCCAAAAAA. */ +{ "macwhfmr", 0x30230000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macwhfmr<.f> 0,b,c 00110bbb00100011FBBBCCCCCC111110. */ +{ "macwhfmr", 0x3023003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macwhfmr<.f><.cc> b,b,c 00110bbb11100011FBBBCCCCCC0QQQQQ. */ +{ "macwhfmr", 0x30E30000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,b,u6 00110bbb01100011FBBBuuuuuuAAAAAA. */ +{ "macwhfmr", 0x30630000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f> 0,b,u6 00110bbb01100011FBBBuuuuuu111110. */ +{ "macwhfmr", 0x3063003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f><.cc> b,b,u6 00110bbb11100011FBBBuuuuuu1QQQQQ. */ +{ "macwhfmr", 0x30E30020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfmr<.f> b,b,s12 00110bbb10100011FBBBssssssSSSSSS. */ +{ "macwhfmr", 0x30A30000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macwhfmr<.f> a,limm,c 0011011000100011F111CCCCCCAAAAAA. */ +{ "macwhfmr", 0x36237000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macwhfmr<.f> a,b,limm 00110bbb00100011FBBB111110AAAAAA. */ +{ "macwhfmr", 0x30230F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macwhfmr<.f> 0,limm,c 0011011001100011F111CCCCCC111110. */ +{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macwhfmr<.f> 0,b,limm 00110bbb00100011FBBB111110111110. */ +{ "macwhfmr", 0x30230FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,c 00110bbb11100011FBBB1111100QQQQQ. */ +{ "macwhfmr", 0x30E30F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macwhfmr<.f><.cc> b,b,limm 0011011011100011F111CCCCCC0QQQQQ. */ +{ "macwhfmr", 0x36E37000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macwhfmr<.f> a,limm,u6 0011011001100011F111uuuuuuAAAAAA. */ +{ "macwhfmr", 0x36637000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f> 0,limm,u6 0011011001100011F111uuuuuu111110. */ +{ "macwhfmr", 0x3663703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,u6 0011011011100011F111uuuuuu1QQQQQ. */ +{ "macwhfmr", 0x36E37020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhfmr<.f> 0,limm,s12 0011011010100011F111ssssssSSSSSS. */ +{ "macwhfmr", 0x36A37000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macwhfmr<.f> a,limm,limm 0011011000100011F111111110AAAAAA. */ +{ "macwhfmr", 0x36237F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macwhfmr<.f> 0,limm,limm 0011011000100011F111111110111110. */ +{ "macwhfmr", 0x36237FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macwhfmr<.f><.cc> 0,limm,limm 0011011011100011F1111111100QQQQQ. */ +{ "macwhfmr", 0x36E37F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macwhl<.f> a,b,c 00110bbb00011101FBBBCCCCCCAAAAAA. */ +{ "macwhl", 0x301D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macwhl<.f> 0,b,c 00110bbb00011101FBBBCCCCCC111110. */ +{ "macwhl", 0x301D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macwhl<.f><.cc> b,b,c 00110bbb11011101FBBBCCCCCC0QQQQQ. */ +{ "macwhl", 0x30DD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macwhl<.f> a,b,u6 00110bbb01011101FBBBuuuuuuAAAAAA. */ +{ "macwhl", 0x305D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macwhl<.f> 0,b,u6 00110bbb01011101FBBBuuuuuu111110. */ +{ "macwhl", 0x305D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macwhl<.f><.cc> b,b,u6 00110bbb11011101FBBBuuuuuu1QQQQQ. */ +{ "macwhl", 0x30DD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhl<.f> b,b,s12 00110bbb10011101FBBBssssssSSSSSS. */ +{ "macwhl", 0x309D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macwhl<.f> a,limm,c 0011011000011101F111CCCCCCAAAAAA. */ +{ "macwhl", 0x361D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macwhl<.f> a,b,limm 00110bbb00011101FBBB111110AAAAAA. */ +{ "macwhl", 0x301D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macwhl<.f> 0,limm,c 0011011000011101F111CCCCCC111110. */ +{ "macwhl", 0x361D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macwhl<.f> 0,b,limm 00110bbb00011101FBBB111110111110. */ +{ "macwhl", 0x301D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,c 00110bbb11011101FBBB1111100QQQQQ. */ +{ "macwhl", 0x30DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macwhl<.f><.cc> b,b,limm 0011011011011101F111CCCCCC0QQQQQ. */ +{ "macwhl", 0x36DD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macwhl<.f> a,limm,u6 0011011001011101F111uuuuuuAAAAAA. */ +{ "macwhl", 0x365D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhl<.f> 0,limm,u6 0011011001011101F111uuuuuu111110. */ +{ "macwhl", 0x365D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,u6 0011011011011101F111uuuuuu1QQQQQ. */ +{ "macwhl", 0x36DD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhl<.f> 0,limm,s12 0011011010011101F111ssssssSSSSSS. */ +{ "macwhl", 0x369D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macwhl<.f> a,limm,limm 0011011000011101F111111110AAAAAA. */ +{ "macwhl", 0x361D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macwhl<.f> 0,limm,limm 0011011000011101F111111110111110. */ +{ "macwhl", 0x361D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macwhl<.f><.cc> 0,limm,limm 0011011011011101F1111111100QQQQQ. */ +{ "macwhl", 0x36DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* macwhul<.f> a,b,c 00110bbb00011111FBBBCCCCCCAAAAAA. */ +{ "macwhul", 0x301F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* macwhul<.f> 0,b,c 00110bbb00011111FBBBCCCCCC111110. */ +{ "macwhul", 0x301F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* macwhul<.f><.cc> b,b,c 00110bbb11011111FBBBCCCCCC0QQQQQ. */ +{ "macwhul", 0x30DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* macwhul<.f> a,b,u6 00110bbb01011111FBBBuuuuuuAAAAAA. */ +{ "macwhul", 0x305F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* macwhul<.f> 0,b,u6 00110bbb01011111FBBBuuuuuu111110. */ +{ "macwhul", 0x305F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* macwhul<.f><.cc> b,b,u6 00110bbb11011111FBBBuuuuuu1QQQQQ. */ +{ "macwhul", 0x30DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhul<.f> b,b,s12 00110bbb10011111FBBBssssssSSSSSS. */ +{ "macwhul", 0x309F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* macwhul<.f> a,limm,c 0011011000011111F111CCCCCCAAAAAA. */ +{ "macwhul", 0x361F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* macwhul<.f> a,b,limm 00110bbb00011111FBBB111110AAAAAA. */ +{ "macwhul", 0x301F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* macwhul<.f> 0,limm,c 0011011000011111F111CCCCCC111110. */ +{ "macwhul", 0x361F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* macwhul<.f> 0,b,limm 00110bbb00011111FBBB111110111110. */ +{ "macwhul", 0x301F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,c 00110bbb11011111FBBB1111100QQQQQ. */ +{ "macwhul", 0x30DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* macwhul<.f><.cc> b,b,limm 0011011011011111F111CCCCCC0QQQQQ. */ +{ "macwhul", 0x36DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* macwhul<.f> a,limm,u6 0011011001011111F111uuuuuuAAAAAA. */ +{ "macwhul", 0x365F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhul<.f> 0,limm,u6 0011011001011111F111uuuuuu111110. */ +{ "macwhul", 0x365F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,u6 0011011011011111F111uuuuuu1QQQQQ. */ +{ "macwhul", 0x36DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* macwhul<.f> 0,limm,s12 0011011010011111F111ssssssSSSSSS. */ +{ "macwhul", 0x369F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* macwhul<.f> a,limm,limm 0011011000011111F111111110AAAAAA. */ +{ "macwhul", 0x361F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* macwhul<.f> 0,limm,limm 0011011000011111F111111110111110. */ +{ "macwhul", 0x361F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* macwhul<.f><.cc> 0,limm,limm 0011011011011111F1111111100QQQQQ. */ +{ "macwhul", 0x36DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* max<.f> a,b,c 00100bbb00001000FBBBCCCCCCAAAAAA. */ +{ "max", 0x20080000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* max<.f> 0,b,c 00100bbb00001000FBBBCCCCCC111110. */ +{ "max", 0x2008003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* max<.f><.cc> b,b,c 00100bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "max", 0x20C80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* max<.f> a,b,u6 00100bbb01001000FBBBuuuuuuAAAAAA. */ +{ "max", 0x20480000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* max<.f> 0,b,u6 00100bbb01001000FBBBuuuuuu111110. */ +{ "max", 0x2048003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* max<.f><.cc> b,b,u6 00100bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "max", 0x20C80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* max<.f> b,b,s12 00100bbb10001000FBBBssssssSSSSSS. */ +{ "max", 0x20880000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* max<.f> a,limm,c 0010011000001000F111CCCCCCAAAAAA. */ +{ "max", 0x26087000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* max<.f> a,b,limm 00100bbb00001000FBBB111110AAAAAA. */ +{ "max", 0x20080F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* max<.f> 0,limm,c 0010011000001000F111CCCCCC111110. */ +{ "max", 0x2608703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* max<.f> 0,b,limm 00100bbb00001000FBBB111110111110. */ +{ "max", 0x20080FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* max<.f><.cc> b,b,limm 00100bbb11001000FBBB1111100QQQQQ. */ +{ "max", 0x20C80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* max<.f><.cc> 0,limm,c 0010011011001000F111CCCCCC0QQQQQ. */ +{ "max", 0x26C87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* max<.f> a,limm,u6 0010011001001000F111uuuuuuAAAAAA. */ +{ "max", 0x26487000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* max<.f> 0,limm,u6 0010011001001000F111uuuuuu111110. */ +{ "max", 0x2648703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* max<.f><.cc> 0,limm,u6 0010011011001000F111uuuuuu1QQQQQ. */ +{ "max", 0x26C87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* max<.f> 0,limm,s12 0010011010001000F111ssssssSSSSSS. */ +{ "max", 0x26887000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* max<.f> a,limm,limm 0010011000001000F111111110AAAAAA. */ +{ "max", 0x26087F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* max<.f> 0,limm,limm 0010011000001000F111111110111110. */ +{ "max", 0x26087FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* max<.f><.cc> 0,limm,limm 0010011011001000F1111111100QQQQQ. */ +{ "max", 0x26C87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,b,c 00101bbb00101011FBBBCCCCCCAAAAAA. */ +{ "maxabssdw", 0x282B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* maxabssdw<.f> 0,b,c 00101bbb00101011FBBBCCCCCC111110. */ +{ "maxabssdw", 0x282B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* maxabssdw<.f><.cc> b,b,c 00101bbb11101011FBBBCCCCCC0QQQQQ. */ +{ "maxabssdw", 0x28EB0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,b,u6 00101bbb01101011FBBBuuuuuuAAAAAA. */ +{ "maxabssdw", 0x286B0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f> 0,b,u6 00101bbb01101011FBBBuuuuuu111110. */ +{ "maxabssdw", 0x286B003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f><.cc> b,b,u6 00101bbb11101011FBBBuuuuuu1QQQQQ. */ +{ "maxabssdw", 0x28EB0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* maxabssdw<.f> b,b,s12 00101bbb10101011FBBBssssssSSSSSS. */ +{ "maxabssdw", 0x28AB0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* maxabssdw<.f> a,limm,c 0010111000101011F111CCCCCCAAAAAA. */ +{ "maxabssdw", 0x2E2B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* maxabssdw<.f> a,b,limm 00101bbb00101011FBBB111110AAAAAA. */ +{ "maxabssdw", 0x282B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* maxabssdw<.f> 0,limm,c 0010111000101011F111CCCCCC111110. */ +{ "maxabssdw", 0x2E2B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* maxabssdw<.f> 0,b,limm 00101bbb00101011FBBB111110111110. */ +{ "maxabssdw", 0x282B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,c 0010111011101011F111CCCCCC0QQQQQ. */ +{ "maxabssdw", 0x2EEB7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* maxabssdw<.f><.cc> b,b,limm 00101bbb11101011FBBB1111100QQQQQ. */ +{ "maxabssdw", 0x28EB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* maxabssdw<.f> a,limm,u6 0010111001101011F111uuuuuuAAAAAA. */ +{ "maxabssdw", 0x2E6B7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f> 0,limm,u6 0010111001101011F111uuuuuu111110. */ +{ "maxabssdw", 0x2E6B703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,u6 0010111011101011F111uuuuuu1QQQQQ. */ +{ "maxabssdw", 0x2EEB7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* maxabssdw<.f> 0,limm,s12 0010111010101011F111ssssssSSSSSS. */ +{ "maxabssdw", 0x2EAB7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* maxabssdw<.f> a,limm,limm 0010111000101011F111111110AAAAAA. */ +{ "maxabssdw", 0x2E2B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* maxabssdw<.f> 0,limm,limm 0010111000101011F111111110111110. */ +{ "maxabssdw", 0x2E2B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* maxabssdw<.f><.cc> 0,limm,limm 0010111011101011F1111111100QQQQQ. */ +{ "maxabssdw", 0x2EEB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* maxidl<.f> a,b,c 00101bbb00001111FBBBCCCCCCAAAAAA. */ +{ "maxidl", 0x280F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* maxidl<.f> 0,b,c 00101bbb00001111FBBBCCCCCC111110. */ +{ "maxidl", 0x280F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* maxidl<.f><.cc> b,b,c 00101bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "maxidl", 0x28CF0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* maxidl<.f> a,b,u6 00101bbb01001111FBBBuuuuuuAAAAAA. */ +{ "maxidl", 0x284F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* maxidl<.f> 0,b,u6 00101bbb01001111FBBBuuuuuu111110. */ +{ "maxidl", 0x284F003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* maxidl<.f><.cc> b,b,u6 00101bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "maxidl", 0x28CF0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* maxidl<.f> b,b,s12 00101bbb10001111FBBBssssssSSSSSS. */ +{ "maxidl", 0x288F0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* maxidl<.f> a,limm,c 0010111000001111F111CCCCCCAAAAAA. */ +{ "maxidl", 0x2E0F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* maxidl<.f> a,b,limm 00101bbb00001111FBBB111110AAAAAA. */ +{ "maxidl", 0x280F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* maxidl<.f> 0,limm,c 0010111000001111F111CCCCCC111110. */ +{ "maxidl", 0x2E0F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* maxidl<.f> 0,b,limm 00101bbb00001111FBBB111110111110. */ +{ "maxidl", 0x280F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,c 0010111011001111F111CCCCCC0QQQQQ. */ +{ "maxidl", 0x2ECF7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* maxidl<.f><.cc> b,b,limm 00101bbb11001111FBBB1111100QQQQQ. */ +{ "maxidl", 0x28CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* maxidl<.f> a,limm,u6 0010111001001111F111uuuuuuAAAAAA. */ +{ "maxidl", 0x2E4F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* maxidl<.f> 0,limm,u6 0010111001001111F111uuuuuu111110. */ +{ "maxidl", 0x2E4F703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,u6 0010111011001111F111uuuuuu1QQQQQ. */ +{ "maxidl", 0x2ECF7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* maxidl<.f> 0,limm,s12 0010111010001111F111ssssssSSSSSS. */ +{ "maxidl", 0x2E8F7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* maxidl<.f> a,limm,limm 0010111000001111F111111110AAAAAA. */ +{ "maxidl", 0x2E0F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* maxidl<.f> 0,limm,limm 0010111000001111F111111110111110. */ +{ "maxidl", 0x2E0F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* maxidl<.f><.cc> 0,limm,limm 0010111011001111F1111111100QQQQQ. */ +{ "maxidl", 0x2ECF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* min<.f> a,b,c 00100bbb00001001FBBBCCCCCCAAAAAA. */ +{ "min", 0x20090000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* min<.f> 0,b,c 00100bbb00001001FBBBCCCCCC111110. */ +{ "min", 0x2009003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* min<.f><.cc> b,b,c 00100bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "min", 0x20C90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* min<.f> a,b,u6 00100bbb01001001FBBBuuuuuuAAAAAA. */ +{ "min", 0x20490000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* min<.f> 0,b,u6 00100bbb01001001FBBBuuuuuu111110. */ +{ "min", 0x2049003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* min<.f><.cc> b,b,u6 00100bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "min", 0x20C90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* min<.f> b,b,s12 00100bbb10001001FBBBssssssSSSSSS. */ +{ "min", 0x20890000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* min<.f> a,limm,c 0010011000001001F111CCCCCCAAAAAA. */ +{ "min", 0x26097000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* min<.f> a,b,limm 00100bbb00001001FBBB111110AAAAAA. */ +{ "min", 0x20090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* min<.f> 0,limm,c 0010011000001001F111CCCCCC111110. */ +{ "min", 0x2609703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* min<.f> 0,b,limm 00100bbb00001001FBBB111110111110. */ +{ "min", 0x20090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* min<.f><.cc> b,b,limm 00100bbb11001001FBBB1111100QQQQQ. */ +{ "min", 0x20C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* min<.f><.cc> 0,limm,c 0010011011001001F111CCCCCC0QQQQQ. */ +{ "min", 0x26C97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* min<.f> a,limm,u6 0010011001001001F111uuuuuuAAAAAA. */ +{ "min", 0x26497000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* min<.f> 0,limm,u6 0010011001001001F111uuuuuu111110. */ +{ "min", 0x2649703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* min<.f><.cc> 0,limm,u6 0010011011001001F111uuuuuu1QQQQQ. */ +{ "min", 0x26C97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* min<.f> 0,limm,s12 0010011010001001F111ssssssSSSSSS. */ +{ "min", 0x26897000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* min<.f> a,limm,limm 0010011000001001F111111110AAAAAA. */ +{ "min", 0x26097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* min<.f> 0,limm,limm 0010011000001001F111111110111110. */ +{ "min", 0x26097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* min<.f><.cc> 0,limm,limm 0010011011001001F1111111100QQQQQ. */ +{ "min", 0x26C97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* minidl<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ +{ "minidl", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* minidl<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ +{ "minidl", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* minidl<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "minidl", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* minidl<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ +{ "minidl", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* minidl<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ +{ "minidl", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* minidl<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "minidl", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* minidl<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ +{ "minidl", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* minidl<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ +{ "minidl", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* minidl<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ +{ "minidl", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* minidl<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ +{ "minidl", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* minidl<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ +{ "minidl", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ +{ "minidl", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* minidl<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ +{ "minidl", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* minidl<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ +{ "minidl", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* minidl<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ +{ "minidl", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ +{ "minidl", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* minidl<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ +{ "minidl", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* minidl<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ +{ "minidl", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* minidl<.f> 0,limm,limm 0010111000001001F111111110111110. */ +{ "minidl", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* minidl<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ +{ "minidl", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mov<.f> b,c 00100bbb00001010FBBBCCCCCCRRRRRR. */ +{ "mov", 0x200A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_F }}, + +/* mov<.f> 0,c 0010011000001010F111CCCCCCRRRRRR. */ +{ "mov", 0x260A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, RC }, { C_F }}, + +/* mov<.f><.cc> b,c 00100bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "mov", 0x20CA0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,c 0010011011001010F111CCCCCC0QQQQQ. */ +{ "mov", 0x26CA7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, RC }, { C_F, C_CC }}, + +/* mov<.f> b,u6 00100bbb01001010FBBBuuuuuuRRRRRR. */ +{ "mov", 0x204A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* mov<.f> 0,u6 0010011001001010F111uuuuuuRRRRRR. */ +{ "mov", 0x264A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,u6 0010011011001010F111uuuuuu1QQQQQ. */ +{ "mov", 0x26CA7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_20 }, { C_F, C_CC }}, + +/* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */ +{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, SIMM12_20 }, { C_F }}, + +/* mov<.f> 0,s12 0010011010001010F111ssssssSSSSSS. */ +{ "mov", 0x268A7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, SIMM12_20 }, { C_F }}, + +/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */ +{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_F }}, + +/* mov<.f> 0,limm 0010011000001010F111111110RRRRRR. */ +{ "mov", 0x260A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, LIMM }, { C_F }}, + +/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */ +{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_F, C_CC }}, + +/* mov<.f><.cc> 0,limm 0010011011001010F1111111100QQQQQ. */ +{ "mov", 0x26CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, LIMM }, { C_F, C_CC }}, + +/* mov_s b,h 01110bbbhhh01HHH. */ +{ "mov_s", 0x00007008, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RB_S, R6H }, { 0 }}, + +/* mov_s b,h 01110bbbhhh010HH. */ +{ "mov_s", 0x00007008, 0x0000F81C, 0, MEMORY, NONE, { RB_S, RH_S }, { 0 }}, + +/* mov_s h,b 01110bbbhhh11HHH. */ +{ "mov_s", 0x00007018, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { R6H, RB_S }, { 0 }}, + +/* mov_s h,b 01110bbbhhh110HH. */ +{ "mov_s", 0x00007018, 0x0000F81C, 0, MEMORY, NONE, { RH_S, RB_S }, { 0 }}, + +/* mov_s 0,b 01110bbb1101111H. */ +{ "mov_s", 0x000070DE, 0x0000F8FE, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { ZA_S, RB_S }, { 0 }}, + +/* mov_s 0,b 01110bbb11011011. */ +{ "mov_s", 0x000070DB, 0x0000F8FF, 0, MEMORY, NONE, { ZA_S, RB_S }, { 0 }}, + +/* mov_s g,h 01000ggghhhGG0HH. */ +{ "mov_s", 0x00004000, 0x0000F804, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { G_S, RH_S }, { 0 }}, + +/* mov_s 0,h 01000110hhh110HH. */ +{ "mov_s", 0x00004618, 0x0000FF1C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, RH_S }, { 0 }}, + +/* mov_s h,s3 01110ssshhh011HH. */ +{ "mov_s", 0x0000700C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RH_S, SIMM3_5_S }, { 0 }}, + +/* mov_s 0,s3 01110sss11001111. */ +{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, SIMM3_5_S }, { 0 }}, + +/* mov_s b,u8 11011bbbuuuuuuuu. */ +{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, UIMM8_8_S }, { 0 }}, + +/* mov_s b,limm 01110bbb11001111. */ +{ "mov_s", 0x000070CF, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RB_S, LIMM_S }, { 0 }}, + +/* mov_s b,limm 01110bbb11001011. */ +{ "mov_s", 0x000070CB, 0x0000F8FF, 0, MEMORY, NONE, { RB_S, LIMM_S }, { 0 }}, + +/* mov_s g,limm 01000ggg110GG011. */ +{ "mov_s", 0x000040C3, 0x0000F8E7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { G_S, LIMM_S }, { 0 }}, + +/* mov_s 0,limm 0100011011011011. */ +{ "mov_s", 0x000046DB, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA_S, LIMM_S }, { 0 }}, + +/* mov_s.ne b,h 01110bbbhhh111HH. */ +{ "mov_s", 0x0000701C, 0x0000F81C, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, RH_S }, { C_NE }}, + +/* mov_s.ne b,limm 01110bbb11011111. */ +{ "mov_s", 0x000070DF, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, LIMM_S }, { C_NE }}, + +/* mpy<.f> a,b,c 00100bbb00011010FBBBCCCCCCAAAAAA. */ +{ "mpy", 0x201A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }}, + +/* mpy<.f> 0,b,c 00100bbb00011010FBBBCCCCCC111110. */ +{ "mpy", 0x201A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }}, + +/* mpy<.f><.cc> b,b,c 00100bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "mpy", 0x20DA0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */ +{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpy<.f> 0,b,u6 00100bbb01011010FBBBuuuuuu111110. */ +{ "mpy", 0x205A003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpy<.f><.cc> b,b,u6 00100bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "mpy", 0x20DA0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpy<.f> b,b,s12 00100bbb10011010FBBBssssssSSSSSS. */ +{ "mpy", 0x209A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpy<.f> a,limm,c 0010011000011010F111CCCCCCAAAAAA. */ +{ "mpy", 0x261A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }}, + +/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */ +{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, + +/* mpy<.f> 0,limm,c 0010011000011010F111CCCCCC111110. */ +{ "mpy", 0x261A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }}, + +/* mpy<.f> 0,b,limm 00100bbb00011010FBBB111110111110. */ +{ "mpy", 0x201A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }}, + +/* mpy<.f><.cc> b,b,limm 00100bbb11011010FBBB1111100QQQQQ. */ +{ "mpy", 0x20DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpy<.f><.cc> 0,limm,c 0010011011011010F111CCCCCC0QQQQQ. */ +{ "mpy", 0x26DA7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpy<.f> a,limm,u6 0010011001011010F111uuuuuuAAAAAA. */ +{ "mpy", 0x265A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpy<.f> 0,limm,u6 0010011001011010F111uuuuuu111110. */ +{ "mpy", 0x265A703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpy<.f><.cc> 0,limm,u6 0010011011011010F111uuuuuu1QQQQQ. */ +{ "mpy", 0x26DA7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpy<.f> 0,limm,s12 0010011010011010F111ssssssSSSSSS. */ +{ "mpy", 0x269A7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpy<.f> a,limm,limm 0010011000011010F111111110AAAAAA. */ +{ "mpy", 0x261A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpy<.f> 0,limm,limm 0010011000011010F111111110111110. */ +{ "mpy", 0x261A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpy<.f><.cc> 0,limm,limm 0010011011011010F1111111100QQQQQ. */ +{ "mpy", 0x26DA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyd<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ +{ "mpyd", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }}, + +/* mpyd<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ +{ "mpyd", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }}, + +/* mpyd<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "mpyd", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyd<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ +{ "mpyd", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyd<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ +{ "mpyd", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyd<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "mpyd", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyd<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ +{ "mpyd", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyd<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ +{ "mpyd", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }}, + +/* mpyd<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ +{ "mpyd", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }}, + +/* mpyd<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ +{ "mpyd", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }}, + +/* mpyd<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ +{ "mpyd", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }}, + +/* mpyd<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ +{ "mpyd", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyd<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ +{ "mpyd", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyd<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ +{ "mpyd", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyd<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ +{ "mpyd", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyd<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ +{ "mpyd", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyd<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ +{ "mpyd", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyd<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ +{ "mpyd", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyd<.f> 0,limm,limm 0010111000011000F111111110111110. */ +{ "mpyd", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyd<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ +{ "mpyd", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpydf<.f> a,b,c 00110bbb00010010FBBBCCCCCCAAAAAA. */ +{ "mpydf", 0x30120000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* mpydf<.f> 0,b,c 00110bbb00010010FBBBCCCCCC111110. */ +{ "mpydf", 0x3012003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpydf<.f><.cc> b,b,c 00110bbb11010010FBBBCCCCCC0QQQQQ. */ +{ "mpydf", 0x30D20000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpydf<.f> a,b,u6 00110bbb01010010FBBBuuuuuuAAAAAA. */ +{ "mpydf", 0x30520000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpydf<.f> 0,b,u6 00110bbb01010010FBBBuuuuuu111110. */ +{ "mpydf", 0x3052003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpydf<.f><.cc> b,b,u6 00110bbb11010010FBBBuuuuuu1QQQQQ. */ +{ "mpydf", 0x30D20020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpydf<.f> b,b,s12 00110bbb10010010FBBBssssssSSSSSS. */ +{ "mpydf", 0x30920000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpydf<.f> a,limm,c 0011011000010010F111CCCCCCAAAAAA. */ +{ "mpydf", 0x36127000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpydf<.f> a,b,limm 00110bbb00010010FBBB111110AAAAAA. */ +{ "mpydf", 0x30120F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpydf<.f> 0,limm,c 0011011000010010F111CCCCCC111110. */ +{ "mpydf", 0x3612703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpydf<.f> 0,b,limm 00110bbb00010010FBBB111110111110. */ +{ "mpydf", 0x30120FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpydf<.f><.cc> b,b,limm 00110bbb11010010FBBB1111100QQQQQ. */ +{ "mpydf", 0x30D20F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpydf<.f><.cc> 0,limm,c 0011011011010010F111CCCCCC0QQQQQ. */ +{ "mpydf", 0x36D27000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpydf<.f> a,limm,u6 0011011001010010F111uuuuuuAAAAAA. */ +{ "mpydf", 0x36527000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpydf<.f> 0,limm,u6 0011011001010010F111uuuuuu111110. */ +{ "mpydf", 0x3652703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpydf<.f><.cc> 0,limm,u6 0011011011010010F111uuuuuu1QQQQQ. */ +{ "mpydf", 0x36D27020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpydf<.f> 0,limm,s12 0011011010010010F111ssssssSSSSSS. */ +{ "mpydf", 0x36927000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpydf<.f> a,limm,limm 0011011000010010F111111110AAAAAA. */ +{ "mpydf", 0x36127F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpydf<.f> 0,limm,limm 0011011000010010F111111110111110. */ +{ "mpydf", 0x36127FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpydf<.f><.cc> 0,limm,limm 0011011011010010F1111111100QQQQQ. */ +{ "mpydf", 0x36D27F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpydu<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ +{ "mpydu", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { C_F }}, + +/* mpydu<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ +{ "mpydu", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { C_F }}, + +/* mpydu<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "mpydu", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpydu<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ +{ "mpydu", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpydu<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ +{ "mpydu", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpydu<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "mpydu", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpydu<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ +{ "mpydu", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpydu<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ +{ "mpydu", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { C_F }}, + +/* mpydu<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ +{ "mpydu", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { C_F }}, + +/* mpydu<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ +{ "mpydu", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F }}, + +/* mpydu<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ +{ "mpydu", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { C_F }}, + +/* mpydu<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ +{ "mpydu", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpydu<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ +{ "mpydu", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpydu<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ +{ "mpydu", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpydu<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ +{ "mpydu", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpydu<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ +{ "mpydu", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpydu<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ +{ "mpydu", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpydu<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ +{ "mpydu", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpydu<.f> 0,limm,limm 0010111000011001F111111110111110. */ +{ "mpydu", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpydu<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ +{ "mpydu", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyf<.f> a,b,c 00110bbb00001010FBBBCCCCCCAAAAAA. */ +{ "mpyf", 0x300A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyf<.f> 0,b,c 00110bbb00001010FBBBCCCCCC111110. */ +{ "mpyf", 0x300A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyf<.f><.cc> b,b,c 00110bbb11001010FBBBCCCCCC0QQQQQ. */ +{ "mpyf", 0x30CA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyf<.f> a,b,u6 00110bbb01001010FBBBuuuuuuAAAAAA. */ +{ "mpyf", 0x304A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyf<.f> 0,b,u6 00110bbb01001010FBBBuuuuuu111110. */ +{ "mpyf", 0x304A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyf<.f><.cc> b,b,u6 00110bbb11001010FBBBuuuuuu1QQQQQ. */ +{ "mpyf", 0x30CA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyf<.f> b,b,s12 00110bbb10001010FBBBssssssSSSSSS. */ +{ "mpyf", 0x308A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyf<.f> a,limm,c 0011011000001010F111CCCCCCAAAAAA. */ +{ "mpyf", 0x360A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyf<.f> a,b,limm 00110bbb00001010FBBB111110AAAAAA. */ +{ "mpyf", 0x300A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyf<.f> 0,limm,c 0011011000001010F111CCCCCC111110. */ +{ "mpyf", 0x360A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyf<.f> 0,b,limm 00110bbb00001010FBBB111110111110. */ +{ "mpyf", 0x300A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyf<.f><.cc> b,b,limm 00110bbb11001010FBBB1111100QQQQQ. */ +{ "mpyf", 0x30CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyf<.f><.cc> 0,limm,c 0011011011001010F111CCCCCC0QQQQQ. */ +{ "mpyf", 0x36CA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyf<.f> a,limm,u6 0011011001001010F111uuuuuuAAAAAA. */ +{ "mpyf", 0x364A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyf<.f> 0,limm,u6 0011011001001010F111uuuuuu111110. */ +{ "mpyf", 0x364A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyf<.f><.cc> 0,limm,u6 0011011011001010F111uuuuuu1QQQQQ. */ +{ "mpyf", 0x36CA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyf<.f> 0,limm,s12 0011011010001010F111ssssssSSSSSS. */ +{ "mpyf", 0x368A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyf<.f> a,limm,limm 0011011000001010F111111110AAAAAA. */ +{ "mpyf", 0x360A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyf<.f> 0,limm,limm 0011011000001010F111111110111110. */ +{ "mpyf", 0x360A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyf<.f><.cc> 0,limm,limm 0011011011001010F1111111100QQQQQ. */ +{ "mpyf", 0x36CA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyfr<.f> a,b,c 00110bbb00001011FBBBCCCCCCAAAAAA. */ +{ "mpyfr", 0x300B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyfr<.f> 0,b,c 00110bbb00001011FBBBCCCCCC111110. */ +{ "mpyfr", 0x300B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,c 00110bbb11001011FBBBCCCCCC0QQQQQ. */ +{ "mpyfr", 0x30CB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyfr<.f> a,b,u6 00110bbb01001011FBBBuuuuuuAAAAAA. */ +{ "mpyfr", 0x304B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyfr<.f> 0,b,u6 00110bbb01001011FBBBuuuuuu111110. */ +{ "mpyfr", 0x304B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,u6 00110bbb11001011FBBBuuuuuu1QQQQQ. */ +{ "mpyfr", 0x30CB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyfr<.f> b,b,s12 00110bbb10001011FBBBssssssSSSSSS. */ +{ "mpyfr", 0x308B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyfr<.f> a,limm,c 0011011000001011F111CCCCCCAAAAAA. */ +{ "mpyfr", 0x360B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyfr<.f> a,b,limm 00110bbb00001011FBBB111110AAAAAA. */ +{ "mpyfr", 0x300B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyfr<.f> 0,limm,c 0011011000001011F111CCCCCC111110. */ +{ "mpyfr", 0x360B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyfr<.f> 0,b,limm 00110bbb00001011FBBB111110111110. */ +{ "mpyfr", 0x300B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyfr<.f><.cc> b,b,limm 00110bbb11001011FBBB1111100QQQQQ. */ +{ "mpyfr", 0x30CB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyfr<.f><.cc> 0,limm,c 0011011011001011F111CCCCCC0QQQQQ. */ +{ "mpyfr", 0x36CB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyfr<.f> a,limm,u6 0011011001001011F111uuuuuuAAAAAA. */ +{ "mpyfr", 0x364B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyfr<.f> 0,limm,u6 0011011001001011F111uuuuuu111110. */ +{ "mpyfr", 0x364B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyfr<.f><.cc> 0,limm,u6 0011011011001011F111uuuuuu1QQQQQ. */ +{ "mpyfr", 0x36CB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyfr<.f> 0,limm,s12 0011011010001011F111ssssssSSSSSS. */ +{ "mpyfr", 0x368B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyfr<.f> a,limm,limm 0011011000001011F111111110AAAAAA. */ +{ "mpyfr", 0x360B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyfr<.f> 0,limm,limm 0011011000001011F111111110111110. */ +{ "mpyfr", 0x360B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyfr<.f><.cc> 0,limm,limm 0011011011001011F1111111100QQQQQ. */ +{ "mpyfr", 0x36CB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyh<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ +{ "mpyh", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyh<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ +{ "mpyh", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyh<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "mpyh", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyh<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ +{ "mpyh", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyh<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ +{ "mpyh", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyh<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "mpyh", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyh<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ +{ "mpyh", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyh<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ +{ "mpyh", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyh<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ +{ "mpyh", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyh<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ +{ "mpyh", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyh<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ +{ "mpyh", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyh<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ +{ "mpyh", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyh<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ +{ "mpyh", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyh<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ +{ "mpyh", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyh<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ +{ "mpyh", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyh<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ +{ "mpyh", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyh<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ +{ "mpyh", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyh<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ +{ "mpyh", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyh<.f> 0,limm,limm 0010011000011011F111111110111110. */ +{ "mpyh", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyh<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ +{ "mpyh", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyhu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpyhu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyhu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ +{ "mpyhu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpyhu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyhu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpyhu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyhu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ +{ "mpyhu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpyhu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyhu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ +{ "mpyhu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyhu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ +{ "mpyhu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyhu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ +{ "mpyhu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyhu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ +{ "mpyhu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyhu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ +{ "mpyhu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyhu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ +{ "mpyhu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyhu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ +{ "mpyhu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyhu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ +{ "mpyhu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyhu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ +{ "mpyhu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyhu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ +{ "mpyhu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyhu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ +{ "mpyhu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyhu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ +{ "mpyhu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyhu<.f> 0,limm,limm 0010011000011100F111111110111110. */ +{ "mpyhu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyhu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ +{ "mpyhu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpym<.f> a,b,c 00100bbb00011011FBBBCCCCCCAAAAAA. */ +{ "mpym", 0x201B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }}, + +/* mpym<.f> 0,b,c 00100bbb00011011FBBBCCCCCC111110. */ +{ "mpym", 0x201B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }}, + +/* mpym<.f><.cc> b,b,c 00100bbb11011011FBBBCCCCCC0QQQQQ. */ +{ "mpym", 0x20DB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpym<.f> a,b,u6 00100bbb01011011FBBBuuuuuuAAAAAA. */ +{ "mpym", 0x205B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpym<.f> 0,b,u6 00100bbb01011011FBBBuuuuuu111110. */ +{ "mpym", 0x205B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpym<.f><.cc> b,b,u6 00100bbb11011011FBBBuuuuuu1QQQQQ. */ +{ "mpym", 0x20DB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpym<.f> b,b,s12 00100bbb10011011FBBBssssssSSSSSS. */ +{ "mpym", 0x209B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpym<.f> a,limm,c 0010011000011011F111CCCCCCAAAAAA. */ +{ "mpym", 0x261B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }}, + +/* mpym<.f> a,b,limm 00100bbb00011011FBBB111110AAAAAA. */ +{ "mpym", 0x201B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, + +/* mpym<.f> 0,limm,c 0010011000011011F111CCCCCC111110. */ +{ "mpym", 0x261B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }}, + +/* mpym<.f> 0,b,limm 00100bbb00011011FBBB111110111110. */ +{ "mpym", 0x201B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }}, + +/* mpym<.f><.cc> b,b,limm 00100bbb11011011FBBB1111100QQQQQ. */ +{ "mpym", 0x20DB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpym<.f><.cc> 0,limm,c 0010011011011011F111CCCCCC0QQQQQ. */ +{ "mpym", 0x26DB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpym<.f> a,limm,u6 0010011001011011F111uuuuuuAAAAAA. */ +{ "mpym", 0x265B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpym<.f> 0,limm,u6 0010011001011011F111uuuuuu111110. */ +{ "mpym", 0x265B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpym<.f><.cc> 0,limm,u6 0010011011011011F111uuuuuu1QQQQQ. */ +{ "mpym", 0x26DB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpym<.f> 0,limm,s12 0010011010011011F111ssssssSSSSSS. */ +{ "mpym", 0x269B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpym<.f> a,limm,limm 0010011000011011F111111110AAAAAA. */ +{ "mpym", 0x261B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpym<.f> 0,limm,limm 0010011000011011F111111110111110. */ +{ "mpym", 0x261B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpym<.f><.cc> 0,limm,limm 0010011011011011F1111111100QQQQQ. */ +{ "mpym", 0x26DB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpymu<.f> a,b,c 00100bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpymu", 0x201C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }}, + +/* mpymu<.f> 0,b,c 00100bbb00011100FBBBCCCCCC111110. */ +{ "mpymu", 0x201C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }}, + +/* mpymu<.f><.cc> b,b,c 00100bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpymu", 0x20DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpymu<.f> a,b,u6 00100bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpymu", 0x205C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpymu<.f> 0,b,u6 00100bbb01011100FBBBuuuuuu111110. */ +{ "mpymu", 0x205C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpymu<.f><.cc> b,b,u6 00100bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpymu", 0x20DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpymu<.f> b,b,s12 00100bbb10011100FBBBssssssSSSSSS. */ +{ "mpymu", 0x209C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpymu<.f> a,limm,c 0010011000011100F111CCCCCCAAAAAA. */ +{ "mpymu", 0x261C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }}, + +/* mpymu<.f> a,b,limm 00100bbb00011100FBBB111110AAAAAA. */ +{ "mpymu", 0x201C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, + +/* mpymu<.f> 0,limm,c 0010011000011100F111CCCCCC111110. */ +{ "mpymu", 0x261C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }}, + +/* mpymu<.f> 0,b,limm 00100bbb00011100FBBB111110111110. */ +{ "mpymu", 0x201C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }}, + +/* mpymu<.f><.cc> b,b,limm 00100bbb11011100FBBB1111100QQQQQ. */ +{ "mpymu", 0x20DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpymu<.f><.cc> 0,limm,c 0010011011011100F111CCCCCC0QQQQQ. */ +{ "mpymu", 0x26DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpymu<.f> a,limm,u6 0010011001011100F111uuuuuuAAAAAA. */ +{ "mpymu", 0x265C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpymu<.f> 0,limm,u6 0010011001011100F111uuuuuu111110. */ +{ "mpymu", 0x265C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpymu<.f><.cc> 0,limm,u6 0010011011011100F111uuuuuu1QQQQQ. */ +{ "mpymu", 0x26DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpymu<.f> 0,limm,s12 0010011010011100F111ssssssSSSSSS. */ +{ "mpymu", 0x269C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpymu<.f> a,limm,limm 0010011000011100F111111110AAAAAA. */ +{ "mpymu", 0x261C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpymu<.f> 0,limm,limm 0010011000011100F111111110111110. */ +{ "mpymu", 0x261C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpymu<.f><.cc> 0,limm,limm 0010011011011100F1111111100QQQQQ. */ +{ "mpymu", 0x26DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyqb<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "mpyqb", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyqb<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ +{ "mpyqb", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyqb<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "mpyqb", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyqb<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ +{ "mpyqb", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyqb<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ +{ "mpyqb", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyqb<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ +{ "mpyqb", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyqb<.f><.cc> b,b,limm 00110bbb11100101FBBB1111100QQQQQ. */ +{ "mpyqb", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyu<.f> a,b,c 00100bbb00011101FBBBCCCCCCAAAAAA. */ +{ "mpyu", 0x201D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, RC }, { C_F }}, + +/* mpyu<.f> 0,b,c 00100bbb00011101FBBBCCCCCC111110. */ +{ "mpyu", 0x201D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, RC }, { C_F }}, + +/* mpyu<.f><.cc> b,b,c 00100bbb11011101FBBBCCCCCC0QQQQQ. */ +{ "mpyu", 0x20DD0000, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyu<.f> a,b,u6 00100bbb01011101FBBBuuuuuuAAAAAA. */ +{ "mpyu", 0x205D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyu<.f> 0,b,u6 00100bbb01011101FBBBuuuuuu111110. */ +{ "mpyu", 0x205D003E, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyu<.f><.cc> b,b,u6 00100bbb11011101FBBBuuuuuu1QQQQQ. */ +{ "mpyu", 0x20DD0020, 0xF8FF0020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyu<.f> b,b,s12 00100bbb10011101FBBBssssssSSSSSS. */ +{ "mpyu", 0x209D0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyu<.f> a,limm,c 0010011000011101F111CCCCCCAAAAAA. */ +{ "mpyu", 0x261D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, RC }, { C_F }}, + +/* mpyu<.f> a,b,limm 00100bbb00011101FBBB111110AAAAAA. */ +{ "mpyu", 0x201D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }}, + +/* mpyu<.f> 0,limm,c 0010011000011101F111CCCCCC111110. */ +{ "mpyu", 0x261D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F }}, + +/* mpyu<.f> 0,b,limm 00100bbb00011101FBBB111110111110. */ +{ "mpyu", 0x201D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, RB, LIMM }, { C_F }}, + +/* mpyu<.f><.cc> b,b,limm 00100bbb11011101FBBB1111100QQQQQ. */ +{ "mpyu", 0x20DD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyu<.f><.cc> 0,limm,c 0010011011011101F111CCCCCC0QQQQQ. */ +{ "mpyu", 0x26DD7000, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyu<.f> a,limm,u6 0010011001011101F111uuuuuuAAAAAA. */ +{ "mpyu", 0x265D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyu<.f> 0,limm,u6 0010011001011101F111uuuuuu111110. */ +{ "mpyu", 0x265D703E, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyu<.f><.cc> 0,limm,u6 0010011011011101F111uuuuuu1QQQQQ. */ +{ "mpyu", 0x26DD7020, 0xFFFF7020, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyu<.f> 0,limm,s12 0010011010011101F111ssssssSSSSSS. */ +{ "mpyu", 0x269D7000, 0xFFFF7000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyu<.f> a,limm,limm 0010011000011101F111111110AAAAAA. */ +{ "mpyu", 0x261D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyu<.f> 0,limm,limm 0010011000011101F111111110111110. */ +{ "mpyu", 0x261D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyu<.f><.cc> 0,limm,limm 0010011011011101F1111111100QQQQQ. */ +{ "mpyu", 0x26DD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ +{ "mpyuw", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyuw<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ +{ "mpyuw", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ +{ "mpyuw", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,c 00100bbb00011111FBBBCCCCCCAAAAAA. */ +{ "mpyuw", 0x201F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, RC }, { C_F }}, + +/* mpyuw<.f> 0,b,c 00100bbb00011111FBBBCCCCCC111110. */ +{ "mpyuw", 0x201F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, RC }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,c 00100bbb11011111FBBBCCCCCC0QQQQQ. */ +{ "mpyuw", 0x20DF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ +{ "mpyuw", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ +{ "mpyuw", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ +{ "mpyuw", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> a,b,u6 00100bbb01011111FBBBuuuuuuAAAAAA. */ +{ "mpyuw", 0x205F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,b,u6 00100bbb01011111FBBBuuuuuu111110. */ +{ "mpyuw", 0x205F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,u6 00100bbb11011111FBBBuuuuuu1QQQQQ. */ +{ "mpyuw", 0x20DF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ +{ "mpyuw", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> b,b,s12 00100bbb10011111FBBBssssssSSSSSS. */ +{ "mpyuw", 0x209F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ +{ "mpyuw", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyuw<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ +{ "mpyuw", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyuw<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ +{ "mpyuw", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyuw<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ +{ "mpyuw", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ +{ "mpyuw", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyuw<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ +{ "mpyuw", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,c 0010011000011111F111CCCCCCAAAAAA. */ +{ "mpyuw", 0x261F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, RC }, { C_F }}, + +/* mpyuw<.f> a,b,limm 00100bbb00011111FBBB111110AAAAAA. */ +{ "mpyuw", 0x201F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, LIMM }, { C_F }}, + +/* mpyuw<.f> 0,limm,c 0010011000011111F111CCCCCC111110. */ +{ "mpyuw", 0x261F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F }}, + +/* mpyuw<.f> 0,b,limm 00100bbb00011111FBBB111110111110. */ +{ "mpyuw", 0x201F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, LIMM }, { C_F }}, + +/* mpyuw<.f><.cc> b,b,limm 00100bbb11011111FBBB1111100QQQQQ. */ +{ "mpyuw", 0x20DF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyuw<.f><.cc> 0,limm,c 0010011011011111F111CCCCCC0QQQQQ. */ +{ "mpyuw", 0x26DF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ +{ "mpyuw", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ +{ "mpyuw", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ +{ "mpyuw", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,u6 0010011001011111F111uuuuuuAAAAAA. */ +{ "mpyuw", 0x265F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,u6 0010011001011111F111uuuuuu111110. */ +{ "mpyuw", 0x265F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,u6 0010011011011111F111uuuuuu1QQQQQ. */ +{ "mpyuw", 0x26DF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyuw<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ +{ "mpyuw", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> 0,limm,s12 0010011010011111F111ssssssSSSSSS. */ +{ "mpyuw", 0x269F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyuw<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ +{ "mpyuw", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyuw<.f> 0,limm,limm 0010011000111111F111111110111110. */ +{ "mpyuw", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ +{ "mpyuw", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyuw<.f> a,limm,limm 0010011000011111F111111110AAAAAA. */ +{ "mpyuw", 0x261F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyuw<.f> 0,limm,limm 0010011000011111F111111110111110. */ +{ "mpyuw", 0x261F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyuw<.f><.cc> 0,limm,limm 0010011011011111F1111111100QQQQQ. */ +{ "mpyuw", 0x26DF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyuw_s b,b,c 01111bbbccc01010. */ +{ "mpyuw_s", 0x0000780A, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* mpyw<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ +{ "mpyw", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* mpyw<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ +{ "mpyw", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpyw<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ +{ "mpyw", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,c 00100bbb00011110FBBBCCCCCCAAAAAA. */ +{ "mpyw", 0x201E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, RC }, { C_F }}, + +/* mpyw<.f> 0,b,c 00100bbb00011110FBBBCCCCCC111110. */ +{ "mpyw", 0x201E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, RC }, { C_F }}, + +/* mpyw<.f><.cc> b,b,c 00100bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "mpyw", 0x20DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ +{ "mpyw", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ +{ "mpyw", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ +{ "mpyw", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> a,b,u6 00100bbb01011110FBBBuuuuuuAAAAAA. */ +{ "mpyw", 0x205E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,b,u6 00100bbb01011110FBBBuuuuuu111110. */ +{ "mpyw", 0x205E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> b,b,u6 00100bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "mpyw", 0x20DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ +{ "mpyw", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyw<.f> b,b,s12 00100bbb10011110FBBBssssssSSSSSS. */ +{ "mpyw", 0x209E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpyw<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ +{ "mpyw", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpyw<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ +{ "mpyw", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpyw<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ +{ "mpyw", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpyw<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ +{ "mpyw", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpyw<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ +{ "mpyw", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyw<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ +{ "mpyw", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,c 0010011000011110F111CCCCCCAAAAAA. */ +{ "mpyw", 0x261E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, RC }, { C_F }}, + +/* mpyw<.f> a,b,limm 00100bbb00011110FBBB111110AAAAAA. */ +{ "mpyw", 0x201E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, RB, LIMM }, { C_F }}, + +/* mpyw<.f> 0,limm,c 0010011000011110F111CCCCCC111110. */ +{ "mpyw", 0x261E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F }}, + +/* mpyw<.f> 0,b,limm 00100bbb00011110FBBB111110111110. */ +{ "mpyw", 0x201E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, RB, LIMM }, { C_F }}, + +/* mpyw<.f><.cc> b,b,limm 00100bbb11011110FBBB1111100QQQQQ. */ +{ "mpyw", 0x20DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpyw<.f><.cc> 0,limm,c 0010011011011110F111CCCCCC0QQQQQ. */ +{ "mpyw", 0x26DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ +{ "mpyw", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ +{ "mpyw", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ +{ "mpyw", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,u6 0010011001011110F111uuuuuuAAAAAA. */ +{ "mpyw", 0x265E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,u6 0010011001011110F111uuuuuu111110. */ +{ "mpyw", 0x265E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,u6 0010011011011110F111uuuuuu1QQQQQ. */ +{ "mpyw", 0x26DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpyw<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ +{ "mpyw", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyw<.f> 0,limm,s12 0010011010011110F111ssssssSSSSSS. */ +{ "mpyw", 0x269E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpyw<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ +{ "mpyw", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyw<.f> 0,limm,limm 0010011000111110F111111110111110. */ +{ "mpyw", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ +{ "mpyw", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyw<.f> a,limm,limm 0010011000011110F111111110AAAAAA. */ +{ "mpyw", 0x261E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpyw<.f> 0,limm,limm 0010011000011110F111111110111110. */ +{ "mpyw", 0x261E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpyw<.f><.cc> 0,limm,limm 0010011011011110F1111111100QQQQQ. */ +{ "mpyw", 0x26DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,b,c 00110bbb00100100FBBBCCCCCCAAAAAA. */ +{ "mpywhfl", 0x30240000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhfl<.f> 0,b,c 00110bbb00100100FBBBCCCCCC111110. */ +{ "mpywhfl", 0x3024003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhfl<.f><.cc> b,b,c 00110bbb11100100FBBBCCCCCC0QQQQQ. */ +{ "mpywhfl", 0x30E40000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,b,u6 00110bbb01100100FBBBuuuuuuAAAAAA. */ +{ "mpywhfl", 0x30640000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f> 0,b,u6 00110bbb01100100FBBBuuuuuu111110. */ +{ "mpywhfl", 0x3064003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f><.cc> b,b,u6 00110bbb11100100FBBBuuuuuu1QQQQQ. */ +{ "mpywhfl", 0x30E40020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfl<.f> b,b,s12 00110bbb10100100FBBBssssssSSSSSS. */ +{ "mpywhfl", 0x30A40000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhfl<.f> a,limm,c 0011011000100100F111CCCCCCAAAAAA. */ +{ "mpywhfl", 0x36247000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhfl<.f> a,b,limm 00110bbb00100100FBBB111110AAAAAA. */ +{ "mpywhfl", 0x30240F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhfl<.f> 0,limm,c 0011011001100100F111CCCCCC111110. */ +{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhfl<.f> 0,b,limm 00110bbb00100100FBBB111110111110. */ +{ "mpywhfl", 0x30240FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,c 00110bbb11100100FBBB1111100QQQQQ. */ +{ "mpywhfl", 0x30E40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhfl<.f><.cc> b,b,limm 0011011011100100F111CCCCCC0QQQQQ. */ +{ "mpywhfl", 0x36E47000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhfl<.f> a,limm,u6 0011011001100100F111uuuuuuAAAAAA. */ +{ "mpywhfl", 0x36647000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f> 0,limm,u6 0011011001100100F111uuuuuu111110. */ +{ "mpywhfl", 0x3664703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,u6 0011011011100100F111uuuuuu1QQQQQ. */ +{ "mpywhfl", 0x36E47020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfl<.f> 0,limm,s12 0011011010100100F111ssssssSSSSSS. */ +{ "mpywhfl", 0x36A47000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhfl<.f> a,limm,limm 0011011000100100F111111110AAAAAA. */ +{ "mpywhfl", 0x36247F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfl<.f> 0,limm,limm 0011011000100100F111111110111110. */ +{ "mpywhfl", 0x36247FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfl<.f><.cc> 0,limm,limm 0011011011100100F1111111100QQQQQ. */ +{ "mpywhfl", 0x36E47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,b,c 00110bbb00100101FBBBCCCCCCAAAAAA. */ +{ "mpywhflr", 0x30250000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhflr<.f> 0,b,c 00110bbb00100101FBBBCCCCCC111110. */ +{ "mpywhflr", 0x3025003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhflr<.f><.cc> b,b,c 00110bbb11100101FBBBCCCCCC0QQQQQ. */ +{ "mpywhflr", 0x30E50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,b,u6 00110bbb01100101FBBBuuuuuuAAAAAA. */ +{ "mpywhflr", 0x30650000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f> 0,b,u6 00110bbb01100101FBBBuuuuuu111110. */ +{ "mpywhflr", 0x3065003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f><.cc> b,b,u6 00110bbb11100101FBBBuuuuuu1QQQQQ. */ +{ "mpywhflr", 0x30E50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhflr<.f> b,b,s12 00110bbb10100101FBBBssssssSSSSSS. */ +{ "mpywhflr", 0x30A50000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhflr<.f> a,limm,c 0011011000100101F111CCCCCCAAAAAA. */ +{ "mpywhflr", 0x36257000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhflr<.f> a,b,limm 00110bbb00100101FBBB111110AAAAAA. */ +{ "mpywhflr", 0x30250F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhflr<.f> 0,limm,c 0011011001100101F111CCCCCC111110. */ +{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhflr<.f> 0,b,limm 00110bbb00100101FBBB111110111110. */ +{ "mpywhflr", 0x30250FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,c 00110bbb11100101FBBB1111100QQQQQ. */ +{ "mpywhflr", 0x30E50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhflr<.f><.cc> b,b,limm 0011011011100101F111CCCCCC0QQQQQ. */ +{ "mpywhflr", 0x36E57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhflr<.f> a,limm,u6 0011011001100101F111uuuuuuAAAAAA. */ +{ "mpywhflr", 0x36657000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f> 0,limm,u6 0011011001100101F111uuuuuu111110. */ +{ "mpywhflr", 0x3665703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,u6 0011011011100101F111uuuuuu1QQQQQ. */ +{ "mpywhflr", 0x36E57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhflr<.f> 0,limm,s12 0011011010100101F111ssssssSSSSSS. */ +{ "mpywhflr", 0x36A57000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhflr<.f> a,limm,limm 0011011000100101F111111110AAAAAA. */ +{ "mpywhflr", 0x36257F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhflr<.f> 0,limm,limm 0011011000100101F111111110111110. */ +{ "mpywhflr", 0x36257FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhflr<.f><.cc> 0,limm,limm 0011011011100101F1111111100QQQQQ. */ +{ "mpywhflr", 0x36E57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ +{ "mpywhfm", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhfm<.f> 0,b,c 00110bbb00100000FBBBCCCCCC111110. */ +{ "mpywhfm", 0x3020003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhfm<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "mpywhfm", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ +{ "mpywhfm", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f> 0,b,u6 00110bbb01100000FBBBuuuuuu111110. */ +{ "mpywhfm", 0x3060003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "mpywhfm", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfm<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ +{ "mpywhfm", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhfm<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ +{ "mpywhfm", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhfm<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ +{ "mpywhfm", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhfm<.f> 0,limm,c 0011011001100000F111CCCCCC111110. */ +{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhfm<.f> 0,b,limm 00110bbb00100000FBBB111110111110. */ +{ "mpywhfm", 0x30200FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,c 00110bbb11100000FBBB1111100QQQQQ. */ +{ "mpywhfm", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhfm<.f><.cc> b,b,limm 0011011011100000F111CCCCCC0QQQQQ. */ +{ "mpywhfm", 0x36E07000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhfm<.f> a,limm,u6 0011011001100000F111uuuuuuAAAAAA. */ +{ "mpywhfm", 0x36607000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f> 0,limm,u6 0011011001100000F111uuuuuu111110. */ +{ "mpywhfm", 0x3660703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,u6 0011011011100000F111uuuuuu1QQQQQ. */ +{ "mpywhfm", 0x36E07020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfm<.f> 0,limm,s12 0011011010100000F111ssssssSSSSSS. */ +{ "mpywhfm", 0x36A07000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhfm<.f> a,limm,limm 0011011000100000F111111110AAAAAA. */ +{ "mpywhfm", 0x36207F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfm<.f> 0,limm,limm 0011011000100000F111111110111110. */ +{ "mpywhfm", 0x36207FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfm<.f><.cc> 0,limm,limm 0011011011100000F1111111100QQQQQ. */ +{ "mpywhfm", 0x36E07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ +{ "mpywhfmr", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhfmr<.f> 0,b,c 00110bbb00100001FBBBCCCCCC111110. */ +{ "mpywhfmr", 0x3021003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhfmr<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "mpywhfmr", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ +{ "mpywhfmr", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f> 0,b,u6 00110bbb01100001FBBBuuuuuu111110. */ +{ "mpywhfmr", 0x3061003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f><.cc> b,b,u6 00110bbb11100001FBBBuuuuuu1QQQQQ. */ +{ "mpywhfmr", 0x30E10020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfmr<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ +{ "mpywhfmr", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhfmr<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ +{ "mpywhfmr", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhfmr<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ +{ "mpywhfmr", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,c 0011011001100001F111CCCCCC111110. */ +{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhfmr<.f> 0,b,limm 00110bbb00100001FBBB111110111110. */ +{ "mpywhfmr", 0x30210FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,c 00110bbb11100001FBBB1111100QQQQQ. */ +{ "mpywhfmr", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhfmr<.f><.cc> b,b,limm 0011011011100001F111CCCCCC0QQQQQ. */ +{ "mpywhfmr", 0x36E17000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhfmr<.f> a,limm,u6 0011011001100001F111uuuuuuAAAAAA. */ +{ "mpywhfmr", 0x36617000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,u6 0011011001100001F111uuuuuu111110. */ +{ "mpywhfmr", 0x3661703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,u6 0011011011100001F111uuuuuu1QQQQQ. */ +{ "mpywhfmr", 0x36E17020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhfmr<.f> 0,limm,s12 0011011010100001F111ssssssSSSSSS. */ +{ "mpywhfmr", 0x36A17000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhfmr<.f> a,limm,limm 0011011000100001F111111110AAAAAA. */ +{ "mpywhfmr", 0x36217F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfmr<.f> 0,limm,limm 0011011000100001F111111110111110. */ +{ "mpywhfmr", 0x36217FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhfmr<.f><.cc> 0,limm,limm 0011011011100001F1111111100QQQQQ. */ +{ "mpywhfmr", 0x36E17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhl<.f> a,b,c 00110bbb00011100FBBBCCCCCCAAAAAA. */ +{ "mpywhl", 0x301C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhl<.f> 0,b,c 00110bbb00011100FBBBCCCCCC111110. */ +{ "mpywhl", 0x301C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhl<.f><.cc> b,b,c 00110bbb11011100FBBBCCCCCC0QQQQQ. */ +{ "mpywhl", 0x30DC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhl<.f> a,b,u6 00110bbb01011100FBBBuuuuuuAAAAAA. */ +{ "mpywhl", 0x305C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhl<.f> 0,b,u6 00110bbb01011100FBBBuuuuuu111110. */ +{ "mpywhl", 0x305C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhl<.f><.cc> b,b,u6 00110bbb11011100FBBBuuuuuu1QQQQQ. */ +{ "mpywhl", 0x30DC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhl<.f> b,b,s12 00110bbb10011100FBBBssssssSSSSSS. */ +{ "mpywhl", 0x309C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhl<.f> a,limm,c 0011011000011100F111CCCCCCAAAAAA. */ +{ "mpywhl", 0x361C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhl<.f> a,b,limm 00110bbb00011100FBBB111110AAAAAA. */ +{ "mpywhl", 0x301C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhl<.f> 0,limm,c 0011011000011100F111CCCCCC111110. */ +{ "mpywhl", 0x361C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhl<.f> 0,b,limm 00110bbb00011100FBBB111110111110. */ +{ "mpywhl", 0x301C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,c 00110bbb11011100FBBB1111100QQQQQ. */ +{ "mpywhl", 0x30DC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhl<.f><.cc> b,b,limm 0011011011011100F111CCCCCC0QQQQQ. */ +{ "mpywhl", 0x36DC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhl<.f> a,limm,u6 0011011001011100F111uuuuuuAAAAAA. */ +{ "mpywhl", 0x365C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhl<.f> 0,limm,u6 0011011001011100F111uuuuuu111110. */ +{ "mpywhl", 0x365C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,u6 0011011011011100F111uuuuuu1QQQQQ. */ +{ "mpywhl", 0x36DC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhl<.f> 0,limm,s12 0011011010011100F111ssssssSSSSSS. */ +{ "mpywhl", 0x369C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhl<.f> a,limm,limm 0011011000011100F111111110AAAAAA. */ +{ "mpywhl", 0x361C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhl<.f> 0,limm,limm 0011011000011100F111111110111110. */ +{ "mpywhl", 0x361C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhl<.f><.cc> 0,limm,limm 0011011011011100F1111111100QQQQQ. */ +{ "mpywhl", 0x36DC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpywhul<.f> a,b,c 00110bbb00011110FBBBCCCCCCAAAAAA. */ +{ "mpywhul", 0x301E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mpywhul<.f> 0,b,c 00110bbb00011110FBBBCCCCCC111110. */ +{ "mpywhul", 0x301E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mpywhul<.f><.cc> b,b,c 00110bbb11011110FBBBCCCCCC0QQQQQ. */ +{ "mpywhul", 0x30DE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mpywhul<.f> a,b,u6 00110bbb01011110FBBBuuuuuuAAAAAA. */ +{ "mpywhul", 0x305E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhul<.f> 0,b,u6 00110bbb01011110FBBBuuuuuu111110. */ +{ "mpywhul", 0x305E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mpywhul<.f><.cc> b,b,u6 00110bbb11011110FBBBuuuuuu1QQQQQ. */ +{ "mpywhul", 0x30DE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhul<.f> b,b,s12 00110bbb10011110FBBBssssssSSSSSS. */ +{ "mpywhul", 0x309E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mpywhul<.f> a,limm,c 0011011000011110F111CCCCCCAAAAAA. */ +{ "mpywhul", 0x361E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mpywhul<.f> a,b,limm 00110bbb00011110FBBB111110AAAAAA. */ +{ "mpywhul", 0x301E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mpywhul<.f> 0,limm,c 0011011000011110F111CCCCCC111110. */ +{ "mpywhul", 0x361E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mpywhul<.f> 0,b,limm 00110bbb00011110FBBB111110111110. */ +{ "mpywhul", 0x301E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,c 00110bbb11011110FBBB1111100QQQQQ. */ +{ "mpywhul", 0x30DE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mpywhul<.f><.cc> b,b,limm 0011011011011110F111CCCCCC0QQQQQ. */ +{ "mpywhul", 0x36DE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mpywhul<.f> a,limm,u6 0011011001011110F111uuuuuuAAAAAA. */ +{ "mpywhul", 0x365E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhul<.f> 0,limm,u6 0011011001011110F111uuuuuu111110. */ +{ "mpywhul", 0x365E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,u6 0011011011011110F111uuuuuu1QQQQQ. */ +{ "mpywhul", 0x36DE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mpywhul<.f> 0,limm,s12 0011011010011110F111ssssssSSSSSS. */ +{ "mpywhul", 0x369E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mpywhul<.f> a,limm,limm 0011011000011110F111111110AAAAAA. */ +{ "mpywhul", 0x361E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhul<.f> 0,limm,limm 0011011000011110F111111110111110. */ +{ "mpywhul", 0x361E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mpywhul<.f><.cc> 0,limm,limm 0011011011011110F1111111100QQQQQ. */ +{ "mpywhul", 0x36DE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mpyw_s b,b,c 01111bbbccc01001. */ +{ "mpyw_s", 0x00007809, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY1E, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* mpy_s b,b,c 01111bbbccc01100. */ +{ "mpy_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* msubdf<.f> a,b,c 00110bbb00010101FBBBCCCCCCAAAAAA. */ +{ "msubdf", 0x30150000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* msubdf<.f> 0,b,c 00110bbb00010101FBBBCCCCCC111110. */ +{ "msubdf", 0x3015003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* msubdf<.f><.cc> b,b,c 00110bbb11010101FBBBCCCCCC0QQQQQ. */ +{ "msubdf", 0x30D50000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* msubdf<.f> a,b,u6 00110bbb01010101FBBBuuuuuuAAAAAA. */ +{ "msubdf", 0x30550000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* msubdf<.f> 0,b,u6 00110bbb01010101FBBBuuuuuu111110. */ +{ "msubdf", 0x3055003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* msubdf<.f><.cc> b,b,u6 00110bbb11010101FBBBuuuuuu1QQQQQ. */ +{ "msubdf", 0x30D50020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* msubdf<.f> b,b,s12 00110bbb10010101FBBBssssssSSSSSS. */ +{ "msubdf", 0x30950000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* msubdf<.f> a,limm,c 0011011000010101F111CCCCCCAAAAAA. */ +{ "msubdf", 0x36157000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* msubdf<.f> a,b,limm 00110bbb00010101FBBB111110AAAAAA. */ +{ "msubdf", 0x30150F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* msubdf<.f> 0,limm,c 0011011000010101F111CCCCCC111110. */ +{ "msubdf", 0x3615703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* msubdf<.f> 0,b,limm 00110bbb00010101FBBB111110111110. */ +{ "msubdf", 0x30150FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,c 00110bbb11010101FBBB1111100QQQQQ. */ +{ "msubdf", 0x30D50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* msubdf<.f><.cc> b,b,limm 0011011011010101F111CCCCCC0QQQQQ. */ +{ "msubdf", 0x36D57000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* msubdf<.f> a,limm,u6 0011011001010101F111uuuuuuAAAAAA. */ +{ "msubdf", 0x36557000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubdf<.f> 0,limm,u6 0011011001010101F111uuuuuu111110. */ +{ "msubdf", 0x3655703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,u6 0011011011010101F111uuuuuu1QQQQQ. */ +{ "msubdf", 0x36D57020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* msubdf<.f> 0,limm,s12 0011011010010101F111ssssssSSSSSS. */ +{ "msubdf", 0x36957000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* msubdf<.f> a,limm,limm 0011011000010101F111111110AAAAAA. */ +{ "msubdf", 0x36157F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* msubdf<.f> 0,limm,limm 0011011000010101F111111110111110. */ +{ "msubdf", 0x36157FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* msubdf<.f><.cc> 0,limm,limm 0011011011010101F1111111100QQQQQ. */ +{ "msubdf", 0x36D57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* msubdw<.f> a,b,c 00101bbb00010100FBBBCCCCCCAAAAAA. */ +{ "msubdw", 0x28140000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* msubdw<.f> 0,b,c 00101bbb00010100FBBBCCCCCC111110. */ +{ "msubdw", 0x2814003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* msubdw<.f><.cc> b,b,c 00101bbb11010100FBBBCCCCCC0QQQQQ. */ +{ "msubdw", 0x28D40000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* msubdw<.f> a,b,u6 00101bbb01010100FBBBuuuuuuAAAAAA. */ +{ "msubdw", 0x28540000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* msubdw<.f> 0,b,u6 00101bbb01010100FBBBuuuuuu111110. */ +{ "msubdw", 0x2854003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* msubdw<.f><.cc> b,b,u6 00101bbb11010100FBBBuuuuuu1QQQQQ. */ +{ "msubdw", 0x28D40020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* msubdw<.f> b,b,s12 00101bbb10010100FBBBssssssSSSSSS. */ +{ "msubdw", 0x28940000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* msubdw<.f> a,limm,c 0010111000010100F111CCCCCCAAAAAA. */ +{ "msubdw", 0x2E147000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* msubdw<.f> a,b,limm 00101bbb00010100FBBB111110AAAAAA. */ +{ "msubdw", 0x28140F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* msubdw<.f> 0,limm,c 0010111000010100F111CCCCCC111110. */ +{ "msubdw", 0x2E14703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* msubdw<.f> 0,b,limm 00101bbb00010100FBBB111110111110. */ +{ "msubdw", 0x28140FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,c 0010111011010100F111CCCCCC0QQQQQ. */ +{ "msubdw", 0x2ED47000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* msubdw<.f><.cc> b,b,limm 00101bbb11010100FBBB1111100QQQQQ. */ +{ "msubdw", 0x28D40F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* msubdw<.f> a,limm,u6 0010111001010100F111uuuuuuAAAAAA. */ +{ "msubdw", 0x2E547000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubdw<.f> 0,limm,u6 0010111001010100F111uuuuuu111110. */ +{ "msubdw", 0x2E54703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,u6 0010111011010100F111uuuuuu1QQQQQ. */ +{ "msubdw", 0x2ED47020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* msubdw<.f> 0,limm,s12 0010111010010100F111ssssssSSSSSS. */ +{ "msubdw", 0x2E947000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* msubdw<.f> a,limm,limm 0010111000010100F111111110AAAAAA. */ +{ "msubdw", 0x2E147F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* msubdw<.f> 0,limm,limm 0010111000010100F111111110111110. */ +{ "msubdw", 0x2E147FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* msubdw<.f><.cc> 0,limm,limm 0010111011010100F1111111100QQQQQ. */ +{ "msubdw", 0x2ED47F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* msubf<.f> a,b,c 00110bbb00001110FBBBCCCCCCAAAAAA. */ +{ "msubf", 0x300E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* msubf<.f> 0,b,c 00110bbb00001110FBBBCCCCCC111110. */ +{ "msubf", 0x300E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* msubf<.f><.cc> b,b,c 00110bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "msubf", 0x30CE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* msubf<.f> a,b,u6 00110bbb01001110FBBBuuuuuuAAAAAA. */ +{ "msubf", 0x304E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* msubf<.f> 0,b,u6 00110bbb01001110FBBBuuuuuu111110. */ +{ "msubf", 0x304E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* msubf<.f><.cc> b,b,u6 00110bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "msubf", 0x30CE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* msubf<.f> b,b,s12 00110bbb10001110FBBBssssssSSSSSS. */ +{ "msubf", 0x308E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* msubf<.f> a,limm,c 0011011000001110F111CCCCCCAAAAAA. */ +{ "msubf", 0x360E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* msubf<.f> a,b,limm 00110bbb00001110FBBB111110AAAAAA. */ +{ "msubf", 0x300E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* msubf<.f> 0,limm,c 0011011000001110F111CCCCCC111110. */ +{ "msubf", 0x360E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* msubf<.f> 0,b,limm 00110bbb00001110FBBB111110111110. */ +{ "msubf", 0x300E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,c 00110bbb11001110FBBB1111100QQQQQ. */ +{ "msubf", 0x30CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* msubf<.f><.cc> b,b,limm 0011011011001110F111CCCCCC0QQQQQ. */ +{ "msubf", 0x36CE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* msubf<.f> a,limm,u6 0011011001001110F111uuuuuuAAAAAA. */ +{ "msubf", 0x364E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubf<.f> 0,limm,u6 0011011001001110F111uuuuuu111110. */ +{ "msubf", 0x364E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,u6 0011011011001110F111uuuuuu1QQQQQ. */ +{ "msubf", 0x36CE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* msubf<.f> 0,limm,s12 0011011010001110F111ssssssSSSSSS. */ +{ "msubf", 0x368E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* msubf<.f> a,limm,limm 0011011000001110F111111110AAAAAA. */ +{ "msubf", 0x360E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* msubf<.f> 0,limm,limm 0011011000001110F111111110111110. */ +{ "msubf", 0x360E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* msubf<.f><.cc> 0,limm,limm 0011011011001110F1111111100QQQQQ. */ +{ "msubf", 0x36CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* msubfr<.f> a,b,c 00110bbb00001111FBBBCCCCCCAAAAAA. */ +{ "msubfr", 0x300F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* msubfr<.f> 0,b,c 00110bbb00001111FBBBCCCCCC111110. */ +{ "msubfr", 0x300F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* msubfr<.f><.cc> b,b,c 00110bbb11001111FBBBCCCCCC0QQQQQ. */ +{ "msubfr", 0x30CF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* msubfr<.f> a,b,u6 00110bbb01001111FBBBuuuuuuAAAAAA. */ +{ "msubfr", 0x304F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* msubfr<.f> 0,b,u6 00110bbb01001111FBBBuuuuuu111110. */ +{ "msubfr", 0x304F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* msubfr<.f><.cc> b,b,u6 00110bbb11001111FBBBuuuuuu1QQQQQ. */ +{ "msubfr", 0x30CF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* msubfr<.f> b,b,s12 00110bbb10001111FBBBssssssSSSSSS. */ +{ "msubfr", 0x308F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* msubfr<.f> a,limm,c 0011011000001111F111CCCCCCAAAAAA. */ +{ "msubfr", 0x360F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* msubfr<.f> a,b,limm 00110bbb00001111FBBB111110AAAAAA. */ +{ "msubfr", 0x300F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* msubfr<.f> 0,limm,c 0011011000001111F111CCCCCC111110. */ +{ "msubfr", 0x360F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* msubfr<.f> 0,b,limm 00110bbb00001111FBBB111110111110. */ +{ "msubfr", 0x300F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,c 00110bbb11001111FBBB1111100QQQQQ. */ +{ "msubfr", 0x30CF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* msubfr<.f><.cc> b,b,limm 0011011011001111F111CCCCCC0QQQQQ. */ +{ "msubfr", 0x36CF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* msubfr<.f> a,limm,u6 0011011001001111F111uuuuuuAAAAAA. */ +{ "msubfr", 0x364F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubfr<.f> 0,limm,u6 0011011001001111F111uuuuuu111110. */ +{ "msubfr", 0x364F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,u6 0011011011001111F111uuuuuu1QQQQQ. */ +{ "msubfr", 0x36CF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* msubfr<.f> 0,limm,s12 0011011010001111F111ssssssSSSSSS. */ +{ "msubfr", 0x368F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* msubfr<.f> a,limm,limm 0011011000001111F111111110AAAAAA. */ +{ "msubfr", 0x360F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* msubfr<.f> 0,limm,limm 0011011000001111F111111110111110. */ +{ "msubfr", 0x360F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* msubfr<.f><.cc> 0,limm,limm 0011011011001111F1111111100QQQQQ. */ +{ "msubfr", 0x36CF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* msubt<.f> a,b,c 00101bbb00100000FBBBCCCCCCAAAAAA. */ +{ "msubt", 0x28200000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* msubt<.f> 0,b,c 00101bbb00100000FBBBCCCCCC111110. */ +{ "msubt", 0x2820003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* msubt<.f><.cc> b,b,c 00101bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "msubt", 0x28E00000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* msubt<.f> a,b,u6 00101bbb01100000FBBBuuuuuuAAAAAA. */ +{ "msubt", 0x28600000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* msubt<.f> 0,b,u6 00101bbb01100000FBBBuuuuuu111110. */ +{ "msubt", 0x2860003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* msubt<.f><.cc> b,b,u6 00101bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "msubt", 0x28E00020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* msubt<.f> b,b,s12 00101bbb10100000FBBBssssssSSSSSS. */ +{ "msubt", 0x28A00000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* msubt<.f> a,limm,c 0010111000100000F111CCCCCCAAAAAA. */ +{ "msubt", 0x2E207000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* msubt<.f> a,b,limm 00101bbb00100000FBBB111110AAAAAA. */ +{ "msubt", 0x28200F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* msubt<.f> 0,limm,c 0010111000100000F111CCCCCC111110. */ +{ "msubt", 0x2E20703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* msubt<.f> 0,b,limm 00101bbb00100000FBBB111110111110. */ +{ "msubt", 0x28200FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,c 0010111011100000F111CCCCCC0QQQQQ. */ +{ "msubt", 0x2EE07000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* msubt<.f><.cc> b,b,limm 00101bbb11100000FBBB1111100QQQQQ. */ +{ "msubt", 0x28E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* msubt<.f> a,limm,u6 0010111001100000F111uuuuuuAAAAAA. */ +{ "msubt", 0x2E607000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubt<.f> 0,limm,u6 0010111001100000F111uuuuuu111110. */ +{ "msubt", 0x2E60703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,u6 0010111011100000F111uuuuuu1QQQQQ. */ +{ "msubt", 0x2EE07020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* msubt<.f> 0,limm,s12 0010111010100000F111ssssssSSSSSS. */ +{ "msubt", 0x2EA07000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* msubt<.f> a,limm,limm 0010111000100000F111111110AAAAAA. */ +{ "msubt", 0x2E207F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* msubt<.f> 0,limm,limm 0010111000100000F111111110111110. */ +{ "msubt", 0x2E207FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* msubt<.f><.cc> 0,limm,limm 0010111011100000F1111111100QQQQQ. */ +{ "msubt", 0x2EE07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ +{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { 0 }}, + +/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ +{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_CC }}, + +/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ +{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ +{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_CC }}, + +/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ +{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ +{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ +{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ +{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ +{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_CC }}, + +/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ +{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ +{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ +{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,limm 00101110000001000111111110111110. */ +{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ +{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* mul64 0,b,c 00101bbb000001000BBBCCCCCC111110. */ +{ "mul64", 0x2804003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { 0 }}, + +/* mul64<.cc> 0,b,c 00101bbb110001000BBBCCCCCC0QQQQQ. */ +{ "mul64", 0x28C40000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { C_CC }}, + +/* mul64 0,b,u6 00101bbb010001000BBBuuuuuu111110. */ +{ "mul64", 0x2844003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,b,u6 00101bbb110001000BBBuuuuuu1QQQQQ. */ +{ "mul64", 0x28C40020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* mul64 0,b,s12 00101bbb100001000BBBssssssSSSSSS. */ +{ "mul64", 0x28840000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,c 00101110000001000111CCCCCC111110. */ +{ "mul64", 0x2E04703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* mul64 0,b,limm 00101bbb000001000BBB111110111110. */ +{ "mul64", 0x28040FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* mul64<.cc> 0,limm,c 00101110110001000111CCCCCC0QQQQQ. */ +{ "mul64", 0x2EC47000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { C_CC }}, + +/* mul64<.cc> 0,b,limm 00101bbb110001000BBB1111100QQQQQ. */ +{ "mul64", 0x28C40F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { C_CC }}, + +/* mul64 0,limm,u6 00101110010001000111uuuuuu111110. */ +{ "mul64", 0x2E44703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* mul64<.cc> 0,limm,u6 00101110110001000111uuuuuu1QQQQQ. */ +{ "mul64", 0x2EC47020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* mul64 0,limm,s12 00101110100001000111ssssssSSSSSS. */ +{ "mul64", 0x2E847000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* mul64 0,limm,limm 00101110000001000111111110111110. */ +{ "mul64", 0x2E047FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* mul64<.cc> 0,limm,limm 001011101100010001111111100QQQQQ. */ +{ "mul64", 0x2EC47F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* mul64_s 0,b,c 01111bbbccc01100. */ +{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA_S, RB_S, RC_S }, { 0 }}, + +/* mul64_s 0,b,c 01111bbbccc01100. */ +{ "mul64_s", 0x0000780C, 0x0000F81F, ARC_OPCODE_ARC600, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* muldw<.f> a,b,c 00101bbb00001100FBBBCCCCCCAAAAAA. */ +{ "muldw", 0x280C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* muldw<.f> 0,b,c 00101bbb00001100FBBBCCCCCC111110. */ +{ "muldw", 0x280C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* muldw<.f><.cc> b,b,c 00101bbb11001100FBBBCCCCCC0QQQQQ. */ +{ "muldw", 0x28CC0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* muldw<.f> a,b,u6 00101bbb01001100FBBBuuuuuuAAAAAA. */ +{ "muldw", 0x284C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* muldw<.f> 0,b,u6 00101bbb01001100FBBBuuuuuu111110. */ +{ "muldw", 0x284C003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* muldw<.f><.cc> b,b,u6 00101bbb11001100FBBBuuuuuu1QQQQQ. */ +{ "muldw", 0x28CC0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* muldw<.f> b,b,s12 00101bbb10001100FBBBssssssSSSSSS. */ +{ "muldw", 0x288C0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* muldw<.f> a,limm,c 0010111000001100F111CCCCCCAAAAAA. */ +{ "muldw", 0x2E0C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* muldw<.f> a,b,limm 00101bbb00001100FBBB111110AAAAAA. */ +{ "muldw", 0x280C0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* muldw<.f> 0,limm,c 0010111000001100F111CCCCCC111110. */ +{ "muldw", 0x2E0C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* muldw<.f> 0,b,limm 00101bbb00001100FBBB111110111110. */ +{ "muldw", 0x280C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,c 0010111011001100F111CCCCCC0QQQQQ. */ +{ "muldw", 0x2ECC7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* muldw<.f><.cc> b,b,limm 00101bbb11001100FBBB1111100QQQQQ. */ +{ "muldw", 0x28CC0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* muldw<.f> a,limm,u6 0010111001001100F111uuuuuuAAAAAA. */ +{ "muldw", 0x2E4C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* muldw<.f> 0,limm,u6 0010111001001100F111uuuuuu111110. */ +{ "muldw", 0x2E4C703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,u6 0010111011001100F111uuuuuu1QQQQQ. */ +{ "muldw", 0x2ECC7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* muldw<.f> 0,limm,s12 0010111010001100F111ssssssSSSSSS. */ +{ "muldw", 0x2E8C7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* muldw<.f> a,limm,limm 0010111000001100F111111110AAAAAA. */ +{ "muldw", 0x2E0C7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* muldw<.f> 0,limm,limm 0010111000001100F111111110111110. */ +{ "muldw", 0x2E0C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* muldw<.f><.cc> 0,limm,limm 0010111011001100F1111111100QQQQQ. */ +{ "muldw", 0x2ECC7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulflw<.f> a,b,c 00101bbb00110010FBBBCCCCCCAAAAAA. */ +{ "mulflw", 0x28320000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulflw<.f> 0,b,c 00101bbb00110010FBBBCCCCCC111110. */ +{ "mulflw", 0x2832003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulflw<.f><.cc> b,b,c 00101bbb11110010FBBBCCCCCC0QQQQQ. */ +{ "mulflw", 0x28F20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulflw<.f> a,b,u6 00101bbb01110010FBBBuuuuuuAAAAAA. */ +{ "mulflw", 0x28720000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulflw<.f> 0,b,u6 00101bbb01110010FBBBuuuuuu111110. */ +{ "mulflw", 0x2872003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulflw<.f><.cc> b,b,u6 00101bbb11110010FBBBuuuuuu1QQQQQ. */ +{ "mulflw", 0x28F20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulflw<.f> b,b,s12 00101bbb10110010FBBBssssssSSSSSS. */ +{ "mulflw", 0x28B20000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulflw<.f> a,limm,c 0010111000110010F111CCCCCCAAAAAA. */ +{ "mulflw", 0x2E327000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulflw<.f> a,b,limm 00101bbb00110010FBBB111110AAAAAA. */ +{ "mulflw", 0x28320F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulflw<.f> 0,limm,c 0010111000110010F111CCCCCC111110. */ +{ "mulflw", 0x2E32703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulflw<.f> 0,b,limm 00101bbb00110010FBBB111110111110. */ +{ "mulflw", 0x28320FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,c 0010111011110010F111CCCCCC0QQQQQ. */ +{ "mulflw", 0x2EF27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulflw<.f><.cc> b,b,limm 00101bbb11110010FBBB1111100QQQQQ. */ +{ "mulflw", 0x28F20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulflw<.f> a,limm,u6 0010111001110010F111uuuuuuAAAAAA. */ +{ "mulflw", 0x2E727000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulflw<.f> 0,limm,u6 0010111001110010F111uuuuuu111110. */ +{ "mulflw", 0x2E72703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,u6 0010111011110010F111uuuuuu1QQQQQ. */ +{ "mulflw", 0x2EF27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulflw<.f> 0,limm,s12 0010111010110010F111ssssssSSSSSS. */ +{ "mulflw", 0x2EB27000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulflw<.f> a,limm,limm 0010111000110010F111111110AAAAAA. */ +{ "mulflw", 0x2E327F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulflw<.f> 0,limm,limm 0010111000110010F111111110111110. */ +{ "mulflw", 0x2E327FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulflw<.f><.cc> 0,limm,limm 0010111011110010F1111111100QQQQQ. */ +{ "mulflw", 0x2EF27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulhflw<.f> a,b,c 00101bbb00111001FBBBCCCCCCAAAAAA. */ +{ "mulhflw", 0x28390000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulhflw<.f> 0,b,c 00101bbb00111001FBBBCCCCCC111110. */ +{ "mulhflw", 0x2839003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulhflw<.f><.cc> b,b,c 00101bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "mulhflw", 0x28F90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulhflw<.f> a,b,u6 00101bbb01111001FBBBuuuuuuAAAAAA. */ +{ "mulhflw", 0x28790000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulhflw<.f> 0,b,u6 00101bbb01111001FBBBuuuuuu111110. */ +{ "mulhflw", 0x2879003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulhflw<.f><.cc> b,b,u6 00101bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "mulhflw", 0x28F90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulhflw<.f> b,b,s12 00101bbb10111001FBBBssssssSSSSSS. */ +{ "mulhflw", 0x28B90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulhflw<.f> a,limm,c 0010111000111001F111CCCCCCAAAAAA. */ +{ "mulhflw", 0x2E397000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulhflw<.f> a,b,limm 00101bbb00111001FBBB111110AAAAAA. */ +{ "mulhflw", 0x28390F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulhflw<.f> 0,limm,c 0010111000111001F111CCCCCC111110. */ +{ "mulhflw", 0x2E39703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulhflw<.f> 0,b,limm 00101bbb00111001FBBB111110111110. */ +{ "mulhflw", 0x28390FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,c 0010111011111001F111CCCCCC0QQQQQ. */ +{ "mulhflw", 0x2EF97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulhflw<.f><.cc> b,b,limm 00101bbb11111001FBBB1111100QQQQQ. */ +{ "mulhflw", 0x28F90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulhflw<.f> a,limm,u6 0010111001111001F111uuuuuuAAAAAA. */ +{ "mulhflw", 0x2E797000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulhflw<.f> 0,limm,u6 0010111001111001F111uuuuuu111110. */ +{ "mulhflw", 0x2E79703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,u6 0010111011111001F111uuuuuu1QQQQQ. */ +{ "mulhflw", 0x2EF97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulhflw<.f> 0,limm,s12 0010111010111001F111ssssssSSSSSS. */ +{ "mulhflw", 0x2EB97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulhflw<.f> a,limm,limm 0010111000111001F111111110AAAAAA. */ +{ "mulhflw", 0x2E397F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulhflw<.f> 0,limm,limm 0010111000111001F111111110111110. */ +{ "mulhflw", 0x2E397FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulhflw<.f><.cc> 0,limm,limm 0010111011111001F1111111100QQQQQ. */ +{ "mulhflw", 0x2EF97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulhlw<.f> a,b,c 00101bbb00111000FBBBCCCCCCAAAAAA. */ +{ "mulhlw", 0x28380000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulhlw<.f> 0,b,c 00101bbb00111000FBBBCCCCCC111110. */ +{ "mulhlw", 0x2838003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulhlw<.f><.cc> b,b,c 00101bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "mulhlw", 0x28F80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulhlw<.f> a,b,u6 00101bbb01111000FBBBuuuuuuAAAAAA. */ +{ "mulhlw", 0x28780000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulhlw<.f> 0,b,u6 00101bbb01111000FBBBuuuuuu111110. */ +{ "mulhlw", 0x2878003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulhlw<.f><.cc> b,b,u6 00101bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "mulhlw", 0x28F80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulhlw<.f> b,b,s12 00101bbb10111000FBBBssssssSSSSSS. */ +{ "mulhlw", 0x28B80000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulhlw<.f> a,limm,c 0010111000111000F111CCCCCCAAAAAA. */ +{ "mulhlw", 0x2E387000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulhlw<.f> a,b,limm 00101bbb00111000FBBB111110AAAAAA. */ +{ "mulhlw", 0x28380F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulhlw<.f> 0,limm,c 0010111000111000F111CCCCCC111110. */ +{ "mulhlw", 0x2E38703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulhlw<.f> 0,b,limm 00101bbb00111000FBBB111110111110. */ +{ "mulhlw", 0x28380FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,c 0010111011111000F111CCCCCC0QQQQQ. */ +{ "mulhlw", 0x2EF87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulhlw<.f><.cc> b,b,limm 00101bbb11111000FBBB1111100QQQQQ. */ +{ "mulhlw", 0x28F80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulhlw<.f> a,limm,u6 0010111001111000F111uuuuuuAAAAAA. */ +{ "mulhlw", 0x2E787000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulhlw<.f> 0,limm,u6 0010111001111000F111uuuuuu111110. */ +{ "mulhlw", 0x2E78703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,u6 0010111011111000F111uuuuuu1QQQQQ. */ +{ "mulhlw", 0x2EF87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulhlw<.f> 0,limm,s12 0010111010111000F111ssssssSSSSSS. */ +{ "mulhlw", 0x2EB87000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulhlw<.f> a,limm,limm 0010111000111000F111111110AAAAAA. */ +{ "mulhlw", 0x2E387F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulhlw<.f> 0,limm,limm 0010111000111000F111111110111110. */ +{ "mulhlw", 0x2E387FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulhlw<.f><.cc> 0,limm,limm 0010111011111000F1111111100QQQQQ. */ +{ "mulhlw", 0x2EF87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mullw<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ +{ "mullw", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mullw<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ +{ "mullw", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mullw<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "mullw", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mullw<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ +{ "mullw", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mullw<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ +{ "mullw", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mullw<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "mullw", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mullw<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ +{ "mullw", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mullw<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ +{ "mullw", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mullw<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ +{ "mullw", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mullw<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ +{ "mullw", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mullw<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ +{ "mullw", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ +{ "mullw", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mullw<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ +{ "mullw", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mullw<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ +{ "mullw", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mullw<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ +{ "mullw", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ +{ "mullw", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mullw<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ +{ "mullw", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mullw<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ +{ "mullw", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mullw<.f> 0,limm,limm 0010111000110001F111111110111110. */ +{ "mullw", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mullw<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ +{ "mullw", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulrdw<.f> a,b,c 00101bbb00001110FBBBCCCCCCAAAAAA. */ +{ "mulrdw", 0x280E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulrdw<.f> 0,b,c 00101bbb00001110FBBBCCCCCC111110. */ +{ "mulrdw", 0x280E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulrdw<.f><.cc> b,b,c 00101bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "mulrdw", 0x28CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulrdw<.f> a,b,u6 00101bbb01001110FBBBuuuuuuAAAAAA. */ +{ "mulrdw", 0x284E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulrdw<.f> 0,b,u6 00101bbb01001110FBBBuuuuuu111110. */ +{ "mulrdw", 0x284E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulrdw<.f><.cc> b,b,u6 00101bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "mulrdw", 0x28CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulrdw<.f> b,b,s12 00101bbb10001110FBBBssssssSSSSSS. */ +{ "mulrdw", 0x288E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulrdw<.f> a,limm,c 0010111000001110F111CCCCCCAAAAAA. */ +{ "mulrdw", 0x2E0E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulrdw<.f> a,b,limm 00101bbb00001110FBBB111110AAAAAA. */ +{ "mulrdw", 0x280E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulrdw<.f> 0,limm,c 0010111000001110F111CCCCCC111110. */ +{ "mulrdw", 0x2E0E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulrdw<.f> 0,b,limm 00101bbb00001110FBBB111110111110. */ +{ "mulrdw", 0x280E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,c 0010111011001110F111CCCCCC0QQQQQ. */ +{ "mulrdw", 0x2ECE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulrdw<.f><.cc> b,b,limm 00101bbb11001110FBBB1111100QQQQQ. */ +{ "mulrdw", 0x28CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulrdw<.f> a,limm,u6 0010111001001110F111uuuuuuAAAAAA. */ +{ "mulrdw", 0x2E4E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulrdw<.f> 0,limm,u6 0010111001001110F111uuuuuu111110. */ +{ "mulrdw", 0x2E4E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,u6 0010111011001110F111uuuuuu1QQQQQ. */ +{ "mulrdw", 0x2ECE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulrdw<.f> 0,limm,s12 0010111010001110F111ssssssSSSSSS. */ +{ "mulrdw", 0x2E8E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulrdw<.f> a,limm,limm 0010111000001110F111111110AAAAAA. */ +{ "mulrdw", 0x2E0E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulrdw<.f> 0,limm,limm 0010111000001110F111111110111110. */ +{ "mulrdw", 0x2E0E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulrdw<.f><.cc> 0,limm,limm 0010111011001110F1111111100QQQQQ. */ +{ "mulrdw", 0x2ECE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulrt<.f> a,b,c 00101bbb00011010FBBBCCCCCCAAAAAA. */ +{ "mulrt", 0x281A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulrt<.f> 0,b,c 00101bbb00011010FBBBCCCCCC111110. */ +{ "mulrt", 0x281A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulrt<.f><.cc> b,b,c 00101bbb11011010FBBBCCCCCC0QQQQQ. */ +{ "mulrt", 0x28DA0000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulrt<.f> a,b,u6 00101bbb01011010FBBBuuuuuuAAAAAA. */ +{ "mulrt", 0x285A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulrt<.f> 0,b,u6 00101bbb01011010FBBBuuuuuu111110. */ +{ "mulrt", 0x285A003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulrt<.f><.cc> b,b,u6 00101bbb11011010FBBBuuuuuu1QQQQQ. */ +{ "mulrt", 0x28DA0020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulrt<.f> b,b,s12 00101bbb10011010FBBBssssssSSSSSS. */ +{ "mulrt", 0x289A0000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulrt<.f> a,limm,c 0010111000011010F111CCCCCCAAAAAA. */ +{ "mulrt", 0x2E1A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulrt<.f> a,b,limm 00101bbb00011010FBBB111110AAAAAA. */ +{ "mulrt", 0x281A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulrt<.f> 0,limm,c 0010111000011010F111CCCCCC111110. */ +{ "mulrt", 0x2E1A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulrt<.f> 0,b,limm 00101bbb00011010FBBB111110111110. */ +{ "mulrt", 0x281A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,c 0010111011011010F111CCCCCC0QQQQQ. */ +{ "mulrt", 0x2EDA7000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulrt<.f><.cc> b,b,limm 00101bbb11011010FBBB1111100QQQQQ. */ +{ "mulrt", 0x28DA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulrt<.f> a,limm,u6 0010111001011010F111uuuuuuAAAAAA. */ +{ "mulrt", 0x2E5A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulrt<.f> 0,limm,u6 0010111001011010F111uuuuuu111110. */ +{ "mulrt", 0x2E5A703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,u6 0010111011011010F111uuuuuu1QQQQQ. */ +{ "mulrt", 0x2EDA7020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulrt<.f> 0,limm,s12 0010111010011010F111ssssssSSSSSS. */ +{ "mulrt", 0x2E9A7000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulrt<.f> a,limm,limm 0010111000011010F111111110AAAAAA. */ +{ "mulrt", 0x2E1A7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulrt<.f> 0,limm,limm 0010111000011010F111111110111110. */ +{ "mulrt", 0x2E1A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulrt<.f><.cc> 0,limm,limm 0010111011011010F1111111100QQQQQ. */ +{ "mulrt", 0x2EDA7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mult<.f> a,b,c 00101bbb00011000FBBBCCCCCCAAAAAA. */ +{ "mult", 0x28180000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mult<.f> 0,b,c 00101bbb00011000FBBBCCCCCC111110. */ +{ "mult", 0x2818003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mult<.f><.cc> b,b,c 00101bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "mult", 0x28D80000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mult<.f> a,b,u6 00101bbb01011000FBBBuuuuuuAAAAAA. */ +{ "mult", 0x28580000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mult<.f> 0,b,u6 00101bbb01011000FBBBuuuuuu111110. */ +{ "mult", 0x2858003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mult<.f><.cc> b,b,u6 00101bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "mult", 0x28D80020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mult<.f> b,b,s12 00101bbb10011000FBBBssssssSSSSSS. */ +{ "mult", 0x28980000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mult<.f> a,limm,c 0010111000011000F111CCCCCCAAAAAA. */ +{ "mult", 0x2E187000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mult<.f> a,b,limm 00101bbb00011000FBBB111110AAAAAA. */ +{ "mult", 0x28180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mult<.f> 0,limm,c 0010111000011000F111CCCCCC111110. */ +{ "mult", 0x2E18703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mult<.f> 0,b,limm 00101bbb00011000FBBB111110111110. */ +{ "mult", 0x28180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mult<.f><.cc> 0,limm,c 0010111011011000F111CCCCCC0QQQQQ. */ +{ "mult", 0x2ED87000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mult<.f><.cc> b,b,limm 00101bbb11011000FBBB1111100QQQQQ. */ +{ "mult", 0x28D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mult<.f> a,limm,u6 0010111001011000F111uuuuuuAAAAAA. */ +{ "mult", 0x2E587000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mult<.f> 0,limm,u6 0010111001011000F111uuuuuu111110. */ +{ "mult", 0x2E58703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mult<.f><.cc> 0,limm,u6 0010111011011000F111uuuuuu1QQQQQ. */ +{ "mult", 0x2ED87020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mult<.f> 0,limm,s12 0010111010011000F111ssssssSSSSSS. */ +{ "mult", 0x2E987000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mult<.f> a,limm,limm 0010111000011000F111111110AAAAAA. */ +{ "mult", 0x2E187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mult<.f> 0,limm,limm 0010111000011000F111111110111110. */ +{ "mult", 0x2E187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mult<.f><.cc> 0,limm,limm 0010111011011000F1111111100QQQQQ. */ +{ "mult", 0x2ED87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ +{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { 0 }}, + +/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ +{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, RC }, { C_CC }}, + +/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ +{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ +{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_CC }}, + +/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ +{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ +{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ +{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ +{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ +{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, RB, LIMM }, { C_CC }}, + +/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ +{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ +{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ +{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,limm 00101110000001010111111110111110. */ +{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ +{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* mulu64 0,b,c 00101bbb000001010BBBCCCCCC111110. */ +{ "mulu64", 0x2805003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { 0 }}, + +/* mulu64<.cc> 0,b,c 00101bbb110001010BBBCCCCCC0QQQQQ. */ +{ "mulu64", 0x28C50000, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, RC }, { C_CC }}, + +/* mulu64 0,b,u6 00101bbb010001010BBBuuuuuu111110. */ +{ "mulu64", 0x2845003E, 0xF8FF803F, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,b,u6 00101bbb110001010BBBuuuuuu1QQQQQ. */ +{ "mulu64", 0x28C50020, 0xF8FF8020, ARC_OPCODE_ARC600, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* mulu64 0,b,s12 00101bbb100001010BBBssssssSSSSSS. */ +{ "mulu64", 0x28850000, 0xF8FF8000, ARC_OPCODE_ARC600, ARITH, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,c 00101110000001010111CCCCCC111110. */ +{ "mulu64", 0x2E05703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* mulu64 0,b,limm 00101bbb000001010BBB111110111110. */ +{ "mulu64", 0x28050FBE, 0xF8FF8FFF, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* mulu64<.cc> 0,limm,c 00101110110001010111CCCCCC0QQQQQ. */ +{ "mulu64", 0x2EC57000, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, RC }, { C_CC }}, + +/* mulu64<.cc> 0,b,limm 00101bbb110001010BBB1111100QQQQQ. */ +{ "mulu64", 0x28C50F80, 0xF8FF8FE0, ARC_OPCODE_ARC600, ARITH, NONE, { RB, LIMM }, { C_CC }}, + +/* mulu64 0,limm,u6 00101110010001010111uuuuuu111110. */ +{ "mulu64", 0x2E45703E, 0xFFFFF03F, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* mulu64<.cc> 0,limm,u6 00101110110001010111uuuuuu1QQQQQ. */ +{ "mulu64", 0x2EC57020, 0xFFFFF020, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* mulu64 0,limm,s12 00101110100001010111ssssssSSSSSS. */ +{ "mulu64", 0x2E857000, 0xFFFFF000, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* mulu64 0,limm,limm 00101110000001010111111110111110. */ +{ "mulu64", 0x2E057FBE, 0xFFFFFFFF, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* mulu64<.cc> 0,limm,limm 001011101100010101111111100QQQQQ. */ +{ "mulu64", 0x2EC57F80, 0xFFFFFFE0, ARC_OPCODE_ARC600, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* muludw<.f> a,b,c 00101bbb00001101FBBBCCCCCCAAAAAA. */ +{ "muludw", 0x280D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* muludw<.f> 0,b,c 00101bbb00001101FBBBCCCCCC111110. */ +{ "muludw", 0x280D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* muludw<.f><.cc> b,b,c 00101bbb11001101FBBBCCCCCC0QQQQQ. */ +{ "muludw", 0x28CD0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* muludw<.f> a,b,u6 00101bbb01001101FBBBuuuuuuAAAAAA. */ +{ "muludw", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* muludw<.f> 0,b,u6 00101bbb01001101FBBBuuuuuu111110. */ +{ "muludw", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* muludw<.f><.cc> b,b,u6 00101bbb11001101FBBBuuuuuu1QQQQQ. */ +{ "muludw", 0x28CD0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* muludw<.f> b,b,s12 00101bbb10001101FBBBssssssSSSSSS. */ +{ "muludw", 0x288D0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* muludw<.f> a,limm,c 0010111000001101F111CCCCCCAAAAAA. */ +{ "muludw", 0x2E0D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* muludw<.f> a,b,limm 00101bbb00001101FBBB111110AAAAAA. */ +{ "muludw", 0x280D0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* muludw<.f> 0,limm,c 0010111000001101F111CCCCCC111110. */ +{ "muludw", 0x2E0D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* muludw<.f> 0,b,limm 00101bbb00001101FBBB111110111110. */ +{ "muludw", 0x280D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,c 0010111011001101F111CCCCCC0QQQQQ. */ +{ "muludw", 0x2ECD7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* muludw<.f><.cc> b,b,limm 00101bbb11001101FBBB1111100QQQQQ. */ +{ "muludw", 0x28CD0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* muludw<.f> a,limm,u6 0010111001001101F111uuuuuuAAAAAA. */ +{ "muludw", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* muludw<.f> 0,limm,u6 0010111001001101F111uuuuuu111110. */ +{ "muludw", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,u6 0010111011001101F111uuuuuu1QQQQQ. */ +{ "muludw", 0x2ECD7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* muludw<.f> 0,limm,s12 0010111010001101F111ssssssSSSSSS. */ +{ "muludw", 0x2E8D7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* muludw<.f> a,limm,limm 0010111000001101F111111110AAAAAA. */ +{ "muludw", 0x2E0D7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* muludw<.f> 0,limm,limm 0010111000001101F111111110111110. */ +{ "muludw", 0x2E0D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* muludw<.f><.cc> 0,limm,limm 0010111011001101F1111111100QQQQQ. */ +{ "muludw", 0x2ECD7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mululw<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ +{ "mululw", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mululw<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ +{ "mululw", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mululw<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "mululw", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mululw<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ +{ "mululw", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mululw<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ +{ "mululw", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mululw<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "mululw", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mululw<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ +{ "mululw", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mululw<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ +{ "mululw", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mululw<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ +{ "mululw", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mululw<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ +{ "mululw", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mululw<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ +{ "mululw", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ +{ "mululw", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mululw<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ +{ "mululw", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mululw<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ +{ "mululw", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mululw<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ +{ "mululw", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ +{ "mululw", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mululw<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ +{ "mululw", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mululw<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ +{ "mululw", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mululw<.f> 0,limm,limm 0010111000110000F111111110111110. */ +{ "mululw", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mululw<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ +{ "mululw", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* mulut<.f> a,b,c 00101bbb00011001FBBBCCCCCCAAAAAA. */ +{ "mulut", 0x28190000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, RC }, { C_F }}, + +/* mulut<.f> 0,b,c 00101bbb00011001FBBBCCCCCC111110. */ +{ "mulut", 0x2819003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, RC }, { C_F }}, + +/* mulut<.f><.cc> b,b,c 00101bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "mulut", 0x28D90000, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* mulut<.f> a,b,u6 00101bbb01011001FBBBuuuuuuAAAAAA. */ +{ "mulut", 0x28590000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* mulut<.f> 0,b,u6 00101bbb01011001FBBBuuuuuu111110. */ +{ "mulut", 0x2859003E, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* mulut<.f><.cc> b,b,u6 00101bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "mulut", 0x28D90020, 0xF8FF0020, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* mulut<.f> b,b,s12 00101bbb10011001FBBBssssssSSSSSS. */ +{ "mulut", 0x28990000, 0xF8FF0000, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* mulut<.f> a,limm,c 0010111000011001F111CCCCCCAAAAAA. */ +{ "mulut", 0x2E197000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, RC }, { C_F }}, + +/* mulut<.f> a,b,limm 00101bbb00011001FBBB111110AAAAAA. */ +{ "mulut", 0x28190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, RB, LIMM }, { C_F }}, + +/* mulut<.f> 0,limm,c 0010111000011001F111CCCCCC111110. */ +{ "mulut", 0x2E19703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* mulut<.f> 0,b,limm 00101bbb00011001FBBB111110111110. */ +{ "mulut", 0x28190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,c 0010111011011001F111CCCCCC0QQQQQ. */ +{ "mulut", 0x2ED97000, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* mulut<.f><.cc> b,b,limm 00101bbb11011001FBBB1111100QQQQQ. */ +{ "mulut", 0x28D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600, DSP, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* mulut<.f> a,limm,u6 0010111001011001F111uuuuuuAAAAAA. */ +{ "mulut", 0x2E597000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulut<.f> 0,limm,u6 0010111001011001F111uuuuuu111110. */ +{ "mulut", 0x2E59703E, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,u6 0010111011011001F111uuuuuu1QQQQQ. */ +{ "mulut", 0x2ED97020, 0xFFFF7020, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* mulut<.f> 0,limm,s12 0010111010011001F111ssssssSSSSSS. */ +{ "mulut", 0x2E997000, 0xFFFF7000, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* mulut<.f> a,limm,limm 0010111000011001F111111110AAAAAA. */ +{ "mulut", 0x2E197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600, DSP, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* mulut<.f> 0,limm,limm 0010111000011001F111111110111110. */ +{ "mulut", 0x2E197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* mulut<.f><.cc> 0,limm,limm 0010111011011001F1111111100QQQQQ. */ +{ "mulut", 0x2ED97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */ +{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB }, { C_F }}, + +/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */ +{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup }, { C_F, C_CC }}, + +/* neg<.f> a,limm 0010011001001110F111000000AAAAAA. */ +{ "neg", 0x264E7000, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM }, { C_F }}, + +/* neg<.f><.cc> 0,limm 0010011011001110F1110000001QQQQQ. */ +{ "neg", 0x26CE7020, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F, C_CC }}, + +/* negs<.f> b,c 00101bbb00101111FBBBCCCCCC000111. */ +{ "negs", 0x282F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { C_F }}, + +/* negs<.f> 0,c 0010111000101111F111CCCCCC000111. */ +{ "negs", 0x2E2F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* negs<.f> b,u6 00101bbb01101111FBBBuuuuuu000111. */ +{ "negs", 0x286F0007, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* negs<.f> 0,u6 0010111001101111F111uuuuuu000111. */ +{ "negs", 0x2E6F7007, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* negs<.f> b,limm 00101bbb00101111FBBB111110000111. */ +{ "negs", 0x282F0F87, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* negs<.f> 0,limm 0010111000101111F111111110000111. */ +{ "negs", 0x2E2F7F87, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* negsh<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ +{ "negsh", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }}, + +/* negsh<.f> 0,c 0010111000101111F111CCCCCC000110. */ +{ "negsh", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }}, + +/* negsh<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ +{ "negsh", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* negsh<.f> 0,u6 0010111001101111F111uuuuuu000110. */ +{ "negsh", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* negsh<.f> b,limm 00101bbb00101111FBBB111110000110. */ +{ "negsh", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* negsh<.f> 0,limm 0010111000101111F111111110000110. */ +{ "negsh", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* negsw<.f> b,c 00101bbb00101111FBBBCCCCCC000110. */ +{ "negsw", 0x282F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* negsw<.f> 0,c 0010111000101111F111CCCCCC000110. */ +{ "negsw", 0x2E2F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* negsw<.f> b,u6 00101bbb01101111FBBBuuuuuu000110. */ +{ "negsw", 0x286F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* negsw<.f> 0,u6 0010111001101111F111uuuuuu000110. */ +{ "negsw", 0x2E6F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* negsw<.f> b,limm 00101bbb00101111FBBB111110000110. */ +{ "negsw", 0x282F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* negsw<.f> 0,limm 0010111000101111F111111110000110. */ +{ "negsw", 0x2E2F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* neg_s b,c 01111bbbccc10011. */ +{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* nop 00100110010010100111000000000000. */ +{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }}, + +/* nop_s 0111100011100000. */ +{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }}, + +/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */ +{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }}, + +/* norm<.f> 0,c 0010111000101111F111CCCCCC000001. */ +{ "norm", 0x2E2F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }}, + +/* norm<.f> b,u6 00101bbb01101111FBBBuuuuuu000001. */ +{ "norm", 0x286F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }}, + +/* norm<.f> 0,u6 0010111001101111F111uuuuuu000001. */ +{ "norm", 0x2E6F7001, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }}, + +/* norm<.f> b,limm 00101bbb00101111FBBB111110000001. */ +{ "norm", 0x282F0F81, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }}, + +/* norm<.f> 0,limm 0010111000101111F111111110000001. */ +{ "norm", 0x2E2F7F81, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }}, + +/* normacc b,c 00101bbb001011110BBBCCCCCC011001. */ +{ "normacc", 0x282F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* normacc 0,c 00101110001011110111CCCCCC011001. */ +{ "normacc", 0x2E2F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* normacc b,u6 00101bbb011011110BBBuuuuuu011001. */ +{ "normacc", 0x286F0019, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* normacc 0,u6 00101110011011110111uuuuuu011001. */ +{ "normacc", 0x2E6F7019, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* normacc b,limm 00101bbb001011110BBB111110011001. */ +{ "normacc", 0x282F0F99, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* normacc 0,limm 00101110001011110111111110011001. */ +{ "normacc", 0x2E2F7F99, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* normh<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ +{ "normh", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }}, + +/* normh<.f> 0,c 0010111000101111F111CCCCCC001000. */ +{ "normh", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, RC }, { C_F }}, + +/* normh<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ +{ "normh", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }}, + +/* normh<.f> 0,u6 0010111001101111F111uuuuuu001000. */ +{ "normh", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }}, + +/* normh<.f> b,limm 00101bbb00101111FBBB111110001000. */ +{ "normh", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, LIMM }, { C_F }}, + +/* normh<.f> 0,limm 0010111000101111F111111110001000. */ +{ "normh", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { ZA, LIMM }, { C_F }}, + +/* normw<.f> b,c 00101bbb00101111FBBBCCCCCC001000. */ +{ "normw", 0x282F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, RC }, { C_F }}, + +/* normw<.f> 0,c 0010111000101111F111CCCCCC001000. */ +{ "normw", 0x2E2F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, RC }, { C_F }}, + +/* normw<.f> b,u6 00101bbb01101111FBBBuuuuuu001000. */ +{ "normw", 0x286F0008, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, UIMM6_20 }, { C_F }}, + +/* normw<.f> 0,u6 0010111001101111F111uuuuuu001000. */ +{ "normw", 0x2E6F7008, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, UIMM6_20 }, { C_F }}, + +/* normw<.f> b,limm 00101bbb00101111FBBB111110001000. */ +{ "normw", 0x282F0F88, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { RB, LIMM }, { C_F }}, + +/* normw<.f> 0,limm 0010111000101111F111111110001000. */ +{ "normw", 0x2E2F7F88, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, BTSCN, { ZA, LIMM }, { C_F }}, + +/* not<.f> b,c 00100bbb00101111FBBBCCCCCC001010. */ +{ "not", 0x202F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* not<.f> 0,c 0010011000101111F111CCCCCC001010. */ +{ "not", 0x262F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* not<.f> b,u6 00100bbb01101111FBBBuuuuuu001010. */ +{ "not", 0x206F000A, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* not<.f> 0,u6 0010011001101111F111uuuuuu001010. */ +{ "not", 0x266F700A, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* not<.f> b,limm 00100bbb00101111FBBB111110001010. */ +{ "not", 0x202F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* not<.f> 0,limm 0010011000101111F111111110001010. */ +{ "not", 0x262F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* not_s b,c 01111bbbccc10010. */ +{ "not_s", 0x00007812, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }}, + +/* or<.f> a,b,c 00100bbb00000101FBBBCCCCCCAAAAAA. */ +{ "or", 0x20050000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* or<.f> 0,b,c 00100bbb00000101FBBBCCCCCC111110. */ +{ "or", 0x2005003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* or<.f><.cc> b,b,c 00100bbb11000101FBBBCCCCCC0QQQQQ. */ +{ "or", 0x20C50000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* or<.f> a,b,u6 00100bbb01000101FBBBuuuuuuAAAAAA. */ +{ "or", 0x20450000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* or<.f> 0,b,u6 00100bbb01000101FBBBuuuuuu111110. */ +{ "or", 0x2045003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* or<.f><.cc> b,b,u6 00100bbb11000101FBBBuuuuuu1QQQQQ. */ +{ "or", 0x20C50020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* or<.f> b,b,s12 00100bbb10000101FBBBssssssSSSSSS. */ +{ "or", 0x20850000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* or<.f> a,limm,c 0010011000000101F111CCCCCCAAAAAA. */ +{ "or", 0x26057000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* or<.f> a,b,limm 00100bbb00000101FBBB111110AAAAAA. */ +{ "or", 0x20050F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* or<.f> 0,limm,c 0010011000000101F111CCCCCC111110. */ +{ "or", 0x2605703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* or<.f> 0,b,limm 00100bbb00000101FBBB111110111110. */ +{ "or", 0x20050FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* or<.f><.cc> b,b,limm 00100bbb11000101FBBB1111100QQQQQ. */ +{ "or", 0x20C50F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* or<.f><.cc> 0,limm,c 0010011011000101F111CCCCCC0QQQQQ. */ +{ "or", 0x26C57000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* or<.f> a,limm,u6 0010011001000101F111uuuuuuAAAAAA. */ +{ "or", 0x26457000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* or<.f> 0,limm,u6 0010011001000101F111uuuuuu111110. */ +{ "or", 0x2645703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* or<.f><.cc> 0,limm,u6 0010011011000101F111uuuuuu1QQQQQ. */ +{ "or", 0x26C57020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* or<.f> 0,limm,s12 0010011010000101F111ssssssSSSSSS. */ +{ "or", 0x26857000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* or<.f> a,limm,limm 0010011000000101F111111110AAAAAA. */ +{ "or", 0x26057F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* or<.f> 0,limm,limm 0010011000000101F111111110111110. */ +{ "or", 0x26057FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* or<.f><.cc> 0,limm,limm 0010011011000101F1111111100QQQQQ. */ +{ "or", 0x26C57F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* or_s b,b,c 01111bbbccc00101. */ +{ "or_s", 0x00007805, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* pkqb<.f> a,b,c 00110bbb00100000FBBBCCCCCCAAAAAA. */ +{ "pkqb", 0x30200000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* pkqb<.f><.cc> b,b,c 00110bbb11100000FBBBCCCCCC0QQQQQ. */ +{ "pkqb", 0x30E00000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* pkqb<.f> a,b,u6 00110bbb01100000FBBBuuuuuuAAAAAA. */ +{ "pkqb", 0x30600000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* pkqb<.f><.cc> b,b,u6 00110bbb11100000FBBBuuuuuu1QQQQQ. */ +{ "pkqb", 0x30E00020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* pkqb<.f> b,b,s12 00110bbb10100000FBBBssssssSSSSSS. */ +{ "pkqb", 0x30A00000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* pkqb<.f> a,limm,c 0011011000100000F111CCCCCCAAAAAA. */ +{ "pkqb", 0x36207000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* pkqb<.f> a,b,limm 00110bbb00100000FBBB111110AAAAAA. */ +{ "pkqb", 0x30200F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* pkqb<.f><.cc> b,b,limm 00110bbb11100000FBBB1111100QQQQQ. */ +{ "pkqb", 0x30E00F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* pop_s b 11000bbb11000001. */ +{ "pop_s", 0x0000C0C1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }}, + +/* pop_s BLINK 11000RRR11010001. */ +{ "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }}, + +/* prealloc<.aa> b,c 00100bbbaa1100010BBBCCCCCC111110. */ +{ "prealloc", 0x2031003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }}, + +/* prealloc<.aa> b,s9 00010bbbssssssssSBBB0aa001111110. */ +{ "prealloc", 0x1000007E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }}, + +/* prealloc<.aa> b,limm 00100bbbaa1100010BBB111110111110. */ +{ "prealloc", 0x20310FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }}, + +/* prealloc limm,c 00100110RR1100010111CCCCCC111110. */ +{ "prealloc", 0x2631703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }}, + +/* prealloc limm 000101100000000001110RR001111110. */ +{ "prealloc", 0x1600707E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* prealloc limm,s9 00010110ssssssssS1110RR001111110. */ +{ "prealloc", 0x1600707E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }}, + +/* prefetch<.aa> b,c 00100bbbaa1100000BBBCCCCCC111110. */ +{ "prefetch", 0x2030003E, 0xF83F803F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }}, + +/* prefetch b 00010bbb000000000BBB0RR000111110. */ +{ "prefetch", 0x1000003E, 0xF8FF89FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, RB, BRAKETdup }, { 0 }}, + +/* prefetch<.aa> b,s9 00010bbbssssssssSBBB0aa000111110. */ +{ "prefetch", 0x1000003E, 0xF80009FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }}, + +/* prefetch<.aa> b,limm 00100bbbaa1100000BBB111110111110. */ +{ "prefetch", 0x20300FBE, 0xF83F8FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }}, + +/* prefetch<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ +{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { C_AA8 }}, + +/* prefetch limm,c 00100110RR1100000111CCCCCC111110. */ +{ "prefetch", 0x2630703E, 0xFF3FF03F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }}, + +/* prefetch limm 000101100000000001110RR000111110. */ +{ "prefetch", 0x1600703E, 0xFFFFF9FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* prefetch<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ +{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_AA21 }}, + +/* prefetch limm,s9 00010110ssssssssS1110RR000111110. */ +{ "prefetch", 0x1600703E, 0xFF0079FF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }}, + +/* prefetch<.aa> limm,limm 00100110aa1100000111111110111110. */ +{ "prefetch", 0x26307FBE, 0xFF3FFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { BRAKET, LIMM, LIMMdup, BRAKETdup }, { C_AA8 }}, + +/* prefetchl2<.aa> b,c 00100bbbaa1100100BBBCCCCCC111110. */ +{ "prefetchl2", 0x2032003E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_AA8 }}, + +/* prefetchl2 b 00010bbb000000000BBB0RR000111110. */ +{ "prefetchl2", 0x1000003E, 0xF8FF89FF, 0, MEMORY, NONE, { RB }, { 0 }}, + +/* prefetchl2<.aa> b,s9 00010bbbssssssssSBBB0aa010111110. */ +{ "prefetchl2", 0x100000BE, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, SIMM9_8 }, { C_AA21 }}, + +/* prefetchl2<.aa> b,limm 00100bbbaa1100100BBB111110111110. */ +{ "prefetchl2", 0x20320FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_AA8 }}, + +/* prefetchl2<.aa> limm,c 00100110aa1100000111CCCCCC111110. */ +{ "prefetchl2", 0x2630703E, 0xFF3FF03F, 0, MEMORY, NONE, { LIMM, RC }, { C_AA8 }}, + +/* prefetchl2 limm,c 00100110RR1100100111CCCCCC111110. */ +{ "prefetchl2", 0x2632703E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, RC }, { 0 }}, + +/* prefetchl2 limm 000101100000000001110RR010111110. */ +{ "prefetchl2", 0x160070BE, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM }, { 0 }}, + +/* prefetchl2<.aa> limm,s9 00010110ssssssssS1110aa000111110. */ +{ "prefetchl2", 0x1600703E, 0xFF0079FF, 0, MEMORY, NONE, { LIMM, SIMM9_8 }, { C_AA21 }}, + +/* prefetchl2 limm,s9 00010110ssssssssS1110RR010111110. */ +{ "prefetchl2", 0x160070BE, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, SIMM9_8 }, { 0 }}, + +/* prefetchl2<.aa> limm,limm 00100110aa1100000111111110111110. */ +{ "prefetchl2", 0x26307FBE, 0xFF3FFFFF, 0, MEMORY, NONE, { LIMM, LIMMdup }, { C_AA8 }}, + +/* prefetchw<.aa> b,c 00100bbbaa1100001BBBCCCCCC111110. */ +{ "prefetchw", 0x2030803E, 0xF83F803F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, RC, BRAKETdup }, { C_AA8 }}, + +/* prefetchw<.aa> b,s9 00010bbbssssssssSBBB1aa000111110. */ +{ "prefetchw", 0x1000083E, 0xF80009FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, SIMM9_8, BRAKETdup }, { C_AA21 }}, + +/* prefetchw<.aa> b,limm 00100bbbaa1100001BBB111110111110. */ +{ "prefetchw", 0x20308FBE, 0xF83F8FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, RB, LIMM, BRAKETdup }, { C_AA8 }}, + +/* prefetchw limm,c 00100110RR1100001111CCCCCC111110. */ +{ "prefetchw", 0x2630F03E, 0xFF3FF03F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, RC, BRAKETdup }, { 0 }}, + +/* prefetchw limm 000101100000000001111RR000111110. */ +{ "prefetchw", 0x1600783E, 0xFFFFF9FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* prefetchw limm,s9 00010110ssssssssS1111RR000111110. */ +{ "prefetchw", 0x1600783E, 0xFF0079FF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BRAKET, LIMM, SIMM9_8, BRAKETdup }, { 0 }}, + +/* push_s b 11000bbb11100001. */ +{ "push_s", 0x0000C0E1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S }, { 0 }}, + +/* push_s blink 11000RRR11110001. */ +{ "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { BLINK_S }, { 0 }}, + +/* qmach<.f> a,b,c 00101bbb00110100FBBBCCCCCCAAAAAA. */ +{ "qmach", 0x28340000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* qmach<.f> 0,b,c 00101bbb00110100FBBBCCCCCC111110. */ +{ "qmach", 0x2834003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* qmach<.f><.cc> b,b,c 00101bbb11110100FBBBCCCCCC0QQQQQ. */ +{ "qmach", 0x28F40000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* qmach<.f> a,b,u6 00101bbb01110100FBBBuuuuuuAAAAAA. */ +{ "qmach", 0x28740000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* qmach<.f> 0,b,u6 00101bbb01110100FBBBuuuuuu111110. */ +{ "qmach", 0x2874003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* qmach<.f><.cc> b,b,u6 00101bbb11110100FBBBuuuuuu1QQQQQ. */ +{ "qmach", 0x28F40020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* qmach<.f> b,b,s12 00101bbb10110100FBBBssssssSSSSSS. */ +{ "qmach", 0x28B40000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* qmach<.f> a,limm,c 0010111000110100F111CCCCCCAAAAAA. */ +{ "qmach", 0x2E347000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* qmach<.f> a,b,limm 00101bbb00110100FBBB111110AAAAAA. */ +{ "qmach", 0x28340F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* qmach<.f> 0,limm,c 0010111000110100F111CCCCCC111110. */ +{ "qmach", 0x2E34703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* qmach<.f> 0,b,limm 00101bbb00110100FBBB111110111110. */ +{ "qmach", 0x28340FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* qmach<.f><.cc> b,b,limm 00101bbb11110100FBBB1111100QQQQQ. */ +{ "qmach", 0x28F40F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* qmach<.f><.cc> 0,limm,c 0010111011110100F111CCCCCC0QQQQQ. */ +{ "qmach", 0x2EF47000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* qmach<.f> a,limm,u6 0010111001110100F111uuuuuuAAAAAA. */ +{ "qmach", 0x2E747000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmach<.f> 0,limm,u6 0010111001110100F111uuuuuu111110. */ +{ "qmach", 0x2E74703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmach<.f><.cc> 0,limm,u6 0010111011110100F111uuuuuu1QQQQQ. */ +{ "qmach", 0x2EF47020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* qmach<.f> 0,limm,s12 0010111010110100F111ssssssSSSSSS. */ +{ "qmach", 0x2EB47000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* qmach<.f> a,limm,limm 0010111000110100F111111110AAAAAA. */ +{ "qmach", 0x2E347F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* qmach<.f> 0,limm,limm 0010111000110100F111111110111110. */ +{ "qmach", 0x2E347FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* qmach<.f><.cc> 0,limm,limm 0010111011110100F1111111100QQQQQ. */ +{ "qmach", 0x2EF47F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* qmachu<.f> a,b,c 00101bbb00110101FBBBCCCCCCAAAAAA. */ +{ "qmachu", 0x28350000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* qmachu<.f> 0,b,c 00101bbb00110101FBBBCCCCCC111110. */ +{ "qmachu", 0x2835003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* qmachu<.f><.cc> b,b,c 00101bbb11110101FBBBCCCCCC0QQQQQ. */ +{ "qmachu", 0x28F50000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* qmachu<.f> a,b,u6 00101bbb01110101FBBBuuuuuuAAAAAA. */ +{ "qmachu", 0x28750000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* qmachu<.f> 0,b,u6 00101bbb01110101FBBBuuuuuu111110. */ +{ "qmachu", 0x2875003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* qmachu<.f><.cc> b,b,u6 00101bbb11110101FBBBuuuuuu1QQQQQ. */ +{ "qmachu", 0x28F50020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* qmachu<.f> b,b,s12 00101bbb10110101FBBBssssssSSSSSS. */ +{ "qmachu", 0x28B50000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* qmachu<.f> a,limm,c 0010111000110101F111CCCCCCAAAAAA. */ +{ "qmachu", 0x2E357000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* qmachu<.f> a,b,limm 00101bbb00110101FBBB111110AAAAAA. */ +{ "qmachu", 0x28350F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* qmachu<.f> 0,limm,c 0010111000110101F111CCCCCC111110. */ +{ "qmachu", 0x2E35703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* qmachu<.f> 0,b,limm 00101bbb00110101FBBB111110111110. */ +{ "qmachu", 0x28350FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* qmachu<.f><.cc> b,b,limm 00101bbb11110101FBBB1111100QQQQQ. */ +{ "qmachu", 0x28F50F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* qmachu<.f><.cc> 0,limm,c 0010111011110101F111CCCCCC0QQQQQ. */ +{ "qmachu", 0x2EF57000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* qmachu<.f> a,limm,u6 0010111001110101F111uuuuuuAAAAAA. */ +{ "qmachu", 0x2E757000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmachu<.f> 0,limm,u6 0010111001110101F111uuuuuu111110. */ +{ "qmachu", 0x2E75703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmachu<.f><.cc> 0,limm,u6 0010111011110101F111uuuuuu1QQQQQ. */ +{ "qmachu", 0x2EF57020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* qmachu<.f> 0,limm,s12 0010111010110101F111ssssssSSSSSS. */ +{ "qmachu", 0x2EB57000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* qmachu<.f> a,limm,limm 0010111000110101F111111110AAAAAA. */ +{ "qmachu", 0x2E357F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* qmachu<.f> 0,limm,limm 0010111000110101F111111110111110. */ +{ "qmachu", 0x2E357FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* qmachu<.f><.cc> 0,limm,limm 0010111011110101F1111111100QQQQQ. */ +{ "qmachu", 0x2EF57F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* qmpyh<.f> a,b,c 00101bbb00110000FBBBCCCCCCAAAAAA. */ +{ "qmpyh", 0x28300000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* qmpyh<.f> 0,b,c 00101bbb00110000FBBBCCCCCC111110. */ +{ "qmpyh", 0x2830003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,c 00101bbb11110000FBBBCCCCCC0QQQQQ. */ +{ "qmpyh", 0x28F00000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* qmpyh<.f> a,b,u6 00101bbb01110000FBBBuuuuuuAAAAAA. */ +{ "qmpyh", 0x28700000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* qmpyh<.f> 0,b,u6 00101bbb01110000FBBBuuuuuu111110. */ +{ "qmpyh", 0x2870003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,u6 00101bbb11110000FBBBuuuuuu1QQQQQ. */ +{ "qmpyh", 0x28F00020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyh<.f> b,b,s12 00101bbb10110000FBBBssssssSSSSSS. */ +{ "qmpyh", 0x28B00000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* qmpyh<.f> a,limm,c 0010111000110000F111CCCCCCAAAAAA. */ +{ "qmpyh", 0x2E307000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* qmpyh<.f> a,b,limm 00101bbb00110000FBBB111110AAAAAA. */ +{ "qmpyh", 0x28300F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* qmpyh<.f> 0,limm,c 0010111000110000F111CCCCCC111110. */ +{ "qmpyh", 0x2E30703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* qmpyh<.f> 0,b,limm 00101bbb00110000FBBB111110111110. */ +{ "qmpyh", 0x28300FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* qmpyh<.f><.cc> b,b,limm 00101bbb11110000FBBB1111100QQQQQ. */ +{ "qmpyh", 0x28F00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* qmpyh<.f><.cc> 0,limm,c 0010111011110000F111CCCCCC0QQQQQ. */ +{ "qmpyh", 0x2EF07000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* qmpyh<.f> a,limm,u6 0010111001110000F111uuuuuuAAAAAA. */ +{ "qmpyh", 0x2E707000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmpyh<.f> 0,limm,u6 0010111001110000F111uuuuuu111110. */ +{ "qmpyh", 0x2E70703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmpyh<.f><.cc> 0,limm,u6 0010111011110000F111uuuuuu1QQQQQ. */ +{ "qmpyh", 0x2EF07020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyh<.f> 0,limm,s12 0010111010110000F111ssssssSSSSSS. */ +{ "qmpyh", 0x2EB07000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* qmpyh<.f> a,limm,limm 0010111000110000F111111110AAAAAA. */ +{ "qmpyh", 0x2E307F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* qmpyh<.f> 0,limm,limm 0010111000110000F111111110111110. */ +{ "qmpyh", 0x2E307FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* qmpyh<.f><.cc> 0,limm,limm 0010111011110000F1111111100QQQQQ. */ +{ "qmpyh", 0x2EF07F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* qmpyhu<.f> a,b,c 00101bbb00110001FBBBCCCCCCAAAAAA. */ +{ "qmpyhu", 0x28310000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { C_F }}, + +/* qmpyhu<.f> 0,b,c 00101bbb00110001FBBBCCCCCC111110. */ +{ "qmpyhu", 0x2831003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,c 00101bbb11110001FBBBCCCCCC0QQQQQ. */ +{ "qmpyhu", 0x28F10000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* qmpyhu<.f> a,b,u6 00101bbb01110001FBBBuuuuuuAAAAAA. */ +{ "qmpyhu", 0x28710000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f> 0,b,u6 00101bbb01110001FBBBuuuuuu111110. */ +{ "qmpyhu", 0x2871003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,u6 00101bbb11110001FBBBuuuuuu1QQQQQ. */ +{ "qmpyhu", 0x28F10020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhu<.f> b,b,s12 00101bbb10110001FBBBssssssSSSSSS. */ +{ "qmpyhu", 0x28B10000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* qmpyhu<.f> a,limm,c 0010111000110001F111CCCCCCAAAAAA. */ +{ "qmpyhu", 0x2E317000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { C_F }}, + +/* qmpyhu<.f> a,b,limm 00101bbb00110001FBBB111110AAAAAA. */ +{ "qmpyhu", 0x28310F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { C_F }}, + +/* qmpyhu<.f> 0,limm,c 0010111000110001F111CCCCCC111110. */ +{ "qmpyhu", 0x2E31703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F }}, + +/* qmpyhu<.f> 0,b,limm 00101bbb00110001FBBB111110111110. */ +{ "qmpyhu", 0x28310FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { C_F }}, + +/* qmpyhu<.f><.cc> b,b,limm 00101bbb11110001FBBB1111100QQQQQ. */ +{ "qmpyhu", 0x28F10F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* qmpyhu<.f><.cc> 0,limm,c 0010111011110001F111CCCCCC0QQQQQ. */ +{ "qmpyhu", 0x2EF17000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* qmpyhu<.f> a,limm,u6 0010111001110001F111uuuuuuAAAAAA. */ +{ "qmpyhu", 0x2E717000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f> 0,limm,u6 0010111001110001F111uuuuuu111110. */ +{ "qmpyhu", 0x2E71703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* qmpyhu<.f><.cc> 0,limm,u6 0010111011110001F111uuuuuu1QQQQQ. */ +{ "qmpyhu", 0x2EF17020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* qmpyhu<.f> 0,limm,s12 0010111010110001F111ssssssSSSSSS. */ +{ "qmpyhu", 0x2EB17000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* qmpyhu<.f> a,limm,limm 0010111000110001F111111110AAAAAA. */ +{ "qmpyhu", 0x2E317F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { C_F }}, + +/* qmpyhu<.f> 0,limm,limm 0010111000110001F111111110111110. */ +{ "qmpyhu", 0x2E317FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* qmpyhu<.f><.cc> 0,limm,limm 0010111011110001F1111111100QQQQQ. */ +{ "qmpyhu", 0x2EF17F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* rcmp b,c 00100bbb000011011BBBCCCCCCRRRRRR. */ +{ "rcmp", 0x200D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { 0 }}, + +/* rcmp b,c 00100bbb000011011BBBCCCCCC000000. */ +{ "rcmp", 0x200D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RC }, { 0 }}, + +/* rcmp<.cc> b,c 00100bbb110011011BBBCCCCCC0QQQQQ. */ +{ "rcmp", 0x20CD8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_CC }}, + +/* rcmp b,u6 00100bbb010011011BBBuuuuuuRRRRRR. */ +{ "rcmp", 0x204D8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* rcmp b,u6 00100bbb010011011BBBuuuuuu000000. */ +{ "rcmp", 0x204D8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* rcmp<.cc> b,u6 00100bbb110011011BBBuuuuuu1QQQQQ. */ +{ "rcmp", 0x20CD8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* rcmp b,s12 00100bbb100011011BBBssssssSSSSSS. */ +{ "rcmp", 0x208D8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* rcmp limm,c 00100110000011011111CCCCCCRRRRRR. */ +{ "rcmp", 0x260DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* rcmp b,limm 00100bbb000011011BBB111110RRRRRR. */ +{ "rcmp", 0x200D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* rcmp limm,c 00100110000011011111CCCCCC000000. */ +{ "rcmp", 0x260DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, RC }, { 0 }}, + +/* rcmp b,limm 00100bbb000011011BBB111110000000. */ +{ "rcmp", 0x200D8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, LIMM }, { 0 }}, + +/* rcmp<.cc> limm,c 00100110110011011111CCCCCC0QQQQQ. */ +{ "rcmp", 0x26CDF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, RC }, { C_CC }}, + +/* rcmp<.cc> b,limm 00100bbb110011011BBB1111100QQQQQ. */ +{ "rcmp", 0x20CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_CC }}, + +/* rcmp limm,u6 00100110010011011111uuuuuuRRRRRR. */ +{ "rcmp", 0x264DF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* rcmp limm,u6 00100110010011011111uuuuuu000000. */ +{ "rcmp", 0x264DF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* rcmp<.cc> limm,u6 00100110110011011111uuuuuu1QQQQQ. */ +{ "rcmp", 0x26CDF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* rcmp limm,s12 00100110100011011111ssssssSSSSSS. */ +{ "rcmp", 0x268DF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* rcmp limm,limm 00100110000011011111111110RRRRRR. */ +{ "rcmp", 0x260DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* rcmp limm,limm 00100110000011011111111110000000. */ +{ "rcmp", 0x260DFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* rcmp<.cc> limm,limm 001001101100110111111111100QQQQQ. */ +{ "rcmp", 0x26CDFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* rem<.f> a,b,c 00101bbb00001000FBBBCCCCCCAAAAAA. */ +{ "rem", 0x28080000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }}, + +/* rem<.f> 0,b,c 00101bbb00001000FBBBCCCCCC111110. */ +{ "rem", 0x2808003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }}, + +/* rem<.f><.cc> b,b,c 00101bbb11001000FBBBCCCCCC0QQQQQ. */ +{ "rem", 0x28C80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* rem<.f> a,b,u6 00101bbb01001000FBBBuuuuuuAAAAAA. */ +{ "rem", 0x28480000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }}, + +/* rem<.f> 0,b,u6 00101bbb01001000FBBBuuuuuu111110. */ +{ "rem", 0x2848003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* rem<.f><.cc> b,b,u6 00101bbb11001000FBBBuuuuuu1QQQQQ. */ +{ "rem", 0x28C80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* rem<.f> b,b,s12 00101bbb10001000FBBBssssssSSSSSS. */ +{ "rem", 0x28880000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* rem<.f> a,limm,c 0010111000001000F111CCCCCCAAAAAA. */ +{ "rem", 0x2E087000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }}, + +/* rem<.f> a,b,limm 00101bbb00001000FBBB111110AAAAAA. */ +{ "rem", 0x28080F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }}, + +/* rem<.f> 0,limm,c 0010111000001000F111CCCCCC111110. */ +{ "rem", 0x2E08703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }}, + +/* rem<.f> 0,b,limm 00101bbb00001000FBBB111110111110. */ +{ "rem", 0x28080FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }}, + +/* rem<.f><.cc> b,b,limm 00101bbb11001000FBBB1111100QQQQQ. */ +{ "rem", 0x28C80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* rem<.f><.cc> 0,limm,c 0010111011001000F111CCCCCC0QQQQQ. */ +{ "rem", 0x2EC87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* rem<.f> a,limm,u6 0010111001001000F111uuuuuuAAAAAA. */ +{ "rem", 0x2E487000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* rem<.f> 0,limm,u6 0010111001001000F111uuuuuu111110. */ +{ "rem", 0x2E48703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* rem<.f><.cc> 0,limm,u6 0010111011001000F111uuuuuu1QQQQQ. */ +{ "rem", 0x2EC87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* rem<.f> 0,limm,s12 0010111010001000F111ssssssSSSSSS. */ +{ "rem", 0x2E887000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* rem<.f> a,limm,limm 0010111000001000F111111110AAAAAA. */ +{ "rem", 0x2E087F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }}, + +/* rem<.f> 0,limm,limm 0010111000001000F111111110111110. */ +{ "rem", 0x2E087FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* rem<.f><.cc> 0,limm,limm 0010111011001000F1111111100QQQQQ. */ +{ "rem", 0x2EC87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* remu<.f> a,b,c 00101bbb00001001FBBBCCCCCCAAAAAA. */ +{ "remu", 0x28090000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, RC }, { C_F }}, + +/* remu<.f> 0,b,c 00101bbb00001001FBBBCCCCCC111110. */ +{ "remu", 0x2809003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, RC }, { C_F }}, + +/* remu<.f><.cc> b,b,c 00101bbb11001001FBBBCCCCCC0QQQQQ. */ +{ "remu", 0x28C90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* remu<.f> a,b,u6 00101bbb01001001FBBBuuuuuuAAAAAA. */ +{ "remu", 0x28490000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, UIMM6_20 }, { C_F }}, + +/* remu<.f> 0,b,u6 00101bbb01001001FBBBuuuuuu111110. */ +{ "remu", 0x2849003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* remu<.f><.cc> b,b,u6 00101bbb11001001FBBBuuuuuu1QQQQQ. */ +{ "remu", 0x28C90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* remu<.f> b,b,s12 00101bbb10001001FBBBssssssSSSSSS. */ +{ "remu", 0x28890000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* remu<.f> a,limm,c 0010111000001001F111CCCCCCAAAAAA. */ +{ "remu", 0x2E097000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, RC }, { C_F }}, + +/* remu<.f> a,b,limm 00101bbb00001001FBBB111110AAAAAA. */ +{ "remu", 0x28090F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, RB, LIMM }, { C_F }}, + +/* remu<.f> 0,limm,c 0010111000001001F111CCCCCC111110. */ +{ "remu", 0x2E09703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F }}, + +/* remu<.f> 0,b,limm 00101bbb00001001FBBB111110111110. */ +{ "remu", 0x28090FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, RB, LIMM }, { C_F }}, + +/* remu<.f><.cc> b,b,limm 00101bbb11001001FBBB1111100QQQQQ. */ +{ "remu", 0x28C90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* remu<.f><.cc> 0,limm,c 0010111011001001F111CCCCCC0QQQQQ. */ +{ "remu", 0x2EC97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* remu<.f> a,limm,u6 0010111001001001F111uuuuuuAAAAAA. */ +{ "remu", 0x2E497000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* remu<.f> 0,limm,u6 0010111001001001F111uuuuuu111110. */ +{ "remu", 0x2E49703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* remu<.f><.cc> 0,limm,u6 0010111011001001F111uuuuuu1QQQQQ. */ +{ "remu", 0x2EC97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* remu<.f> 0,limm,s12 0010111010001001F111ssssssSSSSSS. */ +{ "remu", 0x2E897000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* remu<.f> a,limm,limm 0010111000001001F111111110AAAAAA. */ +{ "remu", 0x2E097F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { RA, LIMM, LIMMdup }, { C_F }}, + +/* remu<.f> 0,limm,limm 0010111000001001F111111110111110. */ +{ "remu", 0x2E097FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* remu<.f><.cc> 0,limm,limm 0010111011001001F1111111100QQQQQ. */ +{ "remu", 0x2EC97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, DIV, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* rlc<.f> b,c 00100bbb00101111FBBBCCCCCC001011. */ +{ "rlc", 0x202F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* rlc<.f> 0,c 0010011000101111F111CCCCCC001011. */ +{ "rlc", 0x262F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* rlc<.f> b,u6 00100bbb01101111FBBBuuuuuu001011. */ +{ "rlc", 0x206F000B, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* rlc<.f> 0,u6 0010011001101111F111uuuuuu001011. */ +{ "rlc", 0x266F700B, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* rlc<.f> b,limm 00100bbb00101111FBBB111110001011. */ +{ "rlc", 0x202F0F8B, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* rlc<.f> 0,limm 0010011000101111F111111110001011. */ +{ "rlc", 0x262F7F8B, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* rnd16<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ +{ "rnd16", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* rnd16<.f> 0,c 0010111000101111F111CCCCCC000011. */ +{ "rnd16", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* rnd16<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ +{ "rnd16", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* rnd16<.f> 0,u6 0010111001101111F111uuuuuu000011. */ +{ "rnd16", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* rnd16<.f> b,limm 00101bbb00101111FBBB111110000011. */ +{ "rnd16", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* rnd16<.f> 0,limm 0010111000101111F111111110000011. */ +{ "rnd16", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* rndh<.f> b,c 00101bbb00101111FBBBCCCCCC000011. */ +{ "rndh", 0x282F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }}, + +/* rndh<.f> 0,c 0010111000101111F111CCCCCC000011. */ +{ "rndh", 0x2E2F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }}, + +/* rndh<.f> b,u6 00101bbb01101111FBBBuuuuuu000011. */ +{ "rndh", 0x286F0003, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* rndh<.f> 0,u6 0010111001101111F111uuuuuu000011. */ +{ "rndh", 0x2E6F7003, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* rndh<.f> b,limm 00101bbb00101111FBBB111110000011. */ +{ "rndh", 0x282F0F83, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* rndh<.f> 0,limm 0010111000101111F111111110000011. */ +{ "rndh", 0x2E2F7F83, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* rol<.f> b,c 00100bbb00101111FBBBCCCCCC001101. */ +{ "rol", 0x202F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* rol<.f> 0,c 0010011000101111F111CCCCCC001101. */ +{ "rol", 0x262F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* rol<.f> b,u6 00100bbb01101111FBBBuuuuuu001101. */ +{ "rol", 0x206F000D, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* rol<.f> 0,u6 0010011001101111F111uuuuuu001101. */ +{ "rol", 0x266F700D, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* rol<.f> b,limm 00100bbb00101111FBBB111110001101. */ +{ "rol", 0x202F0F8D, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* rol<.f> 0,limm 0010011000101111F111111110001101. */ +{ "rol", 0x262F7F8D, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* rol8<.f> b,c 00101bbb00101111FBBBCCCCCC010000. */ +{ "rol8", 0x282F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, RC }, { C_F }}, + +/* rol8<.f> 0,c 0010111000101111F111CCCCCC010000. */ +{ "rol8", 0x2E2F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, RC }, { C_F }}, + +/* rol8<.f> b,u6 00101bbb01101111FBBBuuuuuu010000. */ +{ "rol8", 0x286F0010, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* rol8<.f> 0,u6 0010111001101111F111uuuuuu010000. */ +{ "rol8", 0x2E6F7010, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* rol8<.f> b,limm 00101bbb00101111FBBB111110010000. */ +{ "rol8", 0x282F0F90, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, LIMM }, { C_F }}, + +/* rol8<.f> 0,limm 0010111000101111F111111110010000. */ +{ "rol8", 0x2E2F7F90, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }}, + +/* ror<.f> b,c 00100bbb00101111FBBBCCCCCC000011. */ +{ "ror", 0x202F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* ror<.f> 0,c 0010011000101111F111CCCCCC000011. */ +{ "ror", 0x262F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* ror<.f> a,b,c 00101bbb00000011FBBBCCCCCCAAAAAA. */ +{ "ror", 0x28030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, RC }, { C_F }}, + +/* ror<.f> 0,b,c 00101bbb00000011FBBBCCCCCC111110. */ +{ "ror", 0x2803003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, RC }, { C_F }}, + +/* ror<.f><.cc> b,b,c 00101bbb11000011FBBBCCCCCC0QQQQQ. */ +{ "ror", 0x28C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* ror<.f> b,u6 00100bbb01101111FBBBuuuuuu000011. */ +{ "ror", 0x206F0003, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,u6 0010011001101111F111uuuuuu000011. */ +{ "ror", 0x266F7003, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* ror<.f> a,b,u6 00101bbb01000011FBBBuuuuuuAAAAAA. */ +{ "ror", 0x28430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,b,u6 00101bbb01000011FBBBuuuuuu111110. */ +{ "ror", 0x2843003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* ror<.f><.cc> b,b,u6 00101bbb11000011FBBBuuuuuu1QQQQQ. */ +{ "ror", 0x28C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* ror<.f> b,b,s12 00101bbb10000011FBBBssssssSSSSSS. */ +{ "ror", 0x28830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* ror<.f> b,limm 00100bbb00101111FBBB111110000011. */ +{ "ror", 0x202F0F83, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* ror<.f> 0,limm 0010011000101111F111111110000011. */ +{ "ror", 0x262F7F83, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* ror<.f> a,limm,c 0010111000000011F111CCCCCCAAAAAA. */ +{ "ror", 0x2E037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, RC }, { C_F }}, + +/* ror<.f> a,b,limm 00101bbb00000011FBBB111110AAAAAA. */ +{ "ror", 0x28030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, RB, LIMM }, { C_F }}, + +/* ror<.f> 0,limm,c 0010111000000011F111CCCCCC111110. */ +{ "ror", 0x2E03703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F }}, + +/* ror<.f> 0,b,limm 00101bbb00000011FBBB111110111110. */ +{ "ror", 0x28030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, RB, LIMM }, { C_F }}, + +/* ror<.f><.cc> b,b,limm 00101bbb11000011FBBB1111100QQQQQ. */ +{ "ror", 0x28C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* ror<.f><.cc> 0,limm,c 0010111011000011F111CCCCCC0QQQQQ. */ +{ "ror", 0x2EC37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* ror<.f> a,limm,u6 0010111001000011F111uuuuuuAAAAAA. */ +{ "ror", 0x2E437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* ror<.f> 0,limm,u6 0010111001000011F111uuuuuu111110. */ +{ "ror", 0x2E43703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* ror<.f><.cc> 0,limm,u6 0010111011000011F111uuuuuu1QQQQQ. */ +{ "ror", 0x2EC37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* ror<.f> 0,limm,s12 0010111010000011F111ssssssSSSSSS. */ +{ "ror", 0x2E837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* ror<.f> a,limm,limm 0010111000000011F111111110AAAAAA. */ +{ "ror", 0x2E037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { RA, LIMM, LIMMdup }, { C_F }}, + +/* ror<.f> 0,limm,limm 0010111000000011F111111110111110. */ +{ "ror", 0x2E037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* ror<.f><.cc> 0,limm,limm 0010111011000011F1111111100QQQQQ. */ +{ "ror", 0x2EC37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* ror8<.f> b,c 00101bbb00101111FBBBCCCCCC010001. */ +{ "ror8", 0x282F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, RC }, { C_F }}, + +/* ror8<.f> 0,c 0010111000101111F111CCCCCC010001. */ +{ "ror8", 0x2E2F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, RC }, { C_F }}, + +/* ror8<.f> b,u6 00101bbb01101111FBBBuuuuuu010001. */ +{ "ror8", 0x286F0011, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, UIMM6_20 }, { C_F }}, + +/* ror8<.f> 0,u6 0010111001101111F111uuuuuu010001. */ +{ "ror8", 0x2E6F7011, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, UIMM6_20 }, { C_F }}, + +/* ror8<.f> b,limm 00101bbb00101111FBBB111110010001. */ +{ "ror8", 0x282F0F91, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { RB, LIMM }, { C_F }}, + +/* ror8<.f> 0,limm 0010111000101111F111111110010001. */ +{ "ror8", 0x2E2F7F91, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, SHFT1, { ZA, LIMM }, { C_F }}, + +/* rrc<.f> b,c 00100bbb00101111FBBBCCCCCC000100. */ +{ "rrc", 0x202F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_F }}, + +/* rrc<.f> 0,c 0010011000101111F111CCCCCC000100. */ +{ "rrc", 0x262F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RC }, { C_F }}, + +/* rrc<.f> b,u6 00100bbb01101111FBBBuuuuuu000100. */ +{ "rrc", 0x206F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* rrc<.f> 0,u6 0010011001101111F111uuuuuu000100. */ +{ "rrc", 0x266F7004, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* rrc<.f> b,limm 00100bbb00101111FBBB111110000100. */ +{ "rrc", 0x202F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_F }}, + +/* rrc<.f> 0,limm 0010011000101111F111111110000100. */ +{ "rrc", 0x262F7F84, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM }, { C_F }}, + +/* rsub<.f> a,b,c 00100bbb00001110FBBBCCCCCCAAAAAA. */ +{ "rsub", 0x200E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* rsub<.f> 0,b,c 00100bbb00001110FBBBCCCCCC111110. */ +{ "rsub", 0x200E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* rsub<.f><.cc> b,b,c 00100bbb11001110FBBBCCCCCC0QQQQQ. */ +{ "rsub", 0x20CE0000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* rsub<.f> a,b,u6 00100bbb01001110FBBBuuuuuuAAAAAA. */ +{ "rsub", 0x204E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* rsub<.f> 0,b,u6 00100bbb01001110FBBBuuuuuu111110. */ +{ "rsub", 0x204E003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* rsub<.f><.cc> b,b,u6 00100bbb11001110FBBBuuuuuu1QQQQQ. */ +{ "rsub", 0x20CE0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* rsub<.f> b,b,s12 00100bbb10001110FBBBssssssSSSSSS. */ +{ "rsub", 0x208E0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* rsub<.f> a,limm,c 0010011000001110F111CCCCCCAAAAAA. */ +{ "rsub", 0x260E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* rsub<.f> a,b,limm 00100bbb00001110FBBB111110AAAAAA. */ +{ "rsub", 0x200E0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* rsub<.f> 0,limm,c 0010011000001110F111CCCCCC111110. */ +{ "rsub", 0x260E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* rsub<.f> 0,b,limm 00100bbb00001110FBBB111110111110. */ +{ "rsub", 0x200E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* rsub<.f><.cc> b,b,limm 00100bbb11001110FBBB1111100QQQQQ. */ +{ "rsub", 0x20CE0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* rsub<.f><.cc> 0,limm,c 0010011011001110F111CCCCCC0QQQQQ. */ +{ "rsub", 0x26CE7000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* rsub<.f> a,limm,u6 0010011001001110F111uuuuuuAAAAAA. */ +{ "rsub", 0x264E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* rsub<.f> 0,limm,u6 0010011001001110F111uuuuuu111110. */ +{ "rsub", 0x264E703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* rsub<.f><.cc> 0,limm,u6 0010011011001110F111uuuuuu1QQQQQ. */ +{ "rsub", 0x26CE7020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* rsub<.f> 0,limm,s12 0010011010001110F111ssssssSSSSSS. */ +{ "rsub", 0x268E7000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* rsub<.f> a,limm,limm 0010011000001110F111111110AAAAAA. */ +{ "rsub", 0x260E7F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* rsub<.f> 0,limm,limm 0010011000001110F111111110111110. */ +{ "rsub", 0x260E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* rsub<.f><.cc> 0,limm,limm 0010011011001110F1111111100QQQQQ. */ +{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* rtie 00100100011011110000000000111111. */ +{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* rtsc b,0 00110bbb01101111RBBB000000011010. */ +{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, ZB }, { 0 }}, + +/* rtsc 0,0 0011011001101111R111000000011010. */ +{ "rtsc", 0x366F701A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, ZB }, { 0 }}, + +/* rtsc b,c 00110bbb00101111RBBBCCCCCC011010. */ +{ "rtsc", 0x302F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, RC }, { 0 }}, + +/* rtsc 0,c 0011011000101111R111CCCCCC011010. */ +{ "rtsc", 0x362F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, RC }, { 0 }}, + +/* rtsc b,u6 00110bbb01101111RBBBuuuuuu011010. */ +{ "rtsc", 0x306F001A, 0xF8FF003F, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* rtsc 0,u6 0011011001101111R111uuuuuu011010. */ +{ "rtsc", 0x366F701A, 0xFFFF703F, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* rtsc b,limm 00110bbb00101111RBBB111110011010. */ +{ "rtsc", 0x302F0F9A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, LIMM }, { 0 }}, + +/* rtsc 0,limm 0011011000101111R111111110011010. */ +{ "rtsc", 0x362F7F9A, 0xFFFF7FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { ZA, LIMM }, { 0 }}, + +/* sat16<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ +{ "sat16", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* sat16<.f> 0,c 0010111000101111F111CCCCCC000010. */ +{ "sat16", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* sat16<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ +{ "sat16", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* sat16<.f> 0,u6 0010111001101111F111uuuuuu000010. */ +{ "sat16", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* sat16<.f> b,limm 00101bbb00101111FBBB111110000010. */ +{ "sat16", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* sat16<.f> 0,limm 0010111000101111F111111110000010. */ +{ "sat16", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* sath<.f> b,c 00101bbb00101111FBBBCCCCCC000010. */ +{ "sath", 0x282F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { C_F }}, + +/* sath<.f> 0,c 0010111000101111F111CCCCCC000010. */ +{ "sath", 0x2E2F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { C_F }}, + +/* sath<.f> b,u6 00101bbb01101111FBBBuuuuuu000010. */ +{ "sath", 0x286F0002, 0xF8FF003F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* sath<.f> 0,u6 0010111001101111F111uuuuuu000010. */ +{ "sath", 0x2E6F7002, 0xFFFF703F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* sath<.f> b,limm 00101bbb00101111FBBB111110000010. */ +{ "sath", 0x282F0F82, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* sath<.f> 0,limm 0010111000101111F111111110000010. */ +{ "sath", 0x2E2F7F82, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* sbc<.f> a,b,c 00100bbb00000011FBBBCCCCCCAAAAAA. */ +{ "sbc", 0x20030000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sbc<.f> 0,b,c 00100bbb00000011FBBBCCCCCC111110. */ +{ "sbc", 0x2003003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* sbc<.f><.cc> b,b,c 00100bbb11000011FBBBCCCCCC0QQQQQ. */ +{ "sbc", 0x20C30000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sbc<.f> a,b,u6 00100bbb01000011FBBBuuuuuuAAAAAA. */ +{ "sbc", 0x20430000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sbc<.f> 0,b,u6 00100bbb01000011FBBBuuuuuu111110. */ +{ "sbc", 0x2043003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* sbc<.f><.cc> b,b,u6 00100bbb11000011FBBBuuuuuu1QQQQQ. */ +{ "sbc", 0x20C30020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sbc<.f> b,b,s12 00100bbb10000011FBBBssssssSSSSSS. */ +{ "sbc", 0x20830000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sbc<.f> a,limm,c 0010011000000011F111CCCCCCAAAAAA. */ +{ "sbc", 0x26037000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sbc<.f> a,b,limm 00100bbb00000011FBBB111110AAAAAA. */ +{ "sbc", 0x20030F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sbc<.f> 0,limm,c 0010011000000011F111CCCCCC111110. */ +{ "sbc", 0x2603703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* sbc<.f> 0,b,limm 00100bbb00000011FBBB111110111110. */ +{ "sbc", 0x20030FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* sbc<.f><.cc> b,b,limm 00100bbb11000011FBBB1111100QQQQQ. */ +{ "sbc", 0x20C30F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sbc<.f><.cc> 0,limm,c 0010011011000011F111CCCCCC0QQQQQ. */ +{ "sbc", 0x26C37000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* sbc<.f> a,limm,u6 0010011001000011F111uuuuuuAAAAAA. */ +{ "sbc", 0x26437000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* sbc<.f> 0,limm,u6 0010011001000011F111uuuuuu111110. */ +{ "sbc", 0x2643703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* sbc<.f><.cc> 0,limm,u6 0010011011000011F111uuuuuu1QQQQQ. */ +{ "sbc", 0x26C37020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* sbc<.f> 0,limm,s12 0010011010000011F111ssssssSSSSSS. */ +{ "sbc", 0x26837000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* sbc<.f> a,limm,limm 0010011000000011F111111110AAAAAA. */ +{ "sbc", 0x26037F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* sbc<.f> 0,limm,limm 0010011000000011F111111110111110. */ +{ "sbc", 0x26037FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* sbc<.f><.cc> 0,limm,limm 0010011011000011F1111111100QQQQQ. */ +{ "sbc", 0x26C37F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* scond<.di> b,c 00100bbb00101111DBBBCCCCCC010001. */ +{ "scond", 0x202F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* scond<.di> b,u6 00100bbb01101111DBBBuuuuuu010001. */ +{ "scond", 0x206F0011, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* scond<.di> b,limm 00100bbb00101111DBBB111110010001. */ +{ "scond", 0x202F0F91, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,c 0010011000101111D111CCCCCC010001. */ +{ "scond", 0x262F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,u6 0010011001101111D111uuuuuu010001. */ +{ "scond", 0x266F7011, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }}, + +/* scond<.di> limm,limm 0010011000101111D111111110010001. */ +{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }}, + +/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */ +{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_DI16 }}, + +/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011. */ +{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_DI16 }}, + +/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */ +{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_DI16 }}, + +/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */ +{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* setacc 0,b,c 00101bbb000011011BBBCCCCCC111110. */ +{ "setacc", 0x280D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* setacc<.cc> b,b,c 00101bbb110011011BBBCCCCCC0QQQQQ. */ +{ "setacc", 0x28CD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* setacc a,b,u6 00101bbb010011011BBBuuuuuuAAAAAA. */ +{ "setacc", 0x284D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* setacc 0,b,u6 00101bbb010011011BBBuuuuuu111110. */ +{ "setacc", 0x284D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* setacc<.cc> b,b,u6 00101bbb110011011BBBuuuuuu1QQQQQ. */ +{ "setacc", 0x28CD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* setacc b,b,s12 00101bbb100011011BBBssssssSSSSSS. */ +{ "setacc", 0x288D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* setacc a,limm,c 00101110000011011111CCCCCCAAAAAA. */ +{ "setacc", 0x2E0DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* setacc a,b,limm 00101bbb000011011BBB111110AAAAAA. */ +{ "setacc", 0x280D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* setacc 0,limm,c 00101110000011011111CCCCCC111110. */ +{ "setacc", 0x2E0DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* setacc 0,b,limm 00101bbb000011011BBB111110111110. */ +{ "setacc", 0x280D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* setacc<.cc> b,b,limm 00101bbb110011011BBB1111100QQQQQ. */ +{ "setacc", 0x28CD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* setacc<.cc> 0,limm,c 00101110110011011111CCCCCC0QQQQQ. */ +{ "setacc", 0x2ECDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* setacc a,limm,u6 00101110010011011111uuuuuuAAAAAA. */ +{ "setacc", 0x2E4DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* setacc 0,limm,u6 00101110010011011111uuuuuu111110. */ +{ "setacc", 0x2E4DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* setacc<.cc> 0,limm,u6 00101110110011011111uuuuuu1QQQQQ. */ +{ "setacc", 0x2ECDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* setacc 0,limm,s12 00101110100011011111ssssssSSSSSS. */ +{ "setacc", 0x2E8DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* setacc a,limm,limm 00101110000011011111111110AAAAAA. */ +{ "setacc", 0x2E0DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* setacc 0,limm,limm 00101110000011011111111110111110. */ +{ "setacc", 0x2E0DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* setacc<.cc> 0,limm,limm 001011101100110111111111100QQQQQ. */ +{ "setacc", 0x2ECDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* seteq<.f> a,b,c 00100bbb00111000FBBBCCCCCCAAAAAA. */ +{ "seteq", 0x20380000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* seteq<.f> 0,b,c 00100bbb00111000FBBBCCCCCC111110. */ +{ "seteq", 0x2038003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* seteq<.f><.cc> b,b,c 00100bbb11111000FBBBCCCCCC0QQQQQ. */ +{ "seteq", 0x20F80000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* seteq<.f> a,b,u6 00100bbb01111000FBBBuuuuuuAAAAAA. */ +{ "seteq", 0x20780000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* seteq<.f> 0,b,u6 00100bbb01111000FBBBuuuuuu111110. */ +{ "seteq", 0x2078003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* seteq<.f><.cc> b,b,u6 00100bbb11111000FBBBuuuuuu1QQQQQ. */ +{ "seteq", 0x20F80020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* seteq<.f> b,b,s12 00100bbb10111000FBBBssssssSSSSSS. */ +{ "seteq", 0x20B80000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* seteq<.f> a,limm,c 0010011000111000F111CCCCCCAAAAAA. */ +{ "seteq", 0x26387000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* seteq<.f> a,b,limm 00100bbb00111000FBBB111110AAAAAA. */ +{ "seteq", 0x20380F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* seteq<.f> 0,limm,c 0010011000111000F111CCCCCC111110. */ +{ "seteq", 0x2638703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* seteq<.f> 0,b,limm 00100bbb00111000FBBB111110111110. */ +{ "seteq", 0x20380FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* seteq<.f><.cc> b,b,limm 00100bbb11111000FBBB1111100QQQQQ. */ +{ "seteq", 0x20F80F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* seteq<.f><.cc> 0,limm,c 0010011011111000F111CCCCCC0QQQQQ. */ +{ "seteq", 0x26F87000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* seteq<.f> a,limm,u6 0010011001111000F111uuuuuuAAAAAA. */ +{ "seteq", 0x26787000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* seteq<.f> 0,limm,u6 0010011001111000F111uuuuuu111110. */ +{ "seteq", 0x2678703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* seteq<.f><.cc> 0,limm,u6 0010011011111000F111uuuuuu1QQQQQ. */ +{ "seteq", 0x26F87020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* seteq<.f> 0,limm,s12 0010011010111000F111ssssssSSSSSS. */ +{ "seteq", 0x26B87000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* seteq<.f> a,limm,limm 0010011000111000F111111110AAAAAA. */ +{ "seteq", 0x26387F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* seteq<.f> 0,limm,limm 0010011000111000F111111110111110. */ +{ "seteq", 0x26387FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* seteq<.f><.cc> 0,limm,limm 0010011011111000F1111111100QQQQQ. */ +{ "seteq", 0x26F87F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setge<.f> a,b,c 00100bbb00111011FBBBCCCCCCAAAAAA. */ +{ "setge", 0x203B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setge<.f> 0,b,c 00100bbb00111011FBBBCCCCCC111110. */ +{ "setge", 0x203B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setge<.f><.cc> b,b,c 00100bbb11111011FBBBCCCCCC0QQQQQ. */ +{ "setge", 0x20FB0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setge<.f> a,b,u6 00100bbb01111011FBBBuuuuuuAAAAAA. */ +{ "setge", 0x207B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setge<.f> 0,b,u6 00100bbb01111011FBBBuuuuuu111110. */ +{ "setge", 0x207B003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setge<.f><.cc> b,b,u6 00100bbb11111011FBBBuuuuuu1QQQQQ. */ +{ "setge", 0x20FB0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setge<.f> b,b,s12 00100bbb10111011FBBBssssssSSSSSS. */ +{ "setge", 0x20BB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setge<.f> a,limm,c 0010011000111011F111CCCCCCAAAAAA. */ +{ "setge", 0x263B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setge<.f> a,b,limm 00100bbb00111011FBBB111110AAAAAA. */ +{ "setge", 0x203B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setge<.f> 0,limm,c 0010011000111011F111CCCCCC111110. */ +{ "setge", 0x263B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setge<.f> 0,b,limm 00100bbb00111011FBBB111110111110. */ +{ "setge", 0x203B0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setge<.f><.cc> b,b,limm 00100bbb11111011FBBB1111100QQQQQ. */ +{ "setge", 0x20FB0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setge<.f><.cc> 0,limm,c 0010011011111011F111CCCCCC0QQQQQ. */ +{ "setge", 0x26FB7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setge<.f> a,limm,u6 0010011001111011F111uuuuuuAAAAAA. */ +{ "setge", 0x267B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setge<.f> 0,limm,u6 0010011001111011F111uuuuuu111110. */ +{ "setge", 0x267B703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setge<.f><.cc> 0,limm,u6 0010011011111011F111uuuuuu1QQQQQ. */ +{ "setge", 0x26FB7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setge<.f> 0,limm,s12 0010011010111011F111ssssssSSSSSS. */ +{ "setge", 0x26BB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setge<.f> a,limm,limm 0010011000111011F111111110AAAAAA. */ +{ "setge", 0x263B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setge<.f> 0,limm,limm 0010011000111011F111111110111110. */ +{ "setge", 0x263B7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setge<.f><.cc> 0,limm,limm 0010011011111011F1111111100QQQQQ. */ +{ "setge", 0x26FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setgt<.f> a,b,c 00100bbb00111111FBBBCCCCCCAAAAAA. */ +{ "setgt", 0x203F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setgt<.f> 0,b,c 00100bbb00111111FBBBCCCCCC111110. */ +{ "setgt", 0x203F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setgt<.f><.cc> b,b,c 00100bbb11111111FBBBCCCCCC0QQQQQ. */ +{ "setgt", 0x20FF0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setgt<.f> a,b,u6 00100bbb01111111FBBBuuuuuuAAAAAA. */ +{ "setgt", 0x207F0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setgt<.f> 0,b,u6 00100bbb01111111FBBBuuuuuu111110. */ +{ "setgt", 0x207F003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setgt<.f><.cc> b,b,u6 00100bbb11111111FBBBuuuuuu1QQQQQ. */ +{ "setgt", 0x20FF0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setgt<.f> b,b,s12 00100bbb10111111FBBBssssssSSSSSS. */ +{ "setgt", 0x20BF0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setgt<.f> a,limm,c 0010011000111111F111CCCCCCAAAAAA. */ +{ "setgt", 0x263F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setgt<.f> a,b,limm 00100bbb00111111FBBB111110AAAAAA. */ +{ "setgt", 0x203F0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setgt<.f> 0,limm,c 0010011000111111F111CCCCCC111110. */ +{ "setgt", 0x263F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setgt<.f> 0,b,limm 00100bbb00111111FBBB111110111110. */ +{ "setgt", 0x203F0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setgt<.f><.cc> b,b,limm 00100bbb11111111FBBB1111100QQQQQ. */ +{ "setgt", 0x20FF0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setgt<.f><.cc> 0,limm,c 0010011011111111F111CCCCCC0QQQQQ. */ +{ "setgt", 0x26FF7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setgt<.f> a,limm,u6 0010011001111111F111uuuuuuAAAAAA. */ +{ "setgt", 0x267F7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setgt<.f> 0,limm,u6 0010011001111111F111uuuuuu111110. */ +{ "setgt", 0x267F703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setgt<.f><.cc> 0,limm,u6 0010011011111111F111uuuuuu1QQQQQ. */ +{ "setgt", 0x26FF7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setgt<.f> 0,limm,s12 0010011010111111F111ssssssSSSSSS. */ +{ "setgt", 0x26BF7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setgt<.f> a,limm,limm 0010011000111111F111111110AAAAAA. */ +{ "setgt", 0x263F7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setgt<.f> 0,limm,limm 0010011000111111F111111110111110. */ +{ "setgt", 0x263F7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setgt<.f><.cc> 0,limm,limm 0010011011111111F1111111100QQQQQ. */ +{ "setgt", 0x26FF7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* seths<.f> a,b,c 00100bbb00111101FBBBCCCCCCAAAAAA. */ +{ "seths", 0x203D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* seths<.f> 0,b,c 00100bbb00111101FBBBCCCCCC111110. */ +{ "seths", 0x203D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* seths<.f><.cc> b,b,c 00100bbb11111101FBBBCCCCCC0QQQQQ. */ +{ "seths", 0x20FD0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* seths<.f> a,b,u6 00100bbb01111101FBBBuuuuuuAAAAAA. */ +{ "seths", 0x207D0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* seths<.f> 0,b,u6 00100bbb01111101FBBBuuuuuu111110. */ +{ "seths", 0x207D003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* seths<.f><.cc> b,b,u6 00100bbb11111101FBBBuuuuuu1QQQQQ. */ +{ "seths", 0x20FD0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* seths<.f> b,b,s12 00100bbb10111101FBBBssssssSSSSSS. */ +{ "seths", 0x20BD0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* seths<.f> a,limm,c 0010011000111101F111CCCCCCAAAAAA. */ +{ "seths", 0x263D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* seths<.f> a,b,limm 00100bbb00111101FBBB111110AAAAAA. */ +{ "seths", 0x203D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* seths<.f> 0,limm,c 0010011000111101F111CCCCCC111110. */ +{ "seths", 0x263D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* seths<.f> 0,b,limm 00100bbb00111101FBBB111110111110. */ +{ "seths", 0x203D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* seths<.f><.cc> b,b,limm 00100bbb11111101FBBB1111100QQQQQ. */ +{ "seths", 0x20FD0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* seths<.f><.cc> 0,limm,c 0010011011111101F111CCCCCC0QQQQQ. */ +{ "seths", 0x26FD7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* seths<.f> a,limm,u6 0010011001111101F111uuuuuuAAAAAA. */ +{ "seths", 0x267D7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* seths<.f> 0,limm,u6 0010011001111101F111uuuuuu111110. */ +{ "seths", 0x267D703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* seths<.f><.cc> 0,limm,u6 0010011011111101F111uuuuuu1QQQQQ. */ +{ "seths", 0x26FD7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* seths<.f> 0,limm,s12 0010011010111101F111ssssssSSSSSS. */ +{ "seths", 0x26BD7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* seths<.f> a,limm,limm 0010011000111101F111111110AAAAAA. */ +{ "seths", 0x263D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* seths<.f> 0,limm,limm 0010011000111101F111111110111110. */ +{ "seths", 0x263D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* seths<.f><.cc> 0,limm,limm 0010011011111101F1111111100QQQQQ. */ +{ "seths", 0x26FD7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* seti c 00100110001011110000CCCCCC111111. */ +{ "seti", 0x262F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }}, + +/* seti u6 00100110011011110000uuuuuu111111. */ +{ "seti", 0x266F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }}, + +/* seti limm 00100110001011110000111110111111. */ +{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }}, + +/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */ +{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setle<.f> 0,b,c 00100bbb00111110FBBBCCCCCC111110. */ +{ "setle", 0x203E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setle<.f><.cc> b,b,c 00100bbb11111110FBBBCCCCCC0QQQQQ. */ +{ "setle", 0x20FE0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setle<.f> a,b,u6 00100bbb01111110FBBBuuuuuuAAAAAA. */ +{ "setle", 0x207E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setle<.f> 0,b,u6 00100bbb01111110FBBBuuuuuu111110. */ +{ "setle", 0x207E003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setle<.f><.cc> b,b,u6 00100bbb11111110FBBBuuuuuu1QQQQQ. */ +{ "setle", 0x20FE0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setle<.f> b,b,s12 00100bbb10111110FBBBssssssSSSSSS. */ +{ "setle", 0x20BE0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setle<.f> a,limm,c 0010011000111110F111CCCCCCAAAAAA. */ +{ "setle", 0x263E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setle<.f> a,b,limm 00100bbb00111110FBBB111110AAAAAA. */ +{ "setle", 0x203E0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setle<.f> 0,limm,c 0010011000111110F111CCCCCC111110. */ +{ "setle", 0x263E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setle<.f> 0,b,limm 00100bbb00111110FBBB111110111110. */ +{ "setle", 0x203E0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setle<.f><.cc> b,b,limm 00100bbb11111110FBBB1111100QQQQQ. */ +{ "setle", 0x20FE0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setle<.f><.cc> 0,limm,c 0010011011111110F111CCCCCC0QQQQQ. */ +{ "setle", 0x26FE7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setle<.f> a,limm,u6 0010011001111110F111uuuuuuAAAAAA. */ +{ "setle", 0x267E7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setle<.f> 0,limm,u6 0010011001111110F111uuuuuu111110. */ +{ "setle", 0x267E703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setle<.f><.cc> 0,limm,u6 0010011011111110F111uuuuuu1QQQQQ. */ +{ "setle", 0x26FE7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setle<.f> 0,limm,s12 0010011010111110F111ssssssSSSSSS. */ +{ "setle", 0x26BE7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setle<.f> a,limm,limm 0010011000111110F111111110AAAAAA. */ +{ "setle", 0x263E7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setle<.f> 0,limm,limm 0010011000111110F111111110111110. */ +{ "setle", 0x263E7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setle<.f><.cc> 0,limm,limm 0010011011111110F1111111100QQQQQ. */ +{ "setle", 0x26FE7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setlo<.f> a,b,c 00100bbb00111100FBBBCCCCCCAAAAAA. */ +{ "setlo", 0x203C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setlo<.f> 0,b,c 00100bbb00111100FBBBCCCCCC111110. */ +{ "setlo", 0x203C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setlo<.f><.cc> b,b,c 00100bbb11111100FBBBCCCCCC0QQQQQ. */ +{ "setlo", 0x20FC0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setlo<.f> a,b,u6 00100bbb01111100FBBBuuuuuuAAAAAA. */ +{ "setlo", 0x207C0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setlo<.f> 0,b,u6 00100bbb01111100FBBBuuuuuu111110. */ +{ "setlo", 0x207C003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setlo<.f><.cc> b,b,u6 00100bbb11111100FBBBuuuuuu1QQQQQ. */ +{ "setlo", 0x20FC0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setlo<.f> b,b,s12 00100bbb10111100FBBBssssssSSSSSS. */ +{ "setlo", 0x20BC0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setlo<.f> a,limm,c 0010011000111100F111CCCCCCAAAAAA. */ +{ "setlo", 0x263C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setlo<.f> a,b,limm 00100bbb00111100FBBB111110AAAAAA. */ +{ "setlo", 0x203C0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setlo<.f> 0,limm,c 0010011000111100F111CCCCCC111110. */ +{ "setlo", 0x263C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setlo<.f> 0,b,limm 00100bbb00111100FBBB111110111110. */ +{ "setlo", 0x203C0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setlo<.f><.cc> b,b,limm 00100bbb11111100FBBB1111100QQQQQ. */ +{ "setlo", 0x20FC0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setlo<.f><.cc> 0,limm,c 0010011011111100F111CCCCCC0QQQQQ. */ +{ "setlo", 0x26FC7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setlo<.f> a,limm,u6 0010011001111100F111uuuuuuAAAAAA. */ +{ "setlo", 0x267C7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setlo<.f> 0,limm,u6 0010011001111100F111uuuuuu111110. */ +{ "setlo", 0x267C703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setlo<.f><.cc> 0,limm,u6 0010011011111100F111uuuuuu1QQQQQ. */ +{ "setlo", 0x26FC7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setlo<.f> 0,limm,s12 0010011010111100F111ssssssSSSSSS. */ +{ "setlo", 0x26BC7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setlo<.f> a,limm,limm 0010011000111100F111111110AAAAAA. */ +{ "setlo", 0x263C7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setlo<.f> 0,limm,limm 0010011000111100F111111110111110. */ +{ "setlo", 0x263C7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setlo<.f><.cc> 0,limm,limm 0010011011111100F1111111100QQQQQ. */ +{ "setlo", 0x26FC7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setlt<.f> a,b,c 00100bbb00111010FBBBCCCCCCAAAAAA. */ +{ "setlt", 0x203A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setlt<.f> 0,b,c 00100bbb00111010FBBBCCCCCC111110. */ +{ "setlt", 0x203A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setlt<.f><.cc> b,b,c 00100bbb11111010FBBBCCCCCC0QQQQQ. */ +{ "setlt", 0x20FA0000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setlt<.f> a,b,u6 00100bbb01111010FBBBuuuuuuAAAAAA. */ +{ "setlt", 0x207A0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setlt<.f> 0,b,u6 00100bbb01111010FBBBuuuuuu111110. */ +{ "setlt", 0x207A003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setlt<.f><.cc> b,b,u6 00100bbb11111010FBBBuuuuuu1QQQQQ. */ +{ "setlt", 0x20FA0020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setlt<.f> b,b,s12 00100bbb10111010FBBBssssssSSSSSS. */ +{ "setlt", 0x20BA0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setlt<.f> a,limm,c 0010011000111010F111CCCCCCAAAAAA. */ +{ "setlt", 0x263A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setlt<.f> a,b,limm 00100bbb00111010FBBB111110AAAAAA. */ +{ "setlt", 0x203A0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setlt<.f> 0,limm,c 0010011000111010F111CCCCCC111110. */ +{ "setlt", 0x263A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setlt<.f> 0,b,limm 00100bbb00111010FBBB111110111110. */ +{ "setlt", 0x203A0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setlt<.f><.cc> b,b,limm 00100bbb11111010FBBB1111100QQQQQ. */ +{ "setlt", 0x20FA0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setlt<.f><.cc> 0,limm,c 0010011011111010F111CCCCCC0QQQQQ. */ +{ "setlt", 0x26FA7000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setlt<.f> a,limm,u6 0010011001111010F111uuuuuuAAAAAA. */ +{ "setlt", 0x267A7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setlt<.f> 0,limm,u6 0010011001111010F111uuuuuu111110. */ +{ "setlt", 0x267A703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setlt<.f><.cc> 0,limm,u6 0010011011111010F111uuuuuu1QQQQQ. */ +{ "setlt", 0x26FA7020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setlt<.f> 0,limm,s12 0010011010111010F111ssssssSSSSSS. */ +{ "setlt", 0x26BA7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setlt<.f> a,limm,limm 0010011000111010F111111110AAAAAA. */ +{ "setlt", 0x263A7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setlt<.f> 0,limm,limm 0010011000111010F111111110111110. */ +{ "setlt", 0x263A7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setlt<.f><.cc> 0,limm,limm 0010011011111010F1111111100QQQQQ. */ +{ "setlt", 0x26FA7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setne<.f> a,b,c 00100bbb00111001FBBBCCCCCCAAAAAA. */ +{ "setne", 0x20390000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setne<.f> 0,b,c 00100bbb00111001FBBBCCCCCC111110. */ +{ "setne", 0x2039003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setne<.f><.cc> b,b,c 00100bbb11111001FBBBCCCCCC0QQQQQ. */ +{ "setne", 0x20F90000, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setne<.f> a,b,u6 00100bbb01111001FBBBuuuuuuAAAAAA. */ +{ "setne", 0x20790000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setne<.f> 0,b,u6 00100bbb01111001FBBBuuuuuu111110. */ +{ "setne", 0x2079003E, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setne<.f><.cc> b,b,u6 00100bbb11111001FBBBuuuuuu1QQQQQ. */ +{ "setne", 0x20F90020, 0xF8FF0020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setne<.f> b,b,s12 00100bbb10111001FBBBssssssSSSSSS. */ +{ "setne", 0x20B90000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setne<.f> a,limm,c 0010011000111001F111CCCCCCAAAAAA. */ +{ "setne", 0x26397000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setne<.f> a,b,limm 00100bbb00111001FBBB111110AAAAAA. */ +{ "setne", 0x20390F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setne<.f> 0,limm,c 0010011000111001F111CCCCCC111110. */ +{ "setne", 0x2639703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setne<.f> 0,b,limm 00100bbb00111001FBBB111110111110. */ +{ "setne", 0x20390FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setne<.f><.cc> b,b,limm 00100bbb11111001FBBB1111100QQQQQ. */ +{ "setne", 0x20F90F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setne<.f><.cc> 0,limm,c 0010011011111001F111CCCCCC0QQQQQ. */ +{ "setne", 0x26F97000, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setne<.f> a,limm,u6 0010011001111001F111uuuuuuAAAAAA. */ +{ "setne", 0x26797000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setne<.f> 0,limm,u6 0010011001111001F111uuuuuu111110. */ +{ "setne", 0x2679703E, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setne<.f><.cc> 0,limm,u6 0010011011111001F111uuuuuu1QQQQQ. */ +{ "setne", 0x26F97020, 0xFFFF7020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setne<.f> 0,limm,s12 0010011010111001F111ssssssSSSSSS. */ +{ "setne", 0x26B97000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setne<.f> a,limm,limm 0010011000111001F111111110AAAAAA. */ +{ "setne", 0x26397F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setne<.f> 0,limm,limm 0010011000111001F111111110111110. */ +{ "setne", 0x26397FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setne<.f><.cc> 0,limm,limm 0010011011111001F1111111100QQQQQ. */ +{ "setne", 0x26F97F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* setcc<.f> a,b,c 00100bbb00iiiiiiFBBBCCCCCCAAAAAA. */ +{ "setcc", 0x20000000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, RC }, { C_F }}, + +/* setcc<.f> 0,b,c 00100bbb00iiiiiiFBBBCCCCCC111110. */ +{ "setcc", 0x2000003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, RC }, { C_F }}, + +/* setcc<.f><.cc> b,b,c 00100bbb11iiiiiiFBBBCCCCCC0QQQQQ. */ +{ "setcc", 0x20C00000, 0xF8C00020, 0, LOGICAL, CD1, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* setcc<.f> a,b,u6 00100bbb01iiiiiiFBBBuuuuuuAAAAAA. */ +{ "setcc", 0x20400000, 0xF8C00000, 0, LOGICAL, CD1, { RA, RB, UIMM6_20 }, { C_F }}, + +/* setcc<.f> 0,b,u6 00100bbb01iiiiiiFBBBuuuuuu111110. */ +{ "setcc", 0x2040003E, 0xF8C0003F, 0, LOGICAL, CD1, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* setcc<.f><.cc> b,b,u6 00100bbb11iiiiiiFBBBuuuuuu1QQQQQ. */ +{ "setcc", 0x20C00020, 0xF8C00020, 0, LOGICAL, CD1, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* setcc<.f> b,b,s12 00100bbb10iiiiiiFBBBssssssSSSSSS. */ +{ "setcc", 0x20800000, 0xF8C00000, 0, LOGICAL, CD1, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* setcc<.f> a,limm,c 0010011000iiiiiiF111CCCCCCAAAAAA. */ +{ "setcc", 0x26007000, 0xFFC07000, 0, LOGICAL, CD1, { RA, LIMM, RC }, { C_F }}, + +/* setcc<.f> a,b,limm 00100bbb00iiiiiiFBBB111110AAAAAA. */ +{ "setcc", 0x20000F80, 0xF8C00FC0, 0, LOGICAL, CD1, { RA, RB, LIMM }, { C_F }}, + +/* setcc<.f> 0,limm,c 0010011000iiiiiiF111CCCCCC111110. */ +{ "setcc", 0x2600703E, 0xFFC0703F, 0, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F }}, + +/* setcc<.f> 0,b,limm 00100bbb00iiiiiiFBBB111110111110. */ +{ "setcc", 0x20000FBE, 0xF8C00FFF, 0, LOGICAL, CD1, { ZA, RB, LIMM }, { C_F }}, + +/* setcc<.f><.cc> b,b,limm 00100bbb11iiiiiiFBBB1111100QQQQQ. */ +{ "setcc", 0x20C00F80, 0xF8C00FE0, 0, LOGICAL, CD1, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* setcc<.f><.cc> 0,limm,c 0010011011iiiiiiF111CCCCCC0QQQQQ. */ +{ "setcc", 0x26C07000, 0xFFC07020, 0, LOGICAL, CD1, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* setcc<.f> a,limm,u6 0010011001iiiiiiF111uuuuuuAAAAAA. */ +{ "setcc", 0x26407000, 0xFFC07000, 0, LOGICAL, CD1, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* setcc<.f> 0,limm,u6 0010011001iiiiiiF111uuuuuu111110. */ +{ "setcc", 0x2640703E, 0xFFC0703F, 0, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* setcc<.f><.cc> 0,limm,u6 0010011011iiiiiiF111uuuuuu1QQQQQ. */ +{ "setcc", 0x26C07020, 0xFFC07020, 0, LOGICAL, CD1, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* setcc<.f> 0,limm,s12 0010011010iiiiiiF111ssssssSSSSSS. */ +{ "setcc", 0x26807000, 0xFFC07000, 0, LOGICAL, CD1, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* setcc<.f> a,limm,limm 0010011000iiiiiiF111111110AAAAAA. */ +{ "setcc", 0x26007F80, 0xFFC07FC0, 0, LOGICAL, CD1, { RA, LIMM, LIMMdup }, { C_F }}, + +/* setcc<.f> 0,limm,limm 0010011000iiiiiiF111111110111110. */ +{ "setcc", 0x26007FBE, 0xFFC07FFF, 0, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* setcc<.f><.cc> 0,limm,limm 0010011011iiiiiiF1111111100QQQQQ. */ +{ "setcc", 0x26C07F80, 0xFFC07FE0, 0, LOGICAL, CD1, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* sexb<.f> b,c 00100bbb00101111FBBBCCCCCC000101. */ +{ "sexb", 0x202F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, + +/* sexb<.f> 0,c 0010011000101111F111CCCCCC000101. */ +{ "sexb", 0x262F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* sexb<.f> b,u6 00100bbb01101111FBBBuuuuuu000101. */ +{ "sexb", 0x206F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* sexb<.f> 0,u6 0010011001101111F111uuuuuu000101. */ +{ "sexb", 0x266F7005, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* sexb<.f> b,limm 00100bbb00101111FBBB111110000101. */ +{ "sexb", 0x202F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* sexb<.f> 0,limm 0010011000101111F111111110000101. */ +{ "sexb", 0x262F7F85, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* sexb_s b,c 01111bbbccc01101. */ +{ "sexb_s", 0x0000780D, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* sexh<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ +{ "sexh", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, + +/* sexh<.f> 0,c 0010011000101111F111CCCCCC000110. */ +{ "sexh", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* sexh<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ +{ "sexh", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* sexh<.f> 0,u6 0010011001101111F111uuuuuu000110. */ +{ "sexh", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* sexh<.f> b,limm 00100bbb00101111FBBB111110000110. */ +{ "sexh", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* sexh<.f> 0,limm 0010011000101111F111111110000110. */ +{ "sexh", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* sexh_s b,c 01111bbbccc01110. */ +{ "sexh_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* sexw<.f> b,c 00100bbb00101111FBBBCCCCCC000110. */ +{ "sexw", 0x202F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, + +/* sexw<.f> 0,c 0010011000101111F111CCCCCC000110. */ +{ "sexw", 0x262F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RC }, { C_F }}, + +/* sexw<.f> b,u6 00100bbb01101111FBBBuuuuuu000110. */ +{ "sexw", 0x206F0006, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* sexw<.f> 0,u6 0010011001101111F111uuuuuu000110. */ +{ "sexw", 0x266F7006, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* sexw<.f> b,limm 00100bbb00101111FBBB111110000110. */ +{ "sexw", 0x202F0F86, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, + +/* sexw<.f> 0,limm 0010011000101111F111111110000110. */ +{ "sexw", 0x262F7F86, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM }, { C_F }}, + +/* sexw_s b,c 01111bbbccc01110. */ +{ "sexw_s", 0x0000780E, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB_S, RC_S }, { 0 }}, + +/* sfxtr<.f> a,b,c 00110bbb00101001FBBBCCCCCCAAAAAA. */ +{ "sfxtr", 0x30290000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,c 00110bbb11101001FBBBCCCCCC0QQQQQ. */ +{ "sfxtr", 0x30E90000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sfxtr<.f> a,b,u6 00110bbb01101001FBBBuuuuuuAAAAAA. */ +{ "sfxtr", 0x30690000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,u6 00110bbb11101001FBBBuuuuuu1QQQQQ. */ +{ "sfxtr", 0x30E90020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sfxtr<.f> b,b,s12 00110bbb10101001FBBBssssssSSSSSS. */ +{ "sfxtr", 0x30A90000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sfxtr<.f> a,limm,c 0011011000101001F111CCCCCCAAAAAA. */ +{ "sfxtr", 0x36297000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sfxtr<.f> a,b,limm 00110bbb00101001FBBB111110AAAAAA. */ +{ "sfxtr", 0x30290F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sfxtr<.f><.cc> b,b,limm 00110bbb11101001FBBB1111100QQQQQ. */ +{ "sfxtr", 0x30E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sleep c 00100001001011110000CCCCCC111111. */ +{ "sleep", 0x212F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }}, + +/* sleep u6 00100001011011110000uuuuuu111111. */ +{ "sleep", 0x216F003F, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }}, + +/* sleep limm 00100001001011110000111110111111. */ +{ "sleep", 0x212F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { LIMM }, { 0 }}, + +/* sqrtacc c 00101010001011110000CCCCCC111111. */ +{ "sqrtacc", 0x2A2F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RC }, { 0 }}, + +/* sqrtacc u6 00101010011011110000uuuuuu111111. */ +{ "sqrtacc", 0x2A6F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { UIMM6_20 }, { 0 }}, + +/* sr b,c 00100bbb001010110BBBCCCCCCRRRRRR. */ +{ "sr", 0x202B0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* sr b,c 00100bbb00101011RBBBCCCCCCRRRRRR. */ +{ "sr", 0x202B0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* sr b,u6 00100bbb011010110BBBuuuuuu000000. */ +{ "sr", 0x206B0000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* sr b,u6 00100bbb01101011RBBBuuuuuu000000. */ +{ "sr", 0x206B0000, 0xF8FF003F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* sr b,s12 00100bbb101010110BBBssssssSSSSSS. */ +{ "sr", 0x20AB0000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* sr b,s12 00100bbb10101011RBBBssssssSSSSSS. */ +{ "sr", 0x20AB0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* sr limm,c 00100110001010110111CCCCCCRRRRRR. */ +{ "sr", 0x262B7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* sr b,limm 00100bbb001010110BBB111110RRRRRR. */ +{ "sr", 0x202B0F80, 0xF8FF8FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* sr limm,c 0010011000101011R111CCCCCCRRRRRR. */ +{ "sr", 0x262B7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, RC, BRAKETdup }, { 0 }}, + +/* sr b,limm 00100bbb00101011RBBB111110RRRRRR. */ +{ "sr", 0x202B0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { 0 }}, + +/* sr limm,u6 00100110011010110111uuuuuu000000. */ +{ "sr", 0x266B7000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* sr limm,u6 0010011001101011R111uuuuuu000000. */ +{ "sr", 0x266B7000, 0xFFFF703F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, UIMM6_20, BRAKETdup }, { 0 }}, + +/* sr limm,s12 00100110101010110111ssssssSSSSSS. */ +{ "sr", 0x26AB7000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* sr limm,s12 0010011010101011R111ssssssSSSSSS. */ +{ "sr", 0x26AB7000, 0xFFFF7000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, SIMM12_20, BRAKETdup }, { 0 }}, + +/* sr limm,limm 00100110001010110111111110RRRRRR. */ +{ "sr", 0x262B7F80, 0xFFFFFFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }}, + +/* sr limm,limm 0010011000101011R111111110RRRRRR. */ +{ "sr", 0x262B7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, AUXREG, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { 0 }}, + +/* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZR. */ +{ "st", 0x18000000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> c,b 00011bbb000000000BBBCCCCCCDaaZZ0. */ +{ "st", 0x18000000, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> w6,b 00011bbb000000000BBBwwwwwwDaaZZ1. */ +{ "st", 0x18000001, 0xF8FF8001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZR. */ +{ "st", 0x18000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> c,b,s9 00011bbbssssssssSBBBCCCCCCDaaZZ0. */ +{ "st", 0x18000000, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaaZZ1. */ +{ "st", 0x18000001, 0xF8000001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZR. */ +{ "st", 0x1E007000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di><zz> c,limm 00011110000000000111CCCCCCDRRZZ0. */ +{ "st", 0x1E007000, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di><zz> w6,limm 00011110000000000111wwwwwwDRRZZ1. */ +{ "st", 0x1E007001, 0xFFFFF001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_ZZ29, C_DI26 }}, + +/* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZR. */ +{ "st", 0x18000F80, 0xF8000FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> limm,b,s9 00011bbbssssssssSBBB111110DaaZZ0. */ +{ "st", 0x18000F80, 0xF8000FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> w6,limm,s9 00011110ssssssssS111wwwwwwDaaZZ1. */ +{ "st", 0x1E007001, 0xFF007001, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZR. */ +{ "st", 0x1E007F80, 0xFF007FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* st<.di><.aa><zz> limm,limm,s9 00011110ssssssssS111111110DaaZZ0. */ +{ "st", 0x1E007F80, 0xFF007FC1, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_ZZ29, C_DI26, C_AA27 }}, + +/* stb_s c,b,u5 10101bbbcccuuuuu. */ +{ "stb_s", 0x0000A800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM5_11_S, BRAKETdup }, { 0 }}, + +/* stb_s b,SP,u7 11000bbb011uuuuu. */ +{ "stb_s", 0x0000C060, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* std<.di><.aa> c,b 00011bbb000000000BBBCCCCCCDaa110. */ +{ "std", 0x18000006, 0xF8FF8007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di><.aa> w6,b 00011bbb000000000BBBwwwwwwDaa111. */ +{ "std", 0x18000007, 0xF8FF8007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di><.aa> c,b,s9 00011bbbssssssssSBBBCCCCCCDaa110. */ +{ "std", 0x18000006, 0xF8000007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di><.aa> w6,b,s9 00011bbbssssssssSBBBwwwwwwDaa111. */ +{ "std", 0x18000007, 0xF8000007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di> c,limm 00011110000000000111CCCCCCDRR110. */ +{ "std", 0x1E007006, 0xFFFFF007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RCD, BRAKET, LIMM, BRAKETdup }, { C_DI26 }}, + +/* std<.di> w6,limm 00011110000000000111wwwwwwDRR111. */ +{ "std", 0x1E007007, 0xFFFFF007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, BRAKETdup }, { C_DI26 }}, + +/* std<.di><.aa> limm,b,s9 00011bbbssssssssSBBB111110Daa110. */ +{ "std", 0x18000F86, 0xF8000FC7, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di><.aa> w6,limm,s9 00011110ssssssssS111wwwwwwDaa111. */ +{ "std", 0x1E007007, 0xFF007007, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { W6, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* std<.di><.aa> limm,limm,s9 00011110ssssssssS111111110Daa110. */ +{ "std", 0x1E007F86, 0xFF007FC7, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, SIMM9_8, BRAKETdup }, { C_DI26, C_AA27 }}, + +/* sth_s c,b,u6 10110bbbcccuuuuu. */ +{ "sth_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, + +/* stm a,u6,b 00101bbb01001101RBBBRuuuuuAAAAAA. */ +{ "stm", 0x284D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, RB }, { 0 }}, + +/* stm 0,u6,b 00101bbb01001101RBBBRuuuuu111110. */ +{ "stm", 0x284D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, RB }, { 0 }}, + +/* stm a,u6,limm 0010111001001101R111RuuuuuAAAAAA. */ +{ "stm", 0x2E4D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RA, UIMM6_A16_21, LIMM }, { 0 }}, + +/* stm 0,u6,limm 0010111001001101R111Ruuuuu111110. */ +{ "stm", 0x2E4D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { ZA, UIMM6_A16_21, LIMM }, { 0 }}, + +/* stw_s c,b,u6 10110bbbcccuuuuu. */ +{ "stw_s", 0x0000B000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM6_A16_11_S, BRAKETdup }, { 0 }}, + +/* st_s b,SP,u7 11000bbb010uuuuu. */ +{ "st_s", 0x0000C040, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB_S, BRAKET, SP_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* st_s c,b,u7 10100bbbcccuuuuu. */ +{ "st_s", 0x0000A000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }}, + +/* st_s R0,GP,s11 01010SSSSSS10sss. */ +{ "st_s", 0x00005010, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, CD2, { R0_S, BRAKET, GP_S, SIMM11_A32_13_S, BRAKETdup }, { 0 }}, + +/* sub<.f> a,b,c 00100bbb00000010FBBBCCCCCCAAAAAA. */ +{ "sub", 0x20020000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sub<.f> 0,b,c 00100bbb00000010FBBBCCCCCC111110. */ +{ "sub", 0x2002003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* sub<.f><.cc> b,b,c 00100bbb11000010FBBBCCCCCC0QQQQQ. */ +{ "sub", 0x20C20000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */ +{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sub<.f> 0,b,u6 00100bbb01000010FBBBuuuuuu111110. */ +{ "sub", 0x2042003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* sub<.f><.cc> b,b,u6 00100bbb11000010FBBBuuuuuu1QQQQQ. */ +{ "sub", 0x20C20020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sub<.f> b,b,s12 00100bbb10000010FBBBssssssSSSSSS. */ +{ "sub", 0x20820000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sub<.f> a,limm,c 0010011000000010F111CCCCCCAAAAAA. */ +{ "sub", 0x26027000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */ +{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sub<.f> 0,limm,c 0010011000000010F111CCCCCC111110. */ +{ "sub", 0x2602703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* sub<.f> 0,b,limm 00100bbb00000010FBBB111110111110. */ +{ "sub", 0x20020FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* sub<.f><.cc> b,b,limm 00100bbb11000010FBBB1111100QQQQQ. */ +{ "sub", 0x20C20F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sub<.f><.cc> 0,limm,c 0010011011000010F111CCCCCC0QQQQQ. */ +{ "sub", 0x26C27000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* sub<.f> a,limm,u6 0010011001000010F111uuuuuuAAAAAA. */ +{ "sub", 0x26427000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub<.f> 0,limm,u6 0010011001000010F111uuuuuu111110. */ +{ "sub", 0x2642703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub<.f><.cc> 0,limm,u6 0010011011000010F111uuuuuu1QQQQQ. */ +{ "sub", 0x26C27020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* sub<.f> 0,limm,s12 0010011010000010F111ssssssSSSSSS. */ +{ "sub", 0x26827000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* sub<.f> a,limm,limm 0010011000000010F111111110AAAAAA. */ +{ "sub", 0x26027F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* sub<.f> 0,limm,limm 0010011000000010F111111110111110. */ +{ "sub", 0x26027FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* sub<.f><.cc> 0,limm,limm 0010011011000010F1111111100QQQQQ. */ +{ "sub", 0x26C27F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* sub1<.f> a,b,c 00100bbb00010111FBBBCCCCCCAAAAAA. */ +{ "sub1", 0x20170000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sub1<.f> 0,b,c 00100bbb00010111FBBBCCCCCC111110. */ +{ "sub1", 0x2017003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* sub1<.f><.cc> b,b,c 00100bbb11010111FBBBCCCCCC0QQQQQ. */ +{ "sub1", 0x20D70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sub1<.f> a,b,u6 00100bbb01010111FBBBuuuuuuAAAAAA. */ +{ "sub1", 0x20570000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sub1<.f> 0,b,u6 00100bbb01010111FBBBuuuuuu111110. */ +{ "sub1", 0x2057003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* sub1<.f><.cc> b,b,u6 00100bbb11010111FBBBuuuuuu1QQQQQ. */ +{ "sub1", 0x20D70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sub1<.f> b,b,s12 00100bbb10010111FBBBssssssSSSSSS. */ +{ "sub1", 0x20970000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sub1<.f> a,limm,c 0010011000010111F111CCCCCCAAAAAA. */ +{ "sub1", 0x26177000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sub1<.f> a,b,limm 00100bbb00010111FBBB111110AAAAAA. */ +{ "sub1", 0x20170F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sub1<.f> 0,limm,c 0010011000010111F111CCCCCC111110. */ +{ "sub1", 0x2617703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* sub1<.f> 0,b,limm 00100bbb00010111FBBB111110111110. */ +{ "sub1", 0x20170FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* sub1<.f><.cc> b,b,limm 00100bbb11010111FBBB1111100QQQQQ. */ +{ "sub1", 0x20D70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sub1<.f><.cc> 0,limm,c 0010011011010111F111CCCCCC0QQQQQ. */ +{ "sub1", 0x26D77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* sub1<.f> a,limm,u6 0010011001010111F111uuuuuuAAAAAA. */ +{ "sub1", 0x26577000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub1<.f> 0,limm,u6 0010011001010111F111uuuuuu111110. */ +{ "sub1", 0x2657703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub1<.f><.cc> 0,limm,u6 0010011011010111F111uuuuuu1QQQQQ. */ +{ "sub1", 0x26D77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* sub1<.f> 0,limm,s12 0010011010010111F111ssssssSSSSSS. */ +{ "sub1", 0x26977000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* sub1<.f> a,limm,limm 0010011000010111F111111110AAAAAA. */ +{ "sub1", 0x26177F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* sub1<.f> 0,limm,limm 0010011000010111F111111110111110. */ +{ "sub1", 0x26177FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* sub1<.f><.cc> 0,limm,limm 0010011011010111F1111111100QQQQQ. */ +{ "sub1", 0x26D77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* sub2<.f> a,b,c 00100bbb00011000FBBBCCCCCCAAAAAA. */ +{ "sub2", 0x20180000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sub2<.f> 0,b,c 00100bbb00011000FBBBCCCCCC111110. */ +{ "sub2", 0x2018003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* sub2<.f><.cc> b,b,c 00100bbb11011000FBBBCCCCCC0QQQQQ. */ +{ "sub2", 0x20D80000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sub2<.f> a,b,u6 00100bbb01011000FBBBuuuuuuAAAAAA. */ +{ "sub2", 0x20580000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sub2<.f> 0,b,u6 00100bbb01011000FBBBuuuuuu111110. */ +{ "sub2", 0x2058003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* sub2<.f><.cc> b,b,u6 00100bbb11011000FBBBuuuuuu1QQQQQ. */ +{ "sub2", 0x20D80020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sub2<.f> b,b,s12 00100bbb10011000FBBBssssssSSSSSS. */ +{ "sub2", 0x20980000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sub2<.f> a,limm,c 0010011000011000F111CCCCCCAAAAAA. */ +{ "sub2", 0x26187000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sub2<.f> a,b,limm 00100bbb00011000FBBB111110AAAAAA. */ +{ "sub2", 0x20180F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sub2<.f> 0,limm,c 0010011000011000F111CCCCCC111110. */ +{ "sub2", 0x2618703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* sub2<.f> 0,b,limm 00100bbb00011000FBBB111110111110. */ +{ "sub2", 0x20180FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* sub2<.f><.cc> b,b,limm 00100bbb11011000FBBB1111100QQQQQ. */ +{ "sub2", 0x20D80F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sub2<.f><.cc> 0,limm,c 0010011011011000F111CCCCCC0QQQQQ. */ +{ "sub2", 0x26D87000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* sub2<.f> a,limm,u6 0010011001011000F111uuuuuuAAAAAA. */ +{ "sub2", 0x26587000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub2<.f> 0,limm,u6 0010011001011000F111uuuuuu111110. */ +{ "sub2", 0x2658703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub2<.f><.cc> 0,limm,u6 0010011011011000F111uuuuuu1QQQQQ. */ +{ "sub2", 0x26D87020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* sub2<.f> 0,limm,s12 0010011010011000F111ssssssSSSSSS. */ +{ "sub2", 0x26987000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* sub2<.f> a,limm,limm 0010011000011000F111111110AAAAAA. */ +{ "sub2", 0x26187F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* sub2<.f> 0,limm,limm 0010011000011000F111111110111110. */ +{ "sub2", 0x26187FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* sub2<.f><.cc> 0,limm,limm 0010011011011000F1111111100QQQQQ. */ +{ "sub2", 0x26D87F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* sub3<.f> a,b,c 00100bbb00011001FBBBCCCCCCAAAAAA. */ +{ "sub3", 0x20190000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* sub3<.f> 0,b,c 00100bbb00011001FBBBCCCCCC111110. */ +{ "sub3", 0x2019003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* sub3<.f><.cc> b,b,c 00100bbb11011001FBBBCCCCCC0QQQQQ. */ +{ "sub3", 0x20D90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* sub3<.f> a,b,u6 00100bbb01011001FBBBuuuuuuAAAAAA. */ +{ "sub3", 0x20590000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* sub3<.f> 0,b,u6 00100bbb01011001FBBBuuuuuu111110. */ +{ "sub3", 0x2059003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* sub3<.f><.cc> b,b,u6 00100bbb11011001FBBBuuuuuu1QQQQQ. */ +{ "sub3", 0x20D90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* sub3<.f> b,b,s12 00100bbb10011001FBBBssssssSSSSSS. */ +{ "sub3", 0x20990000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* sub3<.f> a,limm,c 0010011000011001F111CCCCCCAAAAAA. */ +{ "sub3", 0x26197000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* sub3<.f> a,b,limm 00100bbb00011001FBBB111110AAAAAA. */ +{ "sub3", 0x20190F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* sub3<.f> 0,limm,c 0010011000011001F111CCCCCC111110. */ +{ "sub3", 0x2619703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* sub3<.f> 0,b,limm 00100bbb00011001FBBB111110111110. */ +{ "sub3", 0x20190FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* sub3<.f><.cc> b,b,limm 00100bbb11011001FBBB1111100QQQQQ. */ +{ "sub3", 0x20D90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* sub3<.f><.cc> 0,limm,c 0010011011011001F111CCCCCC0QQQQQ. */ +{ "sub3", 0x26D97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* sub3<.f> a,limm,u6 0010011001011001F111uuuuuuAAAAAA. */ +{ "sub3", 0x26597000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub3<.f> 0,limm,u6 0010011001011001F111uuuuuu111110. */ +{ "sub3", 0x2659703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* sub3<.f><.cc> 0,limm,u6 0010011011011001F111uuuuuu1QQQQQ. */ +{ "sub3", 0x26D97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* sub3<.f> 0,limm,s12 0010011010011001F111ssssssSSSSSS. */ +{ "sub3", 0x26997000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* sub3<.f> a,limm,limm 0010011000011001F111111110AAAAAA. */ +{ "sub3", 0x26197F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* sub3<.f> 0,limm,limm 0010011000011001F111111110111110. */ +{ "sub3", 0x26197FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* sub3<.f><.cc> 0,limm,limm 0010011011011001F1111111100QQQQQ. */ +{ "sub3", 0x26D97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* subs<.f> a,b,c 00101bbb00000111FBBBCCCCCCAAAAAA. */ +{ "subs", 0x28070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* subs<.f> 0,b,c 00101bbb00000111FBBBCCCCCC111110. */ +{ "subs", 0x2807003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* subs<.f><.cc> b,b,c 00101bbb11000111FBBBCCCCCC0QQQQQ. */ +{ "subs", 0x28C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* subs<.f> a,b,u6 00101bbb01000111FBBBuuuuuuAAAAAA. */ +{ "subs", 0x28470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* subs<.f> 0,b,u6 00101bbb01000111FBBBuuuuuu111110. */ +{ "subs", 0x2847003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* subs<.f><.cc> b,b,u6 00101bbb11000111FBBBuuuuuu1QQQQQ. */ +{ "subs", 0x28C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* subs<.f> b,b,s12 00101bbb10000111FBBBssssssSSSSSS. */ +{ "subs", 0x28870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ +{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* subs<.f> a,b,limm 00101bbb00000111FBBB111110AAAAAA. */ +{ "subs", 0x28070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* subs<.f> 0,limm,c 0010111000000111F111CCCCCC111110. */ +{ "subs", 0x2E07703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* subs<.f> 0,b,limm 00101bbb00000111FBBB111110111110. */ +{ "subs", 0x28070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* subs<.f> a,limm,c 0010111000000111F111CCCCCCAAAAAA. */ +{ "subs", 0x2E077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* subs<.f><.cc> b,b,limm 00101bbb11000111FBBB1111100QQQQQ. */ +{ "subs", 0x28C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* subs<.f><.cc> 0,limm,c 0010111011000111F111CCCCCC0QQQQQ. */ +{ "subs", 0x2EC77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* subs<.f> a,limm,u6 0010111001000111F111uuuuuuAAAAAA. */ +{ "subs", 0x2E477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* subs<.f> 0,limm,u6 0010111001000111F111uuuuuu111110. */ +{ "subs", 0x2E47703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* subs<.f><.cc> 0,limm,u6 0010111011000111F111uuuuuu1QQQQQ. */ +{ "subs", 0x2EC77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* subs<.f> 0,limm,s12 0010111010000111F111ssssssSSSSSS. */ +{ "subs", 0x2E877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* subs<.f> a,limm,limm 0010111000000111F111111110AAAAAA. */ +{ "subs", 0x2E077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* subs<.f> 0,limm,limm 0010111000000111F111111110111110. */ +{ "subs", 0x2E077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* subs<.f><.cc> 0,limm,limm 0010111011000111F1111111100QQQQQ. */ +{ "subs", 0x2EC77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* subsdw<.f> a,b,c 00101bbb00101001FBBBCCCCCCAAAAAA. */ +{ "subsdw", 0x28290000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* subsdw<.f> 0,b,c 00101bbb00101001FBBBCCCCCC111110. */ +{ "subsdw", 0x2829003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, RC }, { C_F }}, + +/* subsdw<.f><.cc> b,b,c 00101bbb11101001FBBBCCCCCC0QQQQQ. */ +{ "subsdw", 0x28E90000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* subsdw<.f> a,b,u6 00101bbb01101001FBBBuuuuuuAAAAAA. */ +{ "subsdw", 0x28690000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* subsdw<.f> 0,b,u6 00101bbb01101001FBBBuuuuuu111110. */ +{ "subsdw", 0x2869003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* subsdw<.f><.cc> b,b,u6 00101bbb11101001FBBBuuuuuu1QQQQQ. */ +{ "subsdw", 0x28E90020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* subsdw<.f> b,b,s12 00101bbb10101001FBBBssssssSSSSSS. */ +{ "subsdw", 0x28A90000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* subsdw<.f> a,limm,c 0010111000101001F111CCCCCCAAAAAA. */ +{ "subsdw", 0x2E297000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* subsdw<.f> a,b,limm 00101bbb00101001FBBB111110AAAAAA. */ +{ "subsdw", 0x28290F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* subsdw<.f> 0,limm,c 0010111000101001F111CCCCCC111110. */ +{ "subsdw", 0x2E29703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* subsdw<.f> 0,b,limm 00101bbb00101001FBBB111110111110. */ +{ "subsdw", 0x28290FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* subsdw<.f><.cc> b,b,limm 00101bbb11101001FBBB1111100QQQQQ. */ +{ "subsdw", 0x28E90F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* subsdw<.f><.cc> 0,limm,c 0010111011101001F111CCCCCC0QQQQQ. */ +{ "subsdw", 0x2EE97000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* subsdw<.f> a,limm,u6 0010111001101001F111uuuuuuAAAAAA. */ +{ "subsdw", 0x2E697000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* subsdw<.f> 0,limm,u6 0010111001101001F111uuuuuu111110. */ +{ "subsdw", 0x2E69703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* subsdw<.f><.cc> 0,limm,u6 0010111011101001F111uuuuuu1QQQQQ. */ +{ "subsdw", 0x2EE97020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* subsdw<.f> 0,limm,s12 0010111010101001F111ssssssSSSSSS. */ +{ "subsdw", 0x2EA97000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* subsdw<.f> a,limm,limm 0010111000101001F111111110AAAAAA. */ +{ "subsdw", 0x2E297F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* subsdw<.f> 0,limm,limm 0010111000101001F111111110111110. */ +{ "subsdw", 0x2E297FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* subsdw<.f><.cc> 0,limm,limm 0010111011101001F1111111100QQQQQ. */ +{ "subsdw", 0x2EE97F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* sub_s b,b,c 01111bbbccc00010. */ +{ "sub_s", 0x00007802, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* sub_s a,b,c 01001bbbccc10aaa. */ +{ "sub_s", 0x00004810, 0x0000F818, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, CD2, { RA_S, RB_S, RC_S }, { 0 }}, + +/* sub_s c,b,u3 01101bbbccc01uuu. */ +{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RC_S, RB_S, UIMM3_13_S }, { 0 }}, + +/* sub_s b,b,u5 10111bbb011uuuuu. */ +{ "sub_s", 0x0000B860, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }}, + +/* sub_s SP,SP,u7 11000001101uuuuu. */ +{ "sub_s", 0x0000C1A0, 0x0000FFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { SP_S, SP_Sdup, UIMM7_A32_11_S }, { 0 }}, + +/* sub_s.ne b,b,b 01111bbb11000000. */ +{ "sub_s", 0x000078C0, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RB_Sdup, RB_Sdup }, { C_NE }}, + +/* swap<.f> b,c 00101bbb00101111FBBBCCCCCC000000. */ +{ "swap", 0x282F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }}, + +/* swap<.f> 0,c 0010111000101111F111CCCCCC000000. */ +{ "swap", 0x2E2F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }}, + +/* swap<.f> b,u6 00101bbb01101111FBBBuuuuuu000000. */ +{ "swap", 0x286F0000, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }}, + +/* swap<.f> 0,u6 0010111001101111F111uuuuuu000000. */ +{ "swap", 0x2E6F7000, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }}, + +/* swap<.f> b,limm 00101bbb00101111FBBB111110000000. */ +{ "swap", 0x282F0F80, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }}, + +/* swap<.f> 0,limm 0010111000101111F111111110000000. */ +{ "swap", 0x2E2F7F80, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }}, + +/* swape<.f> b,c 00101bbb00101111FBBBCCCCCC001001. */ +{ "swape", 0x282F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, RC }, { C_F }}, + +/* swape<.f> 0,c 0010111000101111F111CCCCCC001001. */ +{ "swape", 0x2E2F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, RC }, { C_F }}, + +/* swape<.f> b,u6 00101bbb01101111FBBBuuuuuu001001. */ +{ "swape", 0x286F0009, 0xF8FF003F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, UIMM6_20 }, { C_F }}, + +/* swape<.f> 0,u6 0010111001101111F111uuuuuu001001. */ +{ "swape", 0x2E6F7009, 0xFFFF703F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, UIMM6_20 }, { C_F }}, + +/* swape<.f> b,limm 00101bbb00101111FBBB111110001001. */ +{ "swape", 0x282F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { RB, LIMM }, { C_F }}, + +/* swape<.f> 0,limm 0010111000101111F111111110001001. */ +{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }}, + +/* swi 00100010011011110000000000111111. */ +{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* swi_s 0111101011100000. */ +{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* swi_s u6 01111uuuuuu11111. */ +{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }}, + +/* sync 00100011011011110000000000111111. */ +{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }}, + +/* trap0 00100010011011110000000000111111. */ +{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { }, { 0 }}, + +/* trap_s u6 01111uuuuuu11110. */ +{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }}, + +/* tst b,c 00100bbb000010111BBBCCCCCCRRRRRR. */ +{ "tst", 0x200B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { 0 }}, + +/* tst b,c 00100bbb000010111BBBCCCCCC000000. */ +{ "tst", 0x200B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, RC }, { 0 }}, + +/* tst<.cc> b,c 00100bbb110010111BBBCCCCCC0QQQQQ. */ +{ "tst", 0x20CB8000, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RC }, { C_CC }}, + +/* tst b,u6 00100bbb010010111BBBuuuuuuRRRRRR. */ +{ "tst", 0x204B8000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* tst b,u6 00100bbb010010111BBBuuuuuu000000. */ +{ "tst", 0x204B8000, 0xF8FF803F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* tst<.cc> b,u6 00100bbb110010111BBBuuuuuu1QQQQQ. */ +{ "tst", 0x20CB8020, 0xF8FF8020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, UIMM6_20 }, { C_CC }}, + +/* tst b,s12 00100bbb100010111BBBssssssSSSSSS. */ +{ "tst", 0x208B8000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, SIMM12_20 }, { 0 }}, + +/* tst limm,c 00100110000010111111CCCCCCRRRRRR. */ +{ "tst", 0x260BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { 0 }}, + +/* tst b,limm 00100bbb000010111BBB111110RRRRRR. */ +{ "tst", 0x200B8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { 0 }}, + +/* tst limm,c 00100110000010111111CCCCCC000000. */ +{ "tst", 0x260BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, RC }, { 0 }}, + +/* tst b,limm 00100bbb000010111BBB111110000000. */ +{ "tst", 0x200B8F80, 0xF8FF8FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { RB, LIMM }, { 0 }}, + +/* tst<.cc> b,limm 00100bbb110010111BBB1111100QQQQQ. */ +{ "tst", 0x20CB8F80, 0xF8FF8FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, LIMM }, { C_CC }}, + +/* tst<.cc> limm,c 00100110110010111111CCCCCC0QQQQQ. */ +{ "tst", 0x26CBF000, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, RC }, { C_CC }}, + +/* tst limm,u6 00100110010010111111uuuuuuRRRRRR. */ +{ "tst", 0x264BF000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* tst limm,u6 00100110010010111111uuuuuu000000. */ +{ "tst", 0x264BF000, 0xFFFFF03F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, UIMM6_20 }, { 0 }}, + +/* tst<.cc> limm,u6 00100110110010111111uuuuuu1QQQQQ. */ +{ "tst", 0x26CBF020, 0xFFFFF020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, UIMM6_20 }, { C_CC }}, + +/* tst limm,s12 00100110100010111111ssssssSSSSSS. */ +{ "tst", 0x268BF000, 0xFFFFF000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, SIMM12_20 }, { 0 }}, + +/* tst limm,limm 00100110000010111111111110RRRRRR. */ +{ "tst", 0x260BFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* tst limm,limm 00100110000010111111111110000000. */ +{ "tst", 0x260BFF80, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, LOGICAL, NONE, { LIMM, LIMMdup }, { 0 }}, + +/* tst<.cc> limm,limm 001001101100101111111111100QQQQQ. */ +{ "tst", 0x26CBFF80, 0xFFFFFFE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { LIMM, LIMMdup }, { C_CC }}, + +/* tst_s b,c 01111bbbccc01011. */ +{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }}, + +/* unimp_s 0111100111100000. */ +{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }}, + +/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */ +{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* upkqb<.f><.cc> b,b,c 00110bbb11100001FBBBCCCCCC0QQQQQ. */ +{ "upkqb", 0x30E10000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* upkqb<.f> a,b,u6 00110bbb01100001FBBBuuuuuuAAAAAA. */ +{ "upkqb", 0x30610000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* upkqb<.f> b,b,s12 00110bbb10100001FBBBssssssSSSSSS. */ +{ "upkqb", 0x30A10000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* upkqb<.f> a,limm,c 0011011000100001F111CCCCCCAAAAAA. */ +{ "upkqb", 0x36217000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* upkqb<.f> a,b,limm 00110bbb00100001FBBB111110AAAAAA. */ +{ "upkqb", 0x30210F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* upkqb<.f><.cc> b,b,limm 00110bbb11100001FBBB1111100QQQQQ. */ +{ "upkqb", 0x30E10F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* vabs2h b,c 00101bbb001011110BBBCCCCCC101000. */ +{ "vabs2h", 0x282F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vabs2h 0,c 00101110001011110111CCCCCC101000. */ +{ "vabs2h", 0x2E2F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vabs2h b,u6 00101bbb011011110BBBuuuuuu101000. */ +{ "vabs2h", 0x286F0028, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vabs2h 0,u6 00101110011011110111uuuuuu101000. */ +{ "vabs2h", 0x2E6F7028, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vabs2h b,limm 00101bbb001011110BBB111110101000. */ +{ "vabs2h", 0x282F0FA8, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vabs2h 0,limm 00101110001011110111111110101000. */ +{ "vabs2h", 0x2E2F7FA8, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vabss2h b,c 00101bbb001011110BBBCCCCCC101001. */ +{ "vabss2h", 0x282F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vabss2h 0,c 00101110001011110111CCCCCC101001. */ +{ "vabss2h", 0x2E2F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vabss2h b,u6 00101bbb011011110BBBuuuuuu101001. */ +{ "vabss2h", 0x286F0029, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vabss2h 0,u6 00101110011011110111uuuuuu101001. */ +{ "vabss2h", 0x2E6F7029, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vabss2h b,limm 00101bbb001011110BBB111110101001. */ +{ "vabss2h", 0x282F0FA9, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vabss2h 0,limm 00101110001011110111111110101001. */ +{ "vabss2h", 0x2E2F7FA9, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vadd2 a,b,c 00101bbb001111000BBBCCCCCCAAAAAA. */ +{ "vadd2", 0x283C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vadd2 0,b,c 00101bbb001111000BBBCCCCCC111110. */ +{ "vadd2", 0x283C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vadd2<.cc> b,b,c 00101bbb111111000BBBCCCCCC0QQQQQ. */ +{ "vadd2", 0x28FC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vadd2 a,b,u6 00101bbb011111000BBBuuuuuuAAAAAA. */ +{ "vadd2", 0x287C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vadd2 0,b,u6 00101bbb011111000BBBuuuuuu111110. */ +{ "vadd2", 0x287C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vadd2<.cc> b,b,u6 00101bbb111111000BBBuuuuuu1QQQQQ. */ +{ "vadd2", 0x28FC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vadd2 b,b,s12 00101bbb101111000BBBssssssSSSSSS. */ +{ "vadd2", 0x28BC0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vadd2 a,limm,c 00101110001111000111CCCCCCAAAAAA. */ +{ "vadd2", 0x2E3C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vadd2 a,b,limm 00101bbb001111000BBB111110AAAAAA. */ +{ "vadd2", 0x283C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vadd2 0,limm,c 00101110001111000111CCCCCC111110. */ +{ "vadd2", 0x2E3C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vadd2 0,b,limm 00101bbb001111000BBB111110111110. */ +{ "vadd2", 0x283C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vadd2<.cc> b,b,limm 00101bbb111111000BBB1111100QQQQQ. */ +{ "vadd2", 0x28FC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vadd2<.cc> 0,limm,c 00101110111111000111CCCCCC0QQQQQ. */ +{ "vadd2", 0x2EFC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vadd2 a,limm,u6 00101110011111000111uuuuuuAAAAAA. */ +{ "vadd2", 0x2E7C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd2 0,limm,u6 00101110011111000111uuuuuu111110. */ +{ "vadd2", 0x2E7C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd2<.cc> 0,limm,u6 00101110111111000111uuuuuu1QQQQQ. */ +{ "vadd2", 0x2EFC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vadd2 0,limm,s12 00101110101111000111ssssssSSSSSS. */ +{ "vadd2", 0x2EBC7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vadd2 a,limm,limm 00101110001111000111111110AAAAAA. */ +{ "vadd2", 0x2E3C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vadd2 0,limm,limm 00101110001111000111111110111110. */ +{ "vadd2", 0x2E3C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vadd2<.cc> 0,limm,limm 001011101111110001111111100QQQQQ. */ +{ "vadd2", 0x2EFC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vadd2h a,b,c 00101bbb000101000BBBCCCCCCAAAAAA. */ +{ "vadd2h", 0x28140000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }}, + +/* vadd2h 0,b,c 00101bbb000101000BBBCCCCCC111110. */ +{ "vadd2h", 0x2814003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }}, + +/* vadd2h<.cc> b,b,c 00101bbb110101000BBBCCCCCC0QQQQQ. */ +{ "vadd2h", 0x28D40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }}, + +/* vadd2h a,b,u6 00101bbb010101000BBBuuuuuuAAAAAA. */ +{ "vadd2h", 0x28540000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vadd2h 0,b,u6 00101bbb010101000BBBuuuuuu111110. */ +{ "vadd2h", 0x2854003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vadd2h<.cc> b,b,u6 00101bbb110101000BBBuuuuuu1QQQQQ. */ +{ "vadd2h", 0x28D40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vadd2h b,b,s12 00101bbb100101000BBBssssssSSSSSS. */ +{ "vadd2h", 0x28940000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vadd2h a,limm,c 00101110000101000111CCCCCCAAAAAA. */ +{ "vadd2h", 0x2E147000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }}, + +/* vadd2h a,b,limm 00101bbb000101000BBB111110AAAAAA. */ +{ "vadd2h", 0x28140F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }}, + +/* vadd2h 0,limm,c 00101110000101000111CCCCCC111110. */ +{ "vadd2h", 0x2E14703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }}, + +/* vadd2h 0,b,limm 00101bbb000101000BBB111110111110. */ +{ "vadd2h", 0x28140FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }}, + +/* vadd2h<.cc> b,b,limm 00101bbb110101000BBB1111100QQQQQ. */ +{ "vadd2h", 0x28D40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vadd2h<.cc> 0,limm,c 00101110110101000111CCCCCC0QQQQQ. */ +{ "vadd2h", 0x2ED47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }}, + +/* vadd2h a,limm,u6 00101110010101000111uuuuuuAAAAAA. */ +{ "vadd2h", 0x2E547000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd2h 0,limm,u6 00101110010101000111uuuuuu111110. */ +{ "vadd2h", 0x2E54703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd2h<.cc> 0,limm,u6 00101110110101000111uuuuuu1QQQQQ. */ +{ "vadd2h", 0x2ED47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vadd2h 0,limm,s12 00101110100101000111ssssssSSSSSS. */ +{ "vadd2h", 0x2E947000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vadd2h a,limm,limm 00101110000101000111111110AAAAAA. */ +{ "vadd2h", 0x2E147F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vadd2h 0,limm,limm 00101110000101000111111110111110. */ +{ "vadd2h", 0x2E147FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vadd2h<.cc> 0,limm,limm 001011101101010001111111100QQQQQ. */ +{ "vadd2h", 0x2ED47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vadd4b a,b,c 00101bbb001001000BBBCCCCCCAAAAAA. */ +{ "vadd4b", 0x28240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vadd4b 0,b,c 00101bbb001001000BBBCCCCCC111110. */ +{ "vadd4b", 0x2824003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vadd4b<.cc> b,b,c 00101bbb111001000BBBCCCCCC0QQQQQ. */ +{ "vadd4b", 0x28E40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vadd4b a,b,u6 00101bbb011001000BBBuuuuuuAAAAAA. */ +{ "vadd4b", 0x28640000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vadd4b 0,b,u6 00101bbb011001000BBBuuuuuu111110. */ +{ "vadd4b", 0x2864003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vadd4b<.cc> b,b,u6 00101bbb111001000BBBuuuuuu1QQQQQ. */ +{ "vadd4b", 0x28E40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vadd4b b,b,s12 00101bbb101001000BBBssssssSSSSSS. */ +{ "vadd4b", 0x28A40000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vadd4b a,limm,c 00101110001001000111CCCCCCAAAAAA. */ +{ "vadd4b", 0x2E247000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vadd4b a,b,limm 00101bbb001001000BBB111110AAAAAA. */ +{ "vadd4b", 0x28240F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vadd4b 0,limm,c 00101110011001000111CCCCCC111110. */ +{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vadd4b 0,b,limm 00101bbb001001000BBB111110111110. */ +{ "vadd4b", 0x28240FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vadd4b<.cc> b,b,limm 00101bbb111001000BBB1111100QQQQQ. */ +{ "vadd4b", 0x28E40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vadd4b<.cc> 0,limm,c 00101110111001000111CCCCCC0QQQQQ. */ +{ "vadd4b", 0x2EE47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vadd4b a,limm,u6 00101110011001000111uuuuuuAAAAAA. */ +{ "vadd4b", 0x2E647000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd4b 0,limm,u6 00101110011001000111uuuuuu111110. */ +{ "vadd4b", 0x2E64703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd4b<.cc> 0,limm,u6 00101110111001000111uuuuuu1QQQQQ. */ +{ "vadd4b", 0x2EE47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vadd4b 0,limm,s12 00101110101001000111ssssssSSSSSS. */ +{ "vadd4b", 0x2EA47000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vadd4b a,limm,limm 00101110001001000111111110AAAAAA. */ +{ "vadd4b", 0x2E247F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vadd4b 0,limm,limm 00101110001001000111111110111110. */ +{ "vadd4b", 0x2E247FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vadd4b<.cc> 0,limm,limm 001011101110010001111111100QQQQQ. */ +{ "vadd4b", 0x2EE47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vadd4h a,b,c 00101bbb001110000BBBCCCCCCAAAAAA. */ +{ "vadd4h", 0x28380000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vadd4h 0,b,c 00101bbb001110000BBBCCCCCC111110. */ +{ "vadd4h", 0x2838003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vadd4h<.cc> b,b,c 00101bbb111110000BBBCCCCCC0QQQQQ. */ +{ "vadd4h", 0x28F80000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vadd4h a,b,u6 00101bbb011110000BBBuuuuuuAAAAAA. */ +{ "vadd4h", 0x28780000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vadd4h 0,b,u6 00101bbb011110000BBBuuuuuu111110. */ +{ "vadd4h", 0x2878003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vadd4h<.cc> b,b,u6 00101bbb111110000BBBuuuuuu1QQQQQ. */ +{ "vadd4h", 0x28F80020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vadd4h b,b,s12 00101bbb101110000BBBssssssSSSSSS. */ +{ "vadd4h", 0x28B80000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vadd4h a,limm,c 00101110001110000111CCCCCCAAAAAA. */ +{ "vadd4h", 0x2E387000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vadd4h a,b,limm 00101bbb001110000BBB111110AAAAAA. */ +{ "vadd4h", 0x28380F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vadd4h 0,limm,c 00101110001110000111CCCCCC111110. */ +{ "vadd4h", 0x2E38703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vadd4h 0,b,limm 00101bbb001110000BBB111110111110. */ +{ "vadd4h", 0x28380FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vadd4h<.cc> b,b,limm 00101bbb111110000BBB1111100QQQQQ. */ +{ "vadd4h", 0x28F80F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vadd4h<.cc> 0,limm,c 00101110111110000111CCCCCC0QQQQQ. */ +{ "vadd4h", 0x2EF87000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vadd4h a,limm,u6 00101110011110000111uuuuuuAAAAAA. */ +{ "vadd4h", 0x2E787000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd4h 0,limm,u6 00101110011110000111uuuuuu111110. */ +{ "vadd4h", 0x2E78703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadd4h<.cc> 0,limm,u6 00101110111110000111uuuuuu1QQQQQ. */ +{ "vadd4h", 0x2EF87020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vadd4h 0,limm,s12 00101110101110000111ssssssSSSSSS. */ +{ "vadd4h", 0x2EB87000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vadd4h a,limm,limm 00101110001110000111111110AAAAAA. */ +{ "vadd4h", 0x2E387F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vadd4h 0,limm,limm 00101110001110000111111110111110. */ +{ "vadd4h", 0x2E387FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vadd4h<.cc> 0,limm,limm 001011101111100001111111100QQQQQ. */ +{ "vadd4h", 0x2EF87F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vadds2h a,b,c 00101bbb000101001BBBCCCCCCAAAAAA. */ +{ "vadds2h", 0x28148000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vadds2h 0,b,c 00101bbb000101001BBBCCCCCC111110. */ +{ "vadds2h", 0x2814803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vadds2h<.cc> b,b,c 00101bbb110101001BBBCCCCCC0QQQQQ. */ +{ "vadds2h", 0x28D48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vadds2h a,b,u6 00101bbb010101001BBBuuuuuuAAAAAA. */ +{ "vadds2h", 0x28548000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vadds2h 0,b,u6 00101bbb010101001BBBuuuuuu111110. */ +{ "vadds2h", 0x2854803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vadds2h<.cc> b,b,u6 00101bbb110101001BBBuuuuuu1QQQQQ. */ +{ "vadds2h", 0x28D48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vadds2h b,b,s12 00101bbb100101001BBBssssssSSSSSS. */ +{ "vadds2h", 0x28948000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vadds2h a,limm,c 00101110000101001111CCCCCCAAAAAA. */ +{ "vadds2h", 0x2E14F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vadds2h a,b,limm 00101bbb000101001BBB111110AAAAAA. */ +{ "vadds2h", 0x28148F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vadds2h 0,limm,c 00101110000101001111CCCCCC111110. */ +{ "vadds2h", 0x2E14F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vadds2h 0,b,limm 00101bbb000101001BBB111110111110. */ +{ "vadds2h", 0x28148FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vadds2h<.cc> b,b,limm 00101bbb110101001BBB1111100QQQQQ. */ +{ "vadds2h", 0x28D48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vadds2h<.cc> 0,limm,c 00101110110101001111CCCCCC0QQQQQ. */ +{ "vadds2h", 0x2ED4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vadds2h a,limm,u6 00101110010101001111uuuuuuAAAAAA. */ +{ "vadds2h", 0x2E54F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadds2h 0,limm,u6 00101110010101001111uuuuuu111110. */ +{ "vadds2h", 0x2E54F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vadds2h<.cc> 0,limm,u6 00101110110101001111uuuuuu1QQQQQ. */ +{ "vadds2h", 0x2ED4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vadds2h 0,limm,s12 00101110100101001111ssssssSSSSSS. */ +{ "vadds2h", 0x2E94F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vadds2h a,limm,limm 00101110000101001111111110AAAAAA. */ +{ "vadds2h", 0x2E14FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vadds2h 0,limm,limm 00101110000101001111111110111110. */ +{ "vadds2h", 0x2E14FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vadds2h<.cc> 0,limm,limm 001011101101010011111111100QQQQQ. */ +{ "vadds2h", 0x2ED4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vaddsub a,b,c 00101bbb001111100BBBCCCCCCAAAAAA. */ +{ "vaddsub", 0x283E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vaddsub 0,b,c 00101bbb001111100BBBCCCCCC111110. */ +{ "vaddsub", 0x283E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vaddsub<.cc> b,b,c 00101bbb111111100BBBCCCCCC0QQQQQ. */ +{ "vaddsub", 0x28FE0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vaddsub a,b,u6 00101bbb011111100BBBuuuuuuAAAAAA. */ +{ "vaddsub", 0x287E0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub 0,b,u6 00101bbb011111100BBBuuuuuu111110. */ +{ "vaddsub", 0x287E003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub<.cc> b,b,u6 00101bbb111111100BBBuuuuuu1QQQQQ. */ +{ "vaddsub", 0x28FE0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vaddsub b,b,s12 00101bbb101111100BBBssssssSSSSSS. */ +{ "vaddsub", 0x28BE0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vaddsub a,limm,c 00101110001111100111CCCCCCAAAAAA. */ +{ "vaddsub", 0x2E3E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vaddsub a,b,limm 00101bbb001111100BBB111110AAAAAA. */ +{ "vaddsub", 0x283E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vaddsub 0,limm,c 00101110001111100111CCCCCC111110. */ +{ "vaddsub", 0x2E3E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vaddsub 0,b,limm 00101bbb001111100BBB111110111110. */ +{ "vaddsub", 0x283E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vaddsub<.cc> b,b,limm 00101bbb111111100BBB1111100QQQQQ. */ +{ "vaddsub", 0x28FE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vaddsub<.cc> 0,limm,c 00101110111111100111CCCCCC0QQQQQ. */ +{ "vaddsub", 0x2EFE7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vaddsub a,limm,u6 00101110011111100111uuuuuuAAAAAA. */ +{ "vaddsub", 0x2E7E7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub 0,limm,u6 00101110011111100111uuuuuu111110. */ +{ "vaddsub", 0x2E7E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub<.cc> 0,limm,u6 00101110111111100111uuuuuu1QQQQQ. */ +{ "vaddsub", 0x2EFE7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vaddsub 0,limm,s12 00101110101111100111ssssssSSSSSS. */ +{ "vaddsub", 0x2EBE7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vaddsub a,limm,limm 00101110001111100111111110AAAAAA. */ +{ "vaddsub", 0x2E3E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub 0,limm,limm 00101110001111100111111110111110. */ +{ "vaddsub", 0x2E3E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub<.cc> 0,limm,limm 001011101111111001111111100QQQQQ. */ +{ "vaddsub", 0x2EFE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vaddsub2h a,b,c 00101bbb000101100BBBCCCCCCAAAAAA. */ +{ "vaddsub2h", 0x28160000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }}, + +/* vaddsub2h 0,b,c 00101bbb000101100BBBCCCCCC111110. */ +{ "vaddsub2h", 0x2816003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }}, + +/* vaddsub2h<.cc> b,b,c 00101bbb110101100BBBCCCCCC0QQQQQ. */ +{ "vaddsub2h", 0x28D60000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }}, + +/* vaddsub2h a,b,u6 00101bbb010101100BBBuuuuuuAAAAAA. */ +{ "vaddsub2h", 0x28560000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub2h 0,b,u6 00101bbb010101100BBBuuuuuu111110. */ +{ "vaddsub2h", 0x2856003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub2h<.cc> b,b,u6 00101bbb110101100BBBuuuuuu1QQQQQ. */ +{ "vaddsub2h", 0x28D60020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vaddsub2h b,b,s12 00101bbb100101100BBBssssssSSSSSS. */ +{ "vaddsub2h", 0x28960000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vaddsub2h a,limm,c 00101110000101100111CCCCCCAAAAAA. */ +{ "vaddsub2h", 0x2E167000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }}, + +/* vaddsub2h a,b,limm 00101bbb000101100BBB111110AAAAAA. */ +{ "vaddsub2h", 0x28160F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }}, + +/* vaddsub2h 0,limm,c 00101110000101100111CCCCCC111110. */ +{ "vaddsub2h", 0x2E16703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }}, + +/* vaddsub2h 0,b,limm 00101bbb000101100BBB111110111110. */ +{ "vaddsub2h", 0x28160FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }}, + +/* vaddsub2h<.cc> b,b,limm 00101bbb110101100BBB1111100QQQQQ. */ +{ "vaddsub2h", 0x28D60F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vaddsub2h<.cc> 0,limm,c 00101110110101100111CCCCCC0QQQQQ. */ +{ "vaddsub2h", 0x2ED67000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }}, + +/* vaddsub2h a,limm,u6 00101110010101100111uuuuuuAAAAAA. */ +{ "vaddsub2h", 0x2E567000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub2h 0,limm,u6 00101110010101100111uuuuuu111110. */ +{ "vaddsub2h", 0x2E56703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub2h<.cc> 0,limm,u6 00101110110101100111uuuuuu1QQQQQ. */ +{ "vaddsub2h", 0x2ED67020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vaddsub2h 0,limm,s12 00101110100101100111ssssssSSSSSS. */ +{ "vaddsub2h", 0x2E967000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vaddsub2h a,limm,limm 00101110000101100111111110AAAAAA. */ +{ "vaddsub2h", 0x2E167F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub2h 0,limm,limm 00101110000101100111111110111110. */ +{ "vaddsub2h", 0x2E167FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub2h<.cc> 0,limm,limm 001011101101011001111111100QQQQQ. */ +{ "vaddsub2h", 0x2ED67F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vaddsub4h a,b,c 00101bbb001110100BBBCCCCCCAAAAAA. */ +{ "vaddsub4h", 0x283A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vaddsub4h 0,b,c 00101bbb001110100BBBCCCCCC111110. */ +{ "vaddsub4h", 0x283A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vaddsub4h<.cc> b,b,c 00101bbb111110100BBBCCCCCC0QQQQQ. */ +{ "vaddsub4h", 0x28FA0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vaddsub4h a,b,u6 00101bbb011110100BBBuuuuuuAAAAAA. */ +{ "vaddsub4h", 0x287A0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub4h 0,b,u6 00101bbb011110100BBBuuuuuu111110. */ +{ "vaddsub4h", 0x287A003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsub4h<.cc> b,b,u6 00101bbb111110100BBBuuuuuu1QQQQQ. */ +{ "vaddsub4h", 0x28FA0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vaddsub4h b,b,s12 00101bbb101110100BBBssssssSSSSSS. */ +{ "vaddsub4h", 0x28BA0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vaddsub4h a,limm,c 00101110001110100111CCCCCCAAAAAA. */ +{ "vaddsub4h", 0x2E3A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vaddsub4h a,b,limm 00101bbb001110100BBB111110AAAAAA. */ +{ "vaddsub4h", 0x283A0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vaddsub4h 0,limm,c 00101110001110100111CCCCCC111110. */ +{ "vaddsub4h", 0x2E3A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vaddsub4h 0,b,limm 00101bbb001110100BBB111110111110. */ +{ "vaddsub4h", 0x283A0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vaddsub4h<.cc> b,b,limm 00101bbb111110100BBB1111100QQQQQ. */ +{ "vaddsub4h", 0x28FA0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vaddsub4h<.cc> 0,limm,c 00101110111110100111CCCCCC0QQQQQ. */ +{ "vaddsub4h", 0x2EFA7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vaddsub4h a,limm,u6 00101110011110100111uuuuuuAAAAAA. */ +{ "vaddsub4h", 0x2E7A7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub4h 0,limm,u6 00101110011110100111uuuuuu111110. */ +{ "vaddsub4h", 0x2E7A703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsub4h<.cc> 0,limm,u6 00101110111110100111uuuuuu1QQQQQ. */ +{ "vaddsub4h", 0x2EFA7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vaddsub4h 0,limm,s12 00101110101110100111ssssssSSSSSS. */ +{ "vaddsub4h", 0x2EBA7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vaddsub4h a,limm,limm 00101110001110100111111110AAAAAA. */ +{ "vaddsub4h", 0x2E3A7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub4h 0,limm,limm 00101110001110100111111110111110. */ +{ "vaddsub4h", 0x2E3A7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsub4h<.cc> 0,limm,limm 001011101111101001111111100QQQQQ. */ +{ "vaddsub4h", 0x2EFA7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vaddsubs2h a,b,c 00101bbb000101101BBBCCCCCCAAAAAA. */ +{ "vaddsubs2h", 0x28168000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vaddsubs2h 0,b,c 00101bbb000101101BBBCCCCCC111110. */ +{ "vaddsubs2h", 0x2816803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,c 00101bbb110101101BBBCCCCCC0QQQQQ. */ +{ "vaddsubs2h", 0x28D68000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vaddsubs2h a,b,u6 00101bbb010101101BBBuuuuuuAAAAAA. */ +{ "vaddsubs2h", 0x28568000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsubs2h 0,b,u6 00101bbb010101101BBBuuuuuu111110. */ +{ "vaddsubs2h", 0x2856803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,u6 00101bbb110101101BBBuuuuuu1QQQQQ. */ +{ "vaddsubs2h", 0x28D68020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vaddsubs2h b,b,s12 00101bbb100101101BBBssssssSSSSSS. */ +{ "vaddsubs2h", 0x28968000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vaddsubs2h a,limm,c 00101110000101101111CCCCCCAAAAAA. */ +{ "vaddsubs2h", 0x2E16F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vaddsubs2h a,b,limm 00101bbb000101101BBB111110AAAAAA. */ +{ "vaddsubs2h", 0x28168F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vaddsubs2h 0,limm,c 00101110000101101111CCCCCC111110. */ +{ "vaddsubs2h", 0x2E16F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vaddsubs2h 0,b,limm 00101bbb000101101BBB111110111110. */ +{ "vaddsubs2h", 0x28168FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vaddsubs2h<.cc> b,b,limm 00101bbb110101101BBB1111100QQQQQ. */ +{ "vaddsubs2h", 0x28D68F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vaddsubs2h<.cc> 0,limm,c 00101110110101101111CCCCCC0QQQQQ. */ +{ "vaddsubs2h", 0x2ED6F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vaddsubs2h a,limm,u6 00101110010101101111uuuuuuAAAAAA. */ +{ "vaddsubs2h", 0x2E56F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsubs2h 0,limm,u6 00101110010101101111uuuuuu111110. */ +{ "vaddsubs2h", 0x2E56F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vaddsubs2h<.cc> 0,limm,u6 00101110110101101111uuuuuu1QQQQQ. */ +{ "vaddsubs2h", 0x2ED6F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vaddsubs2h 0,limm,s12 00101110100101101111ssssssSSSSSS. */ +{ "vaddsubs2h", 0x2E96F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vaddsubs2h a,limm,limm 00101110000101101111111110AAAAAA. */ +{ "vaddsubs2h", 0x2E16FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsubs2h 0,limm,limm 00101110000101101111111110111110. */ +{ "vaddsubs2h", 0x2E16FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vaddsubs2h<.cc> 0,limm,limm 001011101101011011111111100QQQQQ. */ +{ "vaddsubs2h", 0x2ED6FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* valgn2h a,b,c 00101bbb000011010BBBCCCCCCAAAAAA. */ +{ "valgn2h", 0x280D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* valgn2h 0,b,c 00101bbb000011010BBBCCCCCC111110. */ +{ "valgn2h", 0x280D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* valgn2h<.cc> b,b,c 00101bbb110011010BBBCCCCCC0QQQQQ. */ +{ "valgn2h", 0x28CD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* valgn2h a,b,u6 00101bbb010011010BBBuuuuuuAAAAAA. */ +{ "valgn2h", 0x284D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* valgn2h 0,b,u6 00101bbb010011010BBBuuuuuu111110. */ +{ "valgn2h", 0x284D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* valgn2h<.cc> b,b,u6 00101bbb110011010BBBuuuuuu1QQQQQ. */ +{ "valgn2h", 0x28CD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* valgn2h b,b,s12 00101bbb100011010BBBssssssSSSSSS. */ +{ "valgn2h", 0x288D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* valgn2h a,limm,c 00101110000011010111CCCCCCAAAAAA. */ +{ "valgn2h", 0x2E0D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* valgn2h a,b,limm 00101bbb000011010BBB111110AAAAAA. */ +{ "valgn2h", 0x280D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* valgn2h 0,limm,c 00101110000011010111CCCCCC111110. */ +{ "valgn2h", 0x2E0D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* valgn2h 0,b,limm 00101bbb000011010BBB111110111110. */ +{ "valgn2h", 0x280D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* valgn2h<.cc> b,b,limm 00101bbb110011010BBB1111100QQQQQ. */ +{ "valgn2h", 0x28CD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* valgn2h<.cc> 0,limm,c 00101110110011010111CCCCCC0QQQQQ. */ +{ "valgn2h", 0x2ECD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* valgn2h a,limm,u6 00101110010011010111uuuuuuAAAAAA. */ +{ "valgn2h", 0x2E4D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* valgn2h 0,limm,u6 00101110010011010111uuuuuu111110. */ +{ "valgn2h", 0x2E4D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* valgn2h<.cc> 0,limm,u6 00101110110011010111uuuuuu1QQQQQ. */ +{ "valgn2h", 0x2ECD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* valgn2h 0,limm,s12 00101110100011010111ssssssSSSSSS. */ +{ "valgn2h", 0x2E8D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* valgn2h a,limm,limm 00101110000011010111111110AAAAAA. */ +{ "valgn2h", 0x2E0D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* valgn2h 0,limm,limm 00101110000011010111111110111110. */ +{ "valgn2h", 0x2E0D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* valgn2h<.cc> 0,limm,limm 001011101100110101111111100QQQQQ. */ +{ "valgn2h", 0x2ECD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vasl2h a,b,c 00101bbb001000010BBBCCCCCCAAAAAA. */ +{ "vasl2h", 0x28210000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vasl2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ +{ "vasl2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vasl2h<.cc> b,b,c 00101bbb111000010BBBCCCCCC0QQQQQ. */ +{ "vasl2h", 0x28E10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vasl2h a,b,u6 00101bbb011000010BBBuuuuuuAAAAAA. */ +{ "vasl2h", 0x28610000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vasl2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ +{ "vasl2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vasl2h<.cc> b,b,u6 00101bbb111000010BBBuuuuuu1QQQQQ. */ +{ "vasl2h", 0x28E10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vasl2h b,b,s12 00101bbb101000010BBBssssssSSSSSS. */ +{ "vasl2h", 0x28A10000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vasl2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ +{ "vasl2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vasl2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ +{ "vasl2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vasl2h 0,limm,c 00101110011000010111CCCCCC111110. */ +{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vasl2h 0,b,limm 00101bbb001000010BBB111110111110. */ +{ "vasl2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vasl2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ +{ "vasl2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vasl2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ +{ "vasl2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vasl2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ +{ "vasl2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasl2h 0,limm,u6 00101110011000010111uuuuuu111110. */ +{ "vasl2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasl2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ +{ "vasl2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vasl2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ +{ "vasl2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vasl2h a,limm,limm 00101110001000010111111110AAAAAA. */ +{ "vasl2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vasl2h 0,limm,limm 00101110001000010111111110111110. */ +{ "vasl2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vasl2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ +{ "vasl2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vasls2h a,b,c 00101bbb001000011BBBCCCCCCAAAAAA. */ +{ "vasls2h", 0x28218000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vasls2h 0,b,c 00101bbb001000010BBBCCCCCC111110. */ +{ "vasls2h", 0x2821003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vasls2h<.cc> b,b,c 00101bbb111000011BBBCCCCCC0QQQQQ. */ +{ "vasls2h", 0x28E18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vasls2h a,b,u6 00101bbb011000011BBBuuuuuuAAAAAA. */ +{ "vasls2h", 0x28618000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vasls2h 0,b,u6 00101bbb011000010BBBuuuuuu111110. */ +{ "vasls2h", 0x2861003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vasls2h<.cc> b,b,u6 00101bbb111000011BBBuuuuuu1QQQQQ. */ +{ "vasls2h", 0x28E18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vasls2h b,b,s12 00101bbb101000011BBBssssssSSSSSS. */ +{ "vasls2h", 0x28A18000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vasls2h a,limm,c 00101110001000010111CCCCCCAAAAAA. */ +{ "vasls2h", 0x2E217000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vasls2h a,b,limm 00101bbb001000010BBB111110AAAAAA. */ +{ "vasls2h", 0x28210F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vasls2h 0,limm,c 00101110011000010111CCCCCC111110. */ +{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vasls2h 0,b,limm 00101bbb001000010BBB111110111110. */ +{ "vasls2h", 0x28210FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vasls2h<.cc> b,b,limm 00101bbb111000010BBB1111100QQQQQ. */ +{ "vasls2h", 0x28E10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vasls2h<.cc> 0,limm,c 00101110111000010111CCCCCC0QQQQQ. */ +{ "vasls2h", 0x2EE17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vasls2h a,limm,u6 00101110011000010111uuuuuuAAAAAA. */ +{ "vasls2h", 0x2E617000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasls2h 0,limm,u6 00101110011000010111uuuuuu111110. */ +{ "vasls2h", 0x2E61703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasls2h<.cc> 0,limm,u6 00101110111000010111uuuuuu1QQQQQ. */ +{ "vasls2h", 0x2EE17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vasls2h 0,limm,s12 00101110101000010111ssssssSSSSSS. */ +{ "vasls2h", 0x2EA17000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vasls2h a,limm,limm 00101110001000010111111110AAAAAA. */ +{ "vasls2h", 0x2E217F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vasls2h 0,limm,limm 00101110001000010111111110111110. */ +{ "vasls2h", 0x2E217FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vasls2h<.cc> 0,limm,limm 001011101110000101111111100QQQQQ. */ +{ "vasls2h", 0x2EE17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vasr2h a,b,c 00101bbb001000100BBBCCCCCCAAAAAA. */ +{ "vasr2h", 0x28220000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vasr2h 0,b,c 00101bbb001000100BBBCCCCCC111110. */ +{ "vasr2h", 0x2822003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vasr2h<.cc> b,b,c 00101bbb111000100BBBCCCCCC0QQQQQ. */ +{ "vasr2h", 0x28E20000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vasr2h a,b,u6 00101bbb011000100BBBuuuuuuAAAAAA. */ +{ "vasr2h", 0x28620000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vasr2h 0,b,u6 00101bbb011000100BBBuuuuuu111110. */ +{ "vasr2h", 0x2862003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vasr2h<.cc> b,b,u6 00101bbb111000100BBBuuuuuu1QQQQQ. */ +{ "vasr2h", 0x28E20020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vasr2h b,b,s12 00101bbb101000100BBBssssssSSSSSS. */ +{ "vasr2h", 0x28A20000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vasr2h a,limm,c 00101110001000100111CCCCCCAAAAAA. */ +{ "vasr2h", 0x2E227000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vasr2h a,b,limm 00101bbb001000100BBB111110AAAAAA. */ +{ "vasr2h", 0x28220F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vasr2h 0,limm,c 00101110011000100111CCCCCC111110. */ +{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vasr2h 0,b,limm 00101bbb001000100BBB111110111110. */ +{ "vasr2h", 0x28220FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vasr2h<.cc> b,b,limm 00101bbb111000100BBB1111100QQQQQ. */ +{ "vasr2h", 0x28E20F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vasr2h<.cc> 0,limm,c 00101110111000100111CCCCCC0QQQQQ. */ +{ "vasr2h", 0x2EE27000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vasr2h a,limm,u6 00101110011000100111uuuuuuAAAAAA. */ +{ "vasr2h", 0x2E627000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasr2h 0,limm,u6 00101110011000100111uuuuuu111110. */ +{ "vasr2h", 0x2E62703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasr2h<.cc> 0,limm,u6 00101110111000100111uuuuuu1QQQQQ. */ +{ "vasr2h", 0x2EE27020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vasr2h 0,limm,s12 00101110101000100111ssssssSSSSSS. */ +{ "vasr2h", 0x2EA27000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vasr2h a,limm,limm 00101110001000100111111110AAAAAA. */ +{ "vasr2h", 0x2E227F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vasr2h 0,limm,limm 00101110001000100111111110111110. */ +{ "vasr2h", 0x2E227FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vasr2h<.cc> 0,limm,limm 001011101110001001111111100QQQQQ. */ +{ "vasr2h", 0x2EE27F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vasrs2h a,b,c 00101bbb001000101BBBCCCCCCAAAAAA. */ +{ "vasrs2h", 0x28228000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vasrs2h 0,b,c 00101bbb001000101BBBCCCCCC111110. */ +{ "vasrs2h", 0x2822803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vasrs2h<.cc> b,b,c 00101bbb111000101BBBCCCCCC0QQQQQ. */ +{ "vasrs2h", 0x28E28000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vasrs2h a,b,u6 00101bbb011000101BBBuuuuuuAAAAAA. */ +{ "vasrs2h", 0x28628000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vasrs2h 0,b,u6 00101bbb011000101BBBuuuuuu111110. */ +{ "vasrs2h", 0x2862803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vasrs2h<.cc> b,b,u6 00101bbb111000101BBBuuuuuu1QQQQQ. */ +{ "vasrs2h", 0x28E28020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vasrs2h b,b,s12 00101bbb101000101BBBssssssSSSSSS. */ +{ "vasrs2h", 0x28A28000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vasrs2h a,limm,c 00101110001000101111CCCCCCAAAAAA. */ +{ "vasrs2h", 0x2E22F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vasrs2h a,b,limm 00101bbb001000101BBB111110AAAAAA. */ +{ "vasrs2h", 0x28228F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vasrs2h 0,limm,c 00101110011000101111CCCCCC111110. */ +{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vasrs2h 0,b,limm 00101bbb001000101BBB111110111110. */ +{ "vasrs2h", 0x28228FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vasrs2h<.cc> b,b,limm 00101bbb111000101BBB1111100QQQQQ. */ +{ "vasrs2h", 0x28E28F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vasrs2h<.cc> 0,limm,c 00101110111000101111CCCCCC0QQQQQ. */ +{ "vasrs2h", 0x2EE2F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vasrs2h a,limm,u6 00101110011000101111uuuuuuAAAAAA. */ +{ "vasrs2h", 0x2E62F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasrs2h 0,limm,u6 00101110011000101111uuuuuu111110. */ +{ "vasrs2h", 0x2E62F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasrs2h<.cc> 0,limm,u6 00101110111000101111uuuuuu1QQQQQ. */ +{ "vasrs2h", 0x2EE2F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vasrs2h 0,limm,s12 00101110101000101111ssssssSSSSSS. */ +{ "vasrs2h", 0x2EA2F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vasrs2h a,limm,limm 00101110001000101111111110AAAAAA. */ +{ "vasrs2h", 0x2E22FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vasrs2h 0,limm,limm 00101110001000101111111110111110. */ +{ "vasrs2h", 0x2E22FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vasrs2h<.cc> 0,limm,limm 001011101110001011111111100QQQQQ. */ +{ "vasrs2h", 0x2EE2FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vasrsr2h a,b,c 00101bbb001000111BBBCCCCCCAAAAAA. */ +{ "vasrsr2h", 0x28238000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vasrsr2h 0,b,c 00101bbb001000111BBBCCCCCC111110. */ +{ "vasrsr2h", 0x2823803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vasrsr2h<.cc> b,b,c 00101bbb111000111BBBCCCCCC0QQQQQ. */ +{ "vasrsr2h", 0x28E38000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vasrsr2h a,b,u6 00101bbb011000111BBBuuuuuuAAAAAA. */ +{ "vasrsr2h", 0x28638000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vasrsr2h 0,b,u6 00101bbb011000111BBBuuuuuu111110. */ +{ "vasrsr2h", 0x2863803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vasrsr2h<.cc> b,b,u6 00101bbb111000111BBBuuuuuu1QQQQQ. */ +{ "vasrsr2h", 0x28E38020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vasrsr2h b,b,s12 00101bbb101000111BBBssssssSSSSSS. */ +{ "vasrsr2h", 0x28A38000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vasrsr2h a,limm,c 00101110001000111111CCCCCCAAAAAA. */ +{ "vasrsr2h", 0x2E23F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vasrsr2h a,b,limm 00101bbb001000111BBB111110AAAAAA. */ +{ "vasrsr2h", 0x28238F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vasrsr2h 0,limm,c 00101110011000111111CCCCCC111110. */ +{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vasrsr2h 0,b,limm 00101bbb001000111BBB111110111110. */ +{ "vasrsr2h", 0x28238FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vasrsr2h<.cc> b,b,limm 00101bbb111000111BBB1111100QQQQQ. */ +{ "vasrsr2h", 0x28E38F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vasrsr2h<.cc> 0,limm,c 00101110111000111111CCCCCC0QQQQQ. */ +{ "vasrsr2h", 0x2EE3F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vasrsr2h a,limm,u6 00101110011000111111uuuuuuAAAAAA. */ +{ "vasrsr2h", 0x2E63F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasrsr2h 0,limm,u6 00101110011000111111uuuuuu111110. */ +{ "vasrsr2h", 0x2E63F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vasrsr2h<.cc> 0,limm,u6 00101110111000111111uuuuuu1QQQQQ. */ +{ "vasrsr2h", 0x2EE3F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vasrsr2h 0,limm,s12 00101110101000111111ssssssSSSSSS. */ +{ "vasrsr2h", 0x2EA3F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vasrsr2h a,limm,limm 00101110001000111111111110AAAAAA. */ +{ "vasrsr2h", 0x2E23FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vasrsr2h 0,limm,limm 00101110001000111111111110111110. */ +{ "vasrsr2h", 0x2E23FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vasrsr2h<.cc> 0,limm,limm 001011101110001111111111100QQQQQ. */ +{ "vasrsr2h", 0x2EE3FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vbfdw<.f> b,c 00101bbb00101111FBBBCCCCCC001010. */ +{ "vbfdw", 0x282F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, RC }, { C_F }}, + +/* vbfdw<.f> 0,c 0010111000101111F111CCCCCC001010. */ +{ "vbfdw", 0x2E2F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, RC }, { C_F }}, + +/* vbfdw<.f> b,u6 00101bbb01101111FBBBuuuuuu001010. */ +{ "vbfdw", 0x286F000A, 0xF8FF003F, ARC_OPCODE_ARC600, DSP, NONE, { RB, UIMM6_20 }, { C_F }}, + +/* vbfdw<.f> 0,u6 0010111001101111F111uuuuuu001010. */ +{ "vbfdw", 0x2E6F700A, 0xFFFF703F, ARC_OPCODE_ARC600, DSP, NONE, { ZA, UIMM6_20 }, { C_F }}, + +/* vbfdw<.f> b,limm 00101bbb00101111FBBB111110001010. */ +{ "vbfdw", 0x282F0F8A, 0xF8FF0FFF, ARC_OPCODE_ARC600, DSP, NONE, { RB, LIMM }, { C_F }}, + +/* vbfdw<.f> 0,limm 0010111000101111F111111110001010. */ +{ "vbfdw", 0x2E2F7F8A, 0xFFFF7FFF, ARC_OPCODE_ARC600, DSP, NONE, { ZA, LIMM }, { C_F }}, + +/* vext2bhl b,c 00101bbb001011110BBBCCCCCC100100. */ +{ "vext2bhl", 0x282F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vext2bhl 0,c 00101110001011110111CCCCCC100100. */ +{ "vext2bhl", 0x2E2F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vext2bhl b,u6 00101bbb011011110BBBuuuuuu100100. */ +{ "vext2bhl", 0x286F0024, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vext2bhl 0,u6 00101110011011110111uuuuuu100100. */ +{ "vext2bhl", 0x2E6F7024, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vext2bhl b,limm 00101bbb001011110BBB111110100100. */ +{ "vext2bhl", 0x282F0FA4, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vext2bhl 0,limm 00101110001011110111111110100100. */ +{ "vext2bhl", 0x2E2F7FA4, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vext2bhm b,c 00101bbb001011110BBBCCCCCC100101. */ +{ "vext2bhm", 0x282F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vext2bhm 0,c 00101110001011110111CCCCCC100101. */ +{ "vext2bhm", 0x2E2F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vext2bhm b,u6 00101bbb011011110BBBuuuuuu100101. */ +{ "vext2bhm", 0x286F0025, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vext2bhm 0,u6 00101110011011110111uuuuuu100101. */ +{ "vext2bhm", 0x2E6F7025, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vext2bhm b,limm 00101bbb001011110BBB111110100101. */ +{ "vext2bhm", 0x282F0FA5, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vext2bhm 0,limm 00101110001011110111111110100101. */ +{ "vext2bhm", 0x2E2F7FA5, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vlsr2h a,b,c 00101bbb001000110BBBCCCCCCAAAAAA. */ +{ "vlsr2h", 0x28230000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vlsr2h 0,b,c 00101bbb001000110BBBCCCCCC111110. */ +{ "vlsr2h", 0x2823003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vlsr2h<.cc> b,b,c 00101bbb111000110BBBCCCCCC0QQQQQ. */ +{ "vlsr2h", 0x28E30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vlsr2h a,b,u6 00101bbb011000110BBBuuuuuuAAAAAA. */ +{ "vlsr2h", 0x28630000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vlsr2h 0,b,u6 00101bbb011000110BBBuuuuuu111110. */ +{ "vlsr2h", 0x2863003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vlsr2h<.cc> b,b,u6 00101bbb111000110BBBuuuuuu1QQQQQ. */ +{ "vlsr2h", 0x28E30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vlsr2h b,b,s12 00101bbb101000110BBBssssssSSSSSS. */ +{ "vlsr2h", 0x28A30000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vlsr2h a,limm,c 00101110001000110111CCCCCCAAAAAA. */ +{ "vlsr2h", 0x2E237000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vlsr2h a,b,limm 00101bbb001000110BBB111110AAAAAA. */ +{ "vlsr2h", 0x28230F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vlsr2h 0,limm,c 00101110011000110111CCCCCC111110. */ +{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vlsr2h 0,b,limm 00101bbb001000110BBB111110111110. */ +{ "vlsr2h", 0x28230FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vlsr2h<.cc> b,b,limm 00101bbb111000110BBB1111100QQQQQ. */ +{ "vlsr2h", 0x28E30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vlsr2h<.cc> 0,limm,c 00101110111000110111CCCCCC0QQQQQ. */ +{ "vlsr2h", 0x2EE37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vlsr2h a,limm,u6 00101110011000110111uuuuuuAAAAAA. */ +{ "vlsr2h", 0x2E637000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vlsr2h 0,limm,u6 00101110011000110111uuuuuu111110. */ +{ "vlsr2h", 0x2E63703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vlsr2h<.cc> 0,limm,u6 00101110111000110111uuuuuu1QQQQQ. */ +{ "vlsr2h", 0x2EE37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vlsr2h 0,limm,s12 00101110101000110111ssssssSSSSSS. */ +{ "vlsr2h", 0x2EA37000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vlsr2h a,limm,limm 00101110001000110111111110AAAAAA. */ +{ "vlsr2h", 0x2E237F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vlsr2h 0,limm,limm 00101110001000110111111110111110. */ +{ "vlsr2h", 0x2E237FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vlsr2h<.cc> 0,limm,limm 001011101110001101111111100QQQQQ. */ +{ "vlsr2h", 0x2EE37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmac2h a,b,c 00101bbb000111100BBBCCCCCCAAAAAA. */ +{ "vmac2h", 0x281E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmac2h 0,b,c 00101bbb000111100BBBCCCCCC111110. */ +{ "vmac2h", 0x281E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmac2h<.cc> b,b,c 00101bbb110111100BBBCCCCCC0QQQQQ. */ +{ "vmac2h", 0x28DE0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmac2h a,b,u6 00101bbb010111100BBBuuuuuuAAAAAA. */ +{ "vmac2h", 0x285E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2h 0,b,u6 00101bbb010111100BBBuuuuuu111110. */ +{ "vmac2h", 0x285E003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2h<.cc> b,b,u6 00101bbb110111100BBBuuuuuu1QQQQQ. */ +{ "vmac2h", 0x28DE0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmac2h b,b,s12 00101bbb100111100BBBssssssSSSSSS. */ +{ "vmac2h", 0x289E0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmac2h a,limm,c 00101110000111100111CCCCCCAAAAAA. */ +{ "vmac2h", 0x2E1E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmac2h a,b,limm 00101bbb000111100BBB111110AAAAAA. */ +{ "vmac2h", 0x281E0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmac2h 0,limm,c 00101110000111100111CCCCCC111110. */ +{ "vmac2h", 0x2E1E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmac2h 0,b,limm 00101bbb000111100BBB111110111110. */ +{ "vmac2h", 0x281E0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmac2h<.cc> b,b,limm 00101bbb110111100BBB1111100QQQQQ. */ +{ "vmac2h", 0x28DE0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmac2h<.cc> 0,limm,c 00101110110111100111CCCCCC0QQQQQ. */ +{ "vmac2h", 0x2EDE7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmac2h a,limm,u6 00101110010111100111uuuuuuAAAAAA. */ +{ "vmac2h", 0x2E5E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2h 0,limm,u6 00101110010111100111uuuuuu111110. */ +{ "vmac2h", 0x2E5E703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2h<.cc> 0,limm,u6 00101110110111100111uuuuuu1QQQQQ. */ +{ "vmac2h", 0x2EDE7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmac2h 0,limm,s12 00101110100111100111ssssssSSSSSS. */ +{ "vmac2h", 0x2E9E7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmac2h a,limm,limm 00101110000111100111111110AAAAAA. */ +{ "vmac2h", 0x2E1E7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2h 0,limm,limm 00101110000111100111111110111110. */ +{ "vmac2h", 0x2E1E7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2h<.cc> 0,limm,limm 001011101101111001111111100QQQQQ. */ +{ "vmac2h", 0x2EDE7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmac2hf a,b,c 00101bbb000111101BBBCCCCCCAAAAAA. */ +{ "vmac2hf", 0x281E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmac2hf 0,b,c 00101bbb000111101BBBCCCCCC111110. */ +{ "vmac2hf", 0x281E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmac2hf<.cc> b,b,c 00101bbb110111101BBBCCCCCC0QQQQQ. */ +{ "vmac2hf", 0x28DE8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmac2hf a,b,u6 00101bbb010111101BBBuuuuuuAAAAAA. */ +{ "vmac2hf", 0x285E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hf 0,b,u6 00101bbb010111101BBBuuuuuu111110. */ +{ "vmac2hf", 0x285E803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hf<.cc> b,b,u6 00101bbb110111101BBBuuuuuu1QQQQQ. */ +{ "vmac2hf", 0x28DE8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmac2hf b,b,s12 00101bbb100111101BBBssssssSSSSSS. */ +{ "vmac2hf", 0x289E8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmac2hf a,limm,c 00101110000111101111CCCCCCAAAAAA. */ +{ "vmac2hf", 0x2E1EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmac2hf a,b,limm 00101bbb000111101BBB111110AAAAAA. */ +{ "vmac2hf", 0x281E8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmac2hf 0,limm,c 00101110000111101111CCCCCC111110. */ +{ "vmac2hf", 0x2E1EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmac2hf 0,b,limm 00101bbb000111101BBB111110111110. */ +{ "vmac2hf", 0x281E8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmac2hf<.cc> b,b,limm 00101bbb110111101BBB1111100QQQQQ. */ +{ "vmac2hf", 0x28DE8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmac2hf<.cc> 0,limm,c 00101110110111101111CCCCCC0QQQQQ. */ +{ "vmac2hf", 0x2EDEF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmac2hf a,limm,u6 00101110010111101111uuuuuuAAAAAA. */ +{ "vmac2hf", 0x2E5EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hf 0,limm,u6 00101110010111101111uuuuuu111110. */ +{ "vmac2hf", 0x2E5EF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hf<.cc> 0,limm,u6 00101110110111101111uuuuuu1QQQQQ. */ +{ "vmac2hf", 0x2EDEF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmac2hf 0,limm,s12 00101110100111101111ssssssSSSSSS. */ +{ "vmac2hf", 0x2E9EF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmac2hf a,limm,limm 00101110000111101111111110AAAAAA. */ +{ "vmac2hf", 0x2E1EFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hf 0,limm,limm 00101110000111101111111110111110. */ +{ "vmac2hf", 0x2E1EFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hf<.cc> 0,limm,limm 001011101101111011111111100QQQQQ. */ +{ "vmac2hf", 0x2EDEFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmac2hfr a,b,c 00101bbb000111111BBBCCCCCCAAAAAA. */ +{ "vmac2hfr", 0x281F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmac2hfr 0,b,c 00101bbb000111111BBBCCCCCC111110. */ +{ "vmac2hfr", 0x281F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmac2hfr<.cc> b,b,c 00101bbb110111111BBBCCCCCC0QQQQQ. */ +{ "vmac2hfr", 0x28DF8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmac2hfr a,b,u6 00101bbb010111111BBBuuuuuuAAAAAA. */ +{ "vmac2hfr", 0x285F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hfr 0,b,u6 00101bbb010111111BBBuuuuuu111110. */ +{ "vmac2hfr", 0x285F803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hfr<.cc> b,b,u6 00101bbb110111111BBBuuuuuu1QQQQQ. */ +{ "vmac2hfr", 0x28DF8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmac2hfr b,b,s12 00101bbb100111111BBBssssssSSSSSS. */ +{ "vmac2hfr", 0x289F8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmac2hfr a,limm,c 00101110000111111111CCCCCCAAAAAA. */ +{ "vmac2hfr", 0x2E1FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmac2hfr a,b,limm 00101bbb000111111BBB111110AAAAAA. */ +{ "vmac2hfr", 0x281F8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmac2hfr 0,limm,c 00101110000111111111CCCCCC111110. */ +{ "vmac2hfr", 0x2E1FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmac2hfr 0,b,limm 00101bbb000111111BBB111110111110. */ +{ "vmac2hfr", 0x281F8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmac2hfr<.cc> b,b,limm 00101bbb110111111BBB1111100QQQQQ. */ +{ "vmac2hfr", 0x28DF8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmac2hfr<.cc> 0,limm,c 00101110110111111111CCCCCC0QQQQQ. */ +{ "vmac2hfr", 0x2EDFF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmac2hfr a,limm,u6 00101110010111111111uuuuuuAAAAAA. */ +{ "vmac2hfr", 0x2E5FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hfr 0,limm,u6 00101110010111111111uuuuuu111110. */ +{ "vmac2hfr", 0x2E5FF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hfr<.cc> 0,limm,u6 00101110110111111111uuuuuu1QQQQQ. */ +{ "vmac2hfr", 0x2EDFF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmac2hfr 0,limm,s12 00101110100111111111ssssssSSSSSS. */ +{ "vmac2hfr", 0x2E9FF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmac2hfr a,limm,limm 00101110000111111111111110AAAAAA. */ +{ "vmac2hfr", 0x2E1FFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hfr 0,limm,limm 00101110000111111111111110111110. */ +{ "vmac2hfr", 0x2E1FFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hfr<.cc> 0,limm,limm 001011101101111111111111100QQQQQ. */ +{ "vmac2hfr", 0x2EDFFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmac2hnfr a,b,c 00110bbb000100010BBBCCCCCCAAAAAA. */ +{ "vmac2hnfr", 0x30110000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmac2hnfr 0,b,c 00110bbb000100010BBBCCCCCC111110. */ +{ "vmac2hnfr", 0x3011003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,c 00110bbb110100010BBBCCCCCC0QQQQQ. */ +{ "vmac2hnfr", 0x30D10000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmac2hnfr a,b,u6 00110bbb010100010BBBuuuuuuAAAAAA. */ +{ "vmac2hnfr", 0x30510000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hnfr 0,b,u6 00110bbb010100010BBBuuuuuu111110. */ +{ "vmac2hnfr", 0x3051003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,u6 00110bbb110100010BBBuuuuuu1QQQQQ. */ +{ "vmac2hnfr", 0x30D10020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmac2hnfr b,b,s12 00110bbb100100010BBBssssssSSSSSS. */ +{ "vmac2hnfr", 0x30910000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmac2hnfr a,limm,c 00110110000100010111CCCCCCAAAAAA. */ +{ "vmac2hnfr", 0x36117000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmac2hnfr a,b,limm 00110bbb000100010BBB111110AAAAAA. */ +{ "vmac2hnfr", 0x30110F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmac2hnfr 0,limm,c 00110110000100010111CCCCCC111110. */ +{ "vmac2hnfr", 0x3611703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmac2hnfr 0,b,limm 00110bbb000100010BBB111110111110. */ +{ "vmac2hnfr", 0x30110FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmac2hnfr<.cc> b,b,limm 00110bbb110100010BBB1111100QQQQQ. */ +{ "vmac2hnfr", 0x30D10F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmac2hnfr<.cc> 0,limm,c 00110110110100010111CCCCCC0QQQQQ. */ +{ "vmac2hnfr", 0x36D17000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmac2hnfr a,limm,u6 00110110010100010111uuuuuuAAAAAA. */ +{ "vmac2hnfr", 0x36517000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hnfr 0,limm,u6 00110110010100010111uuuuuu111110. */ +{ "vmac2hnfr", 0x3651703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hnfr<.cc> 0,limm,u6 00110110110100010111uuuuuu1QQQQQ. */ +{ "vmac2hnfr", 0x36D17020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmac2hnfr 0,limm,s12 00110110100100010111ssssssSSSSSS. */ +{ "vmac2hnfr", 0x36917000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmac2hnfr a,limm,limm 00110110000100010111111110AAAAAA. */ +{ "vmac2hnfr", 0x36117F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hnfr 0,limm,limm 00110110000100010111111110111110. */ +{ "vmac2hnfr", 0x36117FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hnfr<.cc> 0,limm,limm 001101101101000101111111100QQQQQ. */ +{ "vmac2hnfr", 0x36D17F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmac2hu a,b,c 00101bbb000111110BBBCCCCCCAAAAAA. */ +{ "vmac2hu", 0x281F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmac2hu 0,b,c 00101bbb000111110BBBCCCCCC111110. */ +{ "vmac2hu", 0x281F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmac2hu<.cc> b,b,c 00101bbb110111110BBBCCCCCC0QQQQQ. */ +{ "vmac2hu", 0x28DF0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmac2hu a,b,u6 00101bbb010111110BBBuuuuuuAAAAAA. */ +{ "vmac2hu", 0x285F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hu 0,b,u6 00101bbb010111110BBBuuuuuu111110. */ +{ "vmac2hu", 0x285F003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmac2hu<.cc> b,b,u6 00101bbb110111110BBBuuuuuu1QQQQQ. */ +{ "vmac2hu", 0x28DF0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmac2hu b,b,s12 00101bbb100111110BBBssssssSSSSSS. */ +{ "vmac2hu", 0x289F0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmac2hu a,limm,c 00101110000111110111CCCCCCAAAAAA. */ +{ "vmac2hu", 0x2E1F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmac2hu a,b,limm 00101bbb000111110BBB111110AAAAAA. */ +{ "vmac2hu", 0x281F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmac2hu 0,limm,c 00101110000111110111CCCCCC111110. */ +{ "vmac2hu", 0x2E1F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmac2hu 0,b,limm 00101bbb000111110BBB111110111110. */ +{ "vmac2hu", 0x281F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmac2hu<.cc> b,b,limm 00101bbb110111110BBB1111100QQQQQ. */ +{ "vmac2hu", 0x28DF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmac2hu<.cc> 0,limm,c 00101110110111110111CCCCCC0QQQQQ. */ +{ "vmac2hu", 0x2EDF7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmac2hu a,limm,u6 00101110010111110111uuuuuuAAAAAA. */ +{ "vmac2hu", 0x2E5F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hu 0,limm,u6 00101110010111110111uuuuuu111110. */ +{ "vmac2hu", 0x2E5F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmac2hu<.cc> 0,limm,u6 00101110110111110111uuuuuu1QQQQQ. */ +{ "vmac2hu", 0x2EDF7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmac2hu 0,limm,s12 00101110100111110111ssssssSSSSSS. */ +{ "vmac2hu", 0x2E9F7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmac2hu a,limm,limm 00101110000111110111111110AAAAAA. */ +{ "vmac2hu", 0x2E1F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hu 0,limm,limm 00101110000111110111111110111110. */ +{ "vmac2hu", 0x2E1F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmac2hu<.cc> 0,limm,limm 001011101101111101111111100QQQQQ. */ +{ "vmac2hu", 0x2EDF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmax2h a,b,c 00101bbb001001001BBBCCCCCCAAAAAA. */ +{ "vmax2h", 0x28248000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmax2h 0,b,c 00101bbb001001001BBBCCCCCC111110. */ +{ "vmax2h", 0x2824803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmax2h<.cc> b,b,c 00101bbb111001001BBBCCCCCC0QQQQQ. */ +{ "vmax2h", 0x28E48000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmax2h a,b,u6 00101bbb011001001BBBuuuuuuAAAAAA. */ +{ "vmax2h", 0x28648000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmax2h 0,b,u6 00101bbb011001001BBBuuuuuu111110. */ +{ "vmax2h", 0x2864803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmax2h<.cc> b,b,u6 00101bbb111001001BBBuuuuuu1QQQQQ. */ +{ "vmax2h", 0x28E48020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmax2h b,b,s12 00101bbb101001001BBBssssssSSSSSS. */ +{ "vmax2h", 0x28A48000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmax2h a,limm,c 00101110001001001111CCCCCCAAAAAA. */ +{ "vmax2h", 0x2E24F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmax2h a,b,limm 00101bbb001001001BBB111110AAAAAA. */ +{ "vmax2h", 0x28248F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmax2h 0,limm,c 00101110011001001111CCCCCC111110. */ +{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmax2h 0,b,limm 00101bbb001001001BBB111110111110. */ +{ "vmax2h", 0x28248FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmax2h<.cc> b,b,limm 00101bbb111001001BBB1111100QQQQQ. */ +{ "vmax2h", 0x28E48F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmax2h<.cc> 0,limm,c 00101110111001001111CCCCCC0QQQQQ. */ +{ "vmax2h", 0x2EE4F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmax2h a,limm,u6 00101110011001001111uuuuuuAAAAAA. */ +{ "vmax2h", 0x2E64F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmax2h 0,limm,u6 00101110011001001111uuuuuu111110. */ +{ "vmax2h", 0x2E64F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmax2h<.cc> 0,limm,u6 00101110111001001111uuuuuu1QQQQQ. */ +{ "vmax2h", 0x2EE4F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmax2h 0,limm,s12 00101110101001001111ssssssSSSSSS. */ +{ "vmax2h", 0x2EA4F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmax2h a,limm,limm 00101110001001001111111110AAAAAA. */ +{ "vmax2h", 0x2E24FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmax2h 0,limm,limm 00101110001001001111111110111110. */ +{ "vmax2h", 0x2E24FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmax2h<.cc> 0,limm,limm 001011101110010011111111100QQQQQ. */ +{ "vmax2h", 0x2EE4FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmin2h a,b,c 00101bbb001001011BBBCCCCCCAAAAAA. */ +{ "vmin2h", 0x28258000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmin2h 0,b,c 00101bbb001001011BBBCCCCCC111110. */ +{ "vmin2h", 0x2825803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmin2h<.cc> b,b,c 00101bbb111001011BBBCCCCCC0QQQQQ. */ +{ "vmin2h", 0x28E58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmin2h a,b,u6 00101bbb011001011BBBuuuuuuAAAAAA. */ +{ "vmin2h", 0x28658000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmin2h 0,b,u6 00101bbb011001011BBBuuuuuu111110. */ +{ "vmin2h", 0x2865803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmin2h<.cc> b,b,u6 00101bbb111001011BBBuuuuuu1QQQQQ. */ +{ "vmin2h", 0x28E58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmin2h b,b,s12 00101bbb101001011BBBssssssSSSSSS. */ +{ "vmin2h", 0x28A58000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmin2h a,limm,c 00101110001001011111CCCCCCAAAAAA. */ +{ "vmin2h", 0x2E25F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmin2h a,b,limm 00101bbb001001011BBB111110AAAAAA. */ +{ "vmin2h", 0x28258F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmin2h 0,limm,c 00101110011001011111CCCCCC111110. */ +{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmin2h 0,b,limm 00101bbb001001011BBB111110111110. */ +{ "vmin2h", 0x28258FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmin2h<.cc> b,b,limm 00101bbb111001011BBB1111100QQQQQ. */ +{ "vmin2h", 0x28E58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmin2h<.cc> 0,limm,c 00101110111001011111CCCCCC0QQQQQ. */ +{ "vmin2h", 0x2EE5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmin2h a,limm,u6 00101110011001011111uuuuuuAAAAAA. */ +{ "vmin2h", 0x2E65F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmin2h 0,limm,u6 00101110011001011111uuuuuu111110. */ +{ "vmin2h", 0x2E65F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmin2h<.cc> 0,limm,u6 00101110111001011111uuuuuu1QQQQQ. */ +{ "vmin2h", 0x2EE5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmin2h 0,limm,s12 00101110101001011111ssssssSSSSSS. */ +{ "vmin2h", 0x2EA5F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmin2h a,limm,limm 00101110001001011111111110AAAAAA. */ +{ "vmin2h", 0x2E25FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmin2h 0,limm,limm 00101110001001011111111110111110. */ +{ "vmin2h", 0x2E25FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmin2h<.cc> 0,limm,limm 001011101110010111111111100QQQQQ. */ +{ "vmin2h", 0x2EE5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ +{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ +{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ +{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2h a,b,c 00101bbb000111000BBBCCCCCCAAAAAA. */ +{ "vmpy2h", 0x281C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { 0 }}, + +/* vmpy2h 0,b,c 00101bbb000111000BBBCCCCCC111110. */ +{ "vmpy2h", 0x281C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { 0 }}, + +/* vmpy2h<.cc> b,b,c 00101bbb110111000BBBCCCCCC0QQQQQ. */ +{ "vmpy2h", 0x28DC0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ +{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ +{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ +{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2h a,b,u6 00101bbb010111000BBBuuuuuuAAAAAA. */ +{ "vmpy2h", 0x285C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,b,u6 00101bbb010111000BBBuuuuuu111110. */ +{ "vmpy2h", 0x285C003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> b,b,u6 00101bbb110111000BBBuuuuuu1QQQQQ. */ +{ "vmpy2h", 0x28DC0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ +{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2h b,b,s12 00101bbb100111000BBBssssssSSSSSS. */ +{ "vmpy2h", 0x289C0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ +{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ +{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ +{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ +{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ +{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ +{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2h a,limm,c 00101110000111000111CCCCCCAAAAAA. */ +{ "vmpy2h", 0x2E1C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2h a,b,limm 00101bbb000111000BBB111110AAAAAA. */ +{ "vmpy2h", 0x281C0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2h 0,limm,c 00101110000111000111CCCCCC111110. */ +{ "vmpy2h", 0x2E1C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2h 0,b,limm 00101bbb000111000BBB111110111110. */ +{ "vmpy2h", 0x281C0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2h<.cc> b,b,limm 00101bbb110111000BBB1111100QQQQQ. */ +{ "vmpy2h", 0x28DC0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2h<.cc> 0,limm,c 00101110110111000111CCCCCC0QQQQQ. */ +{ "vmpy2h", 0x2EDC7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ +{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ +{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ +{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2h a,limm,u6 00101110010111000111uuuuuuAAAAAA. */ +{ "vmpy2h", 0x2E5C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2h 0,limm,u6 00101110010111000111uuuuuu111110. */ +{ "vmpy2h", 0x2E5C703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,u6 00101110110111000111uuuuuu1QQQQQ. */ +{ "vmpy2h", 0x2EDC7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ +{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2h 0,limm,s12 00101110100111000111ssssssSSSSSS. */ +{ "vmpy2h", 0x2E9C7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ +{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ +{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ +{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2h a,limm,limm 00101110000111000111111110AAAAAA. */ +{ "vmpy2h", 0x2E1C7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2h 0,limm,limm 00101110000111000111111110111110. */ +{ "vmpy2h", 0x2E1C7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2h<.cc> 0,limm,limm 001011101101110001111111100QQQQQ. */ +{ "vmpy2h", 0x2EDC7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2hf a,b,c 00101bbb000111001BBBCCCCCCAAAAAA. */ +{ "vmpy2hf", 0x281C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmpy2hf 0,b,c 00101bbb000111001BBBCCCCCC111110. */ +{ "vmpy2hf", 0x281C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmpy2hf<.cc> b,b,c 00101bbb110111001BBBCCCCCC0QQQQQ. */ +{ "vmpy2hf", 0x28DC8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2hf a,b,u6 00101bbb010111001BBBuuuuuuAAAAAA. */ +{ "vmpy2hf", 0x285C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hf 0,b,u6 00101bbb010111001BBBuuuuuu111110. */ +{ "vmpy2hf", 0x285C803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hf<.cc> b,b,u6 00101bbb110111001BBBuuuuuu1QQQQQ. */ +{ "vmpy2hf", 0x28DC8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2hf b,b,s12 00101bbb100111001BBBssssssSSSSSS. */ +{ "vmpy2hf", 0x289C8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2hf a,limm,c 00101110000111001111CCCCCCAAAAAA. */ +{ "vmpy2hf", 0x2E1CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2hf a,b,limm 00101bbb000111001BBB111110AAAAAA. */ +{ "vmpy2hf", 0x281C8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2hf 0,limm,c 00101110000111001111CCCCCC111110. */ +{ "vmpy2hf", 0x2E1CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2hf 0,b,limm 00101bbb000111001BBB111110111110. */ +{ "vmpy2hf", 0x281C8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2hf<.cc> b,b,limm 00101bbb110111001BBB1111100QQQQQ. */ +{ "vmpy2hf", 0x28DC8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2hf<.cc> 0,limm,c 00101110110111001111CCCCCC0QQQQQ. */ +{ "vmpy2hf", 0x2EDCF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2hf a,limm,u6 00101110010111001111uuuuuuAAAAAA. */ +{ "vmpy2hf", 0x2E5CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hf 0,limm,u6 00101110010111001111uuuuuu111110. */ +{ "vmpy2hf", 0x2E5CF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hf<.cc> 0,limm,u6 00101110110111001111uuuuuu1QQQQQ. */ +{ "vmpy2hf", 0x2EDCF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2hf 0,limm,s12 00101110100111001111ssssssSSSSSS. */ +{ "vmpy2hf", 0x2E9CF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2hf a,limm,limm 00101110000111001111111110AAAAAA. */ +{ "vmpy2hf", 0x2E1CFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hf 0,limm,limm 00101110000111001111111110111110. */ +{ "vmpy2hf", 0x2E1CFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hf<.cc> 0,limm,limm 001011101101110011111111100QQQQQ. */ +{ "vmpy2hf", 0x2EDCFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2hfr a,b,c 00101bbb000111011BBBCCCCCCAAAAAA. */ +{ "vmpy2hfr", 0x281D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmpy2hfr 0,b,c 00101bbb000111011BBBCCCCCC111110. */ +{ "vmpy2hfr", 0x281D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,c 00101bbb110111011BBBCCCCCC0QQQQQ. */ +{ "vmpy2hfr", 0x28DD8000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2hfr a,b,u6 00101bbb010111011BBBuuuuuuAAAAAA. */ +{ "vmpy2hfr", 0x285D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hfr 0,b,u6 00101bbb010111011BBBuuuuuu111110. */ +{ "vmpy2hfr", 0x285D803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,u6 00101bbb110111011BBBuuuuuu1QQQQQ. */ +{ "vmpy2hfr", 0x28DD8020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2hfr b,b,s12 00101bbb100111011BBBssssssSSSSSS. */ +{ "vmpy2hfr", 0x289D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2hfr a,limm,c 00101110000111011111CCCCCCAAAAAA. */ +{ "vmpy2hfr", 0x2E1DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2hfr a,b,limm 00101bbb000111011BBB111110AAAAAA. */ +{ "vmpy2hfr", 0x281D8F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2hfr 0,limm,c 00101110000111011111CCCCCC111110. */ +{ "vmpy2hfr", 0x2E1DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2hfr 0,b,limm 00101bbb000111011BBB111110111110. */ +{ "vmpy2hfr", 0x281D8FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2hfr<.cc> b,b,limm 00101bbb110111011BBB1111100QQQQQ. */ +{ "vmpy2hfr", 0x28DD8F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2hfr<.cc> 0,limm,c 00101110110111011111CCCCCC0QQQQQ. */ +{ "vmpy2hfr", 0x2EDDF000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2hfr a,limm,u6 00101110010111011111uuuuuuAAAAAA. */ +{ "vmpy2hfr", 0x2E5DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hfr 0,limm,u6 00101110010111011111uuuuuu111110. */ +{ "vmpy2hfr", 0x2E5DF03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hfr<.cc> 0,limm,u6 00101110110111011111uuuuuu1QQQQQ. */ +{ "vmpy2hfr", 0x2EDDF020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2hfr 0,limm,s12 00101110100111011111ssssssSSSSSS. */ +{ "vmpy2hfr", 0x2E9DF000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2hfr a,limm,limm 00101110000111011111111110AAAAAA. */ +{ "vmpy2hfr", 0x2E1DFF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hfr 0,limm,limm 00101110000111011111111110111110. */ +{ "vmpy2hfr", 0x2E1DFFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hfr<.cc> 0,limm,limm 001011101101110111111111100QQQQQ. */ +{ "vmpy2hfr", 0x2EDDFF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ +{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ +{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2hu a,b,c 00101bbb000111010BBBCCCCCCAAAAAA. */ +{ "vmpy2hu", 0x281D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, RC }, { 0 }}, + +/* vmpy2hu 0,b,c 00101bbb000111010BBBCCCCCC111110. */ +{ "vmpy2hu", 0x281D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, RC }, { 0 }}, + +/* vmpy2hu<.cc> b,b,c 00101bbb110111010BBBCCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x28DD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ +{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ +{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2hu a,b,u6 00101bbb010111010BBBuuuuuuAAAAAA. */ +{ "vmpy2hu", 0x285D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,b,u6 00101bbb010111010BBBuuuuuu111110. */ +{ "vmpy2hu", 0x285D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> b,b,u6 00101bbb110111010BBBuuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x28DD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ +{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2hu b,b,s12 00101bbb100111010BBBssssssSSSSSS. */ +{ "vmpy2hu", 0x289D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ +{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ +{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ +{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ +{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ +{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2hu a,limm,c 00101110000111010111CCCCCCAAAAAA. */ +{ "vmpy2hu", 0x2E1D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2hu a,b,limm 00101bbb000111010BBB111110AAAAAA. */ +{ "vmpy2hu", 0x281D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2hu 0,limm,c 00101110000111010111CCCCCC111110. */ +{ "vmpy2hu", 0x2E1D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2hu 0,b,limm 00101bbb000111010BBB111110111110. */ +{ "vmpy2hu", 0x281D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2hu<.cc> b,b,limm 00101bbb110111010BBB1111100QQQQQ. */ +{ "vmpy2hu", 0x28DD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2hu<.cc> 0,limm,c 00101110110111010111CCCCCC0QQQQQ. */ +{ "vmpy2hu", 0x2EDD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ +{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ +{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2hu a,limm,u6 00101110010111010111uuuuuuAAAAAA. */ +{ "vmpy2hu", 0x2E5D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hu 0,limm,u6 00101110010111010111uuuuuu111110. */ +{ "vmpy2hu", 0x2E5D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,u6 00101110110111010111uuuuuu1QQQQQ. */ +{ "vmpy2hu", 0x2EDD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ +{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2hu 0,limm,s12 00101110100111010111ssssssSSSSSS. */ +{ "vmpy2hu", 0x2E9D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ +{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ +{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ +{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2hu a,limm,limm 00101110000111010111111110AAAAAA. */ +{ "vmpy2hu", 0x2E1D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hu 0,limm,limm 00101110000111010111111110111110. */ +{ "vmpy2hu", 0x2E1D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hu<.cc> 0,limm,limm 001011101101110101111111100QQQQQ. */ +{ "vmpy2hu", 0x2EDD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY8E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmpy2hwf a,b,c 00101bbb001000000BBBCCCCCCAAAAAA. */ +{ "vmpy2hwf", 0x28200000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmpy2hwf 0,b,c 00101bbb001000000BBBCCCCCC111110. */ +{ "vmpy2hwf", 0x2820003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,c 00101bbb111000000BBBCCCCCC0QQQQQ. */ +{ "vmpy2hwf", 0x28E00000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmpy2hwf a,b,u6 00101bbb011000000BBBuuuuuuAAAAAA. */ +{ "vmpy2hwf", 0x28600000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hwf 0,b,u6 00101bbb011000000BBBuuuuuu111110. */ +{ "vmpy2hwf", 0x2860003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,u6 00101bbb111000000BBBuuuuuu1QQQQQ. */ +{ "vmpy2hwf", 0x28E00020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmpy2hwf b,b,s12 00101bbb101000000BBBssssssSSSSSS. */ +{ "vmpy2hwf", 0x28A00000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmpy2hwf a,limm,c 00101110001000000111CCCCCCAAAAAA. */ +{ "vmpy2hwf", 0x2E207000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmpy2hwf a,b,limm 00101bbb001000000BBB111110AAAAAA. */ +{ "vmpy2hwf", 0x28200F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmpy2hwf 0,limm,c 00101110011000000111CCCCCC111110. */ +{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmpy2hwf 0,b,limm 00101bbb001000000BBB111110111110. */ +{ "vmpy2hwf", 0x28200FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmpy2hwf<.cc> b,b,limm 00101bbb111000000BBB1111100QQQQQ. */ +{ "vmpy2hwf", 0x28E00F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmpy2hwf<.cc> 0,limm,c 00101110111000000111CCCCCC0QQQQQ. */ +{ "vmpy2hwf", 0x2EE07000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmpy2hwf a,limm,u6 00101110011000000111uuuuuuAAAAAA. */ +{ "vmpy2hwf", 0x2E607000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hwf 0,limm,u6 00101110011000000111uuuuuu111110. */ +{ "vmpy2hwf", 0x2E60703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmpy2hwf<.cc> 0,limm,u6 00101110111000000111uuuuuu1QQQQQ. */ +{ "vmpy2hwf", 0x2EE07020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmpy2hwf 0,limm,s12 00101110101000000111ssssssSSSSSS. */ +{ "vmpy2hwf", 0x2EA07000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmpy2hwf a,limm,limm 00101110001000000111111110AAAAAA. */ +{ "vmpy2hwf", 0x2E207F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hwf 0,limm,limm 00101110001000000111111110111110. */ +{ "vmpy2hwf", 0x2E207FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmpy2hwf<.cc> 0,limm,limm 001011101110000001111111100QQQQQ. */ +{ "vmpy2hwf", 0x2EE07F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmsub2hf a,b,c 00110bbb000001000BBBCCCCCCAAAAAA. */ +{ "vmsub2hf", 0x30040000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmsub2hf 0,b,c 00110bbb000001000BBBCCCCCC111110. */ +{ "vmsub2hf", 0x3004003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmsub2hf<.cc> b,b,c 00110bbb110001000BBBCCCCCC0QQQQQ. */ +{ "vmsub2hf", 0x30C40000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmsub2hf a,b,u6 00110bbb010001000BBBuuuuuuAAAAAA. */ +{ "vmsub2hf", 0x30440000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hf 0,b,u6 00110bbb010001000BBBuuuuuu111110. */ +{ "vmsub2hf", 0x3044003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hf<.cc> b,b,u6 00110bbb110001000BBBuuuuuu1QQQQQ. */ +{ "vmsub2hf", 0x30C40020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmsub2hf b,b,s12 00110bbb100001000BBBssssssSSSSSS. */ +{ "vmsub2hf", 0x30840000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmsub2hf a,limm,c 00110110000001000111CCCCCCAAAAAA. */ +{ "vmsub2hf", 0x36047000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmsub2hf a,b,limm 00110bbb000001000BBB111110AAAAAA. */ +{ "vmsub2hf", 0x30040F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmsub2hf 0,limm,c 00110110000001000111CCCCCC111110. */ +{ "vmsub2hf", 0x3604703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmsub2hf 0,b,limm 00110bbb000001000BBB111110111110. */ +{ "vmsub2hf", 0x30040FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmsub2hf<.cc> b,b,limm 00110bbb110001000BBB1111100QQQQQ. */ +{ "vmsub2hf", 0x30C40F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmsub2hf<.cc> 0,limm,c 00110110110001000111CCCCCC0QQQQQ. */ +{ "vmsub2hf", 0x36C47000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmsub2hf a,limm,u6 00110110010001000111uuuuuuAAAAAA. */ +{ "vmsub2hf", 0x36447000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hf 0,limm,u6 00110110010001000111uuuuuu111110. */ +{ "vmsub2hf", 0x3644703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hf<.cc> 0,limm,u6 00110110110001000111uuuuuu1QQQQQ. */ +{ "vmsub2hf", 0x36C47020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmsub2hf 0,limm,s12 00110110100001000111ssssssSSSSSS. */ +{ "vmsub2hf", 0x36847000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmsub2hf a,limm,limm 00110110000001000111111110AAAAAA. */ +{ "vmsub2hf", 0x36047F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hf 0,limm,limm 00110110000001000111111110111110. */ +{ "vmsub2hf", 0x36047FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hf<.cc> 0,limm,limm 001101101100010001111111100QQQQQ. */ +{ "vmsub2hf", 0x36C47F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmsub2hfr a,b,c 00110bbb000000110BBBCCCCCCAAAAAA. */ +{ "vmsub2hfr", 0x30030000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmsub2hfr 0,b,c 00110bbb000000110BBBCCCCCC111110. */ +{ "vmsub2hfr", 0x3003003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,c 00110bbb110000110BBBCCCCCC0QQQQQ. */ +{ "vmsub2hfr", 0x30C30000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmsub2hfr a,b,u6 00110bbb010000110BBBuuuuuuAAAAAA. */ +{ "vmsub2hfr", 0x30430000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hfr 0,b,u6 00110bbb010000110BBBuuuuuu111110. */ +{ "vmsub2hfr", 0x3043003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,u6 00110bbb110000110BBBuuuuuu1QQQQQ. */ +{ "vmsub2hfr", 0x30C30020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmsub2hfr b,b,s12 00110bbb100000110BBBssssssSSSSSS. */ +{ "vmsub2hfr", 0x30830000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmsub2hfr a,limm,c 00110110000000110111CCCCCCAAAAAA. */ +{ "vmsub2hfr", 0x36037000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmsub2hfr a,b,limm 00110bbb000000110BBB111110AAAAAA. */ +{ "vmsub2hfr", 0x30030F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmsub2hfr 0,limm,c 00110110000000110111CCCCCC111110. */ +{ "vmsub2hfr", 0x3603703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmsub2hfr 0,b,limm 00110bbb000000110BBB111110111110. */ +{ "vmsub2hfr", 0x30030FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmsub2hfr<.cc> b,b,limm 00110bbb110000110BBB1111100QQQQQ. */ +{ "vmsub2hfr", 0x30C30F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmsub2hfr<.cc> 0,limm,c 00110110110000110111CCCCCC0QQQQQ. */ +{ "vmsub2hfr", 0x36C37000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmsub2hfr a,limm,u6 00110110010000110111uuuuuuAAAAAA. */ +{ "vmsub2hfr", 0x36437000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hfr 0,limm,u6 00110110010000110111uuuuuu111110. */ +{ "vmsub2hfr", 0x3643703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hfr<.cc> 0,limm,u6 00110110110000110111uuuuuu1QQQQQ. */ +{ "vmsub2hfr", 0x36C37020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmsub2hfr 0,limm,s12 00110110100000110111ssssssSSSSSS. */ +{ "vmsub2hfr", 0x36837000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmsub2hfr a,limm,limm 00110110000000110111111110AAAAAA. */ +{ "vmsub2hfr", 0x36037F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hfr 0,limm,limm 00110110000000110111111110111110. */ +{ "vmsub2hfr", 0x36037FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hfr<.cc> 0,limm,limm 001101101100001101111111100QQQQQ. */ +{ "vmsub2hfr", 0x36C37F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vmsub2hnfr a,b,c 00110bbb000100011BBBCCCCCCAAAAAA. */ +{ "vmsub2hnfr", 0x30118000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vmsub2hnfr 0,b,c 00110bbb000100011BBBCCCCCC111110. */ +{ "vmsub2hnfr", 0x3011803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,c 00110bbb110100011BBBCCCCCC0QQQQQ. */ +{ "vmsub2hnfr", 0x30D18000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vmsub2hnfr a,b,u6 00110bbb010100011BBBuuuuuuAAAAAA. */ +{ "vmsub2hnfr", 0x30518000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr 0,b,u6 00110bbb010100011BBBuuuuuu111110. */ +{ "vmsub2hnfr", 0x3051803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,u6 00110bbb110100011BBBuuuuuu1QQQQQ. */ +{ "vmsub2hnfr", 0x30D18020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vmsub2hnfr b,b,s12 00110bbb100100011BBBssssssSSSSSS. */ +{ "vmsub2hnfr", 0x30918000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vmsub2hnfr a,limm,c 00110110000100011111CCCCCCAAAAAA. */ +{ "vmsub2hnfr", 0x3611F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vmsub2hnfr a,b,limm 00110bbb000100011BBB111110AAAAAA. */ +{ "vmsub2hnfr", 0x30118F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vmsub2hnfr 0,limm,c 00110110000100011111CCCCCC111110. */ +{ "vmsub2hnfr", 0x3611F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vmsub2hnfr 0,b,limm 00110bbb000100011BBB111110111110. */ +{ "vmsub2hnfr", 0x30118FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vmsub2hnfr<.cc> b,b,limm 00110bbb110100011BBB1111100QQQQQ. */ +{ "vmsub2hnfr", 0x30D18F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vmsub2hnfr<.cc> 0,limm,c 00110110110100011111CCCCCC0QQQQQ. */ +{ "vmsub2hnfr", 0x36D1F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vmsub2hnfr a,limm,u6 00110110010100011111uuuuuuAAAAAA. */ +{ "vmsub2hnfr", 0x3651F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr 0,limm,u6 00110110010100011111uuuuuu111110. */ +{ "vmsub2hnfr", 0x3651F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vmsub2hnfr<.cc> 0,limm,u6 00110110110100011111uuuuuu1QQQQQ. */ +{ "vmsub2hnfr", 0x36D1F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vmsub2hnfr 0,limm,s12 00110110100100011111ssssssSSSSSS. */ +{ "vmsub2hnfr", 0x3691F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vmsub2hnfr a,limm,limm 00110110000100011111111110AAAAAA. */ +{ "vmsub2hnfr", 0x3611FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hnfr 0,limm,limm 00110110000100011111111110111110. */ +{ "vmsub2hnfr", 0x3611FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vmsub2hnfr<.cc> 0,limm,limm 001101101101000111111111100QQQQQ. */ +{ "vmsub2hnfr", 0x36D1FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vneg2h b,c 00101bbb001011110BBBCCCCCC101010. */ +{ "vneg2h", 0x282F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vneg2h 0,c 00101110001011110111CCCCCC101010. */ +{ "vneg2h", 0x2E2F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vneg2h b,u6 00101bbb011011110BBBuuuuuu101010. */ +{ "vneg2h", 0x286F002A, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vneg2h 0,u6 00101110011011110111uuuuuu101010. */ +{ "vneg2h", 0x2E6F702A, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vneg2h b,limm 00101bbb001011110BBB111110101010. */ +{ "vneg2h", 0x282F0FAA, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vneg2h 0,limm 00101110001011110111111110101010. */ +{ "vneg2h", 0x2E2F7FAA, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vnegs2h b,c 00101bbb001011110BBBCCCCCC101011. */ +{ "vnegs2h", 0x282F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vnegs2h 0,c 00101110001011110111CCCCCC101011. */ +{ "vnegs2h", 0x2E2F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vnegs2h b,u6 00101bbb011011110BBBuuuuuu101011. */ +{ "vnegs2h", 0x286F002B, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vnegs2h 0,u6 00101110011011110111uuuuuu101011. */ +{ "vnegs2h", 0x2E6F702B, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vnegs2h b,limm 00101bbb001011110BBB111110101011. */ +{ "vnegs2h", 0x282F0FAB, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vnegs2h 0,limm 00101110001011110111111110101011. */ +{ "vnegs2h", 0x2E2F7FAB, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vnorm2h b,c 00101bbb001011110BBBCCCCCC101100. */ +{ "vnorm2h", 0x282F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vnorm2h 0,c 00101110001011110111CCCCCC101100. */ +{ "vnorm2h", 0x2E2F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vnorm2h b,u6 00101bbb011011110BBBuuuuuu101100. */ +{ "vnorm2h", 0x286F002C, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vnorm2h 0,u6 00101110011011110111uuuuuu101100. */ +{ "vnorm2h", 0x2E6F702C, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vnorm2h b,limm 00101bbb001011110BBB111110101100. */ +{ "vnorm2h", 0x282F0FAC, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vnorm2h 0,limm 00101110001011110111111110101100. */ +{ "vnorm2h", 0x2E2F7FAC, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vrep2hl b,c 00101bbb001011110BBBCCCCCC100010. */ +{ "vrep2hl", 0x282F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vrep2hl 0,c 00101110001011110111CCCCCC100010. */ +{ "vrep2hl", 0x2E2F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vrep2hl b,u6 00101bbb011011110BBBuuuuuu100010. */ +{ "vrep2hl", 0x286F0022, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vrep2hl 0,u6 00101110011011110111uuuuuu100010. */ +{ "vrep2hl", 0x2E6F7022, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vrep2hl b,limm 00101bbb001011110BBB111110100010. */ +{ "vrep2hl", 0x282F0FA2, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vrep2hl 0,limm 00101110001011110111111110100010. */ +{ "vrep2hl", 0x2E2F7FA2, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vrep2hm b,c 00101bbb001011110BBBCCCCCC100011. */ +{ "vrep2hm", 0x282F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vrep2hm 0,c 00101110001011110111CCCCCC100011. */ +{ "vrep2hm", 0x2E2F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vrep2hm b,u6 00101bbb011011110BBBuuuuuu100011. */ +{ "vrep2hm", 0x286F0023, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vrep2hm 0,u6 00101110011011110111uuuuuu100011. */ +{ "vrep2hm", 0x2E6F7023, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vrep2hm b,limm 00101bbb001011110BBB111110100011. */ +{ "vrep2hm", 0x282F0FA3, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vrep2hm 0,limm 00101110001011110111111110100011. */ +{ "vrep2hm", 0x2E2F7FA3, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vsext2bhl b,c 00101bbb001011110BBBCCCCCC100110. */ +{ "vsext2bhl", 0x282F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vsext2bhl 0,c 00101110001011110111CCCCCC100110. */ +{ "vsext2bhl", 0x2E2F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vsext2bhl b,u6 00101bbb011011110BBBuuuuuu100110. */ +{ "vsext2bhl", 0x286F0026, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vsext2bhl 0,u6 00101110011011110111uuuuuu100110. */ +{ "vsext2bhl", 0x2E6F7026, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vsext2bhl b,limm 00101bbb001011110BBB111110100110. */ +{ "vsext2bhl", 0x282F0FA6, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vsext2bhl 0,limm 00101110001011110111111110100110. */ +{ "vsext2bhl", 0x2E2F7FA6, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vsext2bhm b,c 00101bbb001011110BBBCCCCCC100111. */ +{ "vsext2bhm", 0x282F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RC }, { 0 }}, + +/* vsext2bhm 0,c 00101110001011110111CCCCCC100111. */ +{ "vsext2bhm", 0x2E2F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RC }, { 0 }}, + +/* vsext2bhm b,u6 00101bbb011011110BBBuuuuuu100111. */ +{ "vsext2bhm", 0x286F0027, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, UIMM6_20 }, { 0 }}, + +/* vsext2bhm 0,u6 00101110011011110111uuuuuu100111. */ +{ "vsext2bhm", 0x2E6F7027, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, UIMM6_20 }, { 0 }}, + +/* vsext2bhm b,limm 00101bbb001011110BBB111110100111. */ +{ "vsext2bhm", 0x282F0FA7, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, LIMM }, { 0 }}, + +/* vsext2bhm 0,limm 00101110001011110111111110100111. */ +{ "vsext2bhm", 0x2E2F7FA7, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM }, { 0 }}, + +/* vsub2 a,b,c 00101bbb001111010BBBCCCCCCAAAAAA. */ +{ "vsub2", 0x283D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vsub2 0,b,c 00101bbb001111010BBBCCCCCC111110. */ +{ "vsub2", 0x283D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vsub2<.cc> b,b,c 00101bbb111111010BBBCCCCCC0QQQQQ. */ +{ "vsub2", 0x28FD0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vsub2 a,b,u6 00101bbb011111010BBBuuuuuuAAAAAA. */ +{ "vsub2", 0x287D0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsub2 0,b,u6 00101bbb011111010BBBuuuuuu111110. */ +{ "vsub2", 0x287D003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsub2<.cc> b,b,u6 00101bbb111111010BBBuuuuuu1QQQQQ. */ +{ "vsub2", 0x28FD0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsub2 b,b,s12 00101bbb101111010BBBssssssSSSSSS. */ +{ "vsub2", 0x28BD0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsub2 a,limm,c 00101110001111010111CCCCCCAAAAAA. */ +{ "vsub2", 0x2E3D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vsub2 a,b,limm 00101bbb001111010BBB111110AAAAAA. */ +{ "vsub2", 0x283D0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vsub2 0,limm,c 00101110001111010111CCCCCC111110. */ +{ "vsub2", 0x2E3D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vsub2 0,b,limm 00101bbb001111010BBB111110111110. */ +{ "vsub2", 0x283D0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vsub2<.cc> b,b,limm 00101bbb111111010BBB1111100QQQQQ. */ +{ "vsub2", 0x28FD0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsub2<.cc> 0,limm,c 00101110111111010111CCCCCC0QQQQQ. */ +{ "vsub2", 0x2EFD7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsub2 a,limm,u6 00101110011111010111uuuuuuAAAAAA. */ +{ "vsub2", 0x2E7D7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub2 0,limm,u6 00101110011111010111uuuuuu111110. */ +{ "vsub2", 0x2E7D703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub2<.cc> 0,limm,u6 00101110111111010111uuuuuu1QQQQQ. */ +{ "vsub2", 0x2EFD7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsub2 0,limm,s12 00101110101111010111ssssssSSSSSS. */ +{ "vsub2", 0x2EBD7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsub2 a,limm,limm 00101110001111010111111110AAAAAA. */ +{ "vsub2", 0x2E3D7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsub2 0,limm,limm 00101110001111010111111110111110. */ +{ "vsub2", 0x2E3D7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsub2<.cc> 0,limm,limm 001011101111110101111111100QQQQQ. */ +{ "vsub2", 0x2EFD7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsub2h a,b,c 00101bbb000101010BBBCCCCCCAAAAAA. */ +{ "vsub2h", 0x28150000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }}, + +/* vsub2h 0,b,c 00101bbb000101010BBBCCCCCC111110. */ +{ "vsub2h", 0x2815003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }}, + +/* vsub2h<.cc> b,b,c 00101bbb110101010BBBCCCCCC0QQQQQ. */ +{ "vsub2h", 0x28D50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }}, + +/* vsub2h a,b,u6 00101bbb010101010BBBuuuuuuAAAAAA. */ +{ "vsub2h", 0x28550000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsub2h 0,b,u6 00101bbb010101010BBBuuuuuu111110. */ +{ "vsub2h", 0x2855003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsub2h<.cc> b,b,u6 00101bbb110101010BBBuuuuuu1QQQQQ. */ +{ "vsub2h", 0x28D50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsub2h b,b,s12 00101bbb100101010BBBssssssSSSSSS. */ +{ "vsub2h", 0x28950000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsub2h a,limm,c 00101110000101010111CCCCCCAAAAAA. */ +{ "vsub2h", 0x2E157000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }}, + +/* vsub2h a,b,limm 00101bbb000101010BBB111110AAAAAA. */ +{ "vsub2h", 0x28150F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }}, + +/* vsub2h 0,limm,c 00101110000101010111CCCCCC111110. */ +{ "vsub2h", 0x2E15703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }}, + +/* vsub2h 0,b,limm 00101bbb000101010BBB111110111110. */ +{ "vsub2h", 0x28150FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }}, + +/* vsub2h<.cc> b,b,limm 00101bbb110101010BBB1111100QQQQQ. */ +{ "vsub2h", 0x28D50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsub2h<.cc> 0,limm,c 00101110110101010111CCCCCC0QQQQQ. */ +{ "vsub2h", 0x2ED57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsub2h a,limm,u6 00101110010101010111uuuuuuAAAAAA. */ +{ "vsub2h", 0x2E557000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub2h 0,limm,u6 00101110010101010111uuuuuu111110. */ +{ "vsub2h", 0x2E55703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub2h<.cc> 0,limm,u6 00101110110101010111uuuuuu1QQQQQ. */ +{ "vsub2h", 0x2ED57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsub2h 0,limm,s12 00101110100101010111ssssssSSSSSS. */ +{ "vsub2h", 0x2E957000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsub2h a,limm,limm 00101110000101010111111110AAAAAA. */ +{ "vsub2h", 0x2E157F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsub2h 0,limm,limm 00101110000101010111111110111110. */ +{ "vsub2h", 0x2E157FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsub2h<.cc> 0,limm,limm 001011101101010101111111100QQQQQ. */ +{ "vsub2h", 0x2ED57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsub4b a,b,c 00101bbb001001010BBBCCCCCCAAAAAA. */ +{ "vsub4b", 0x28250000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vsub4b 0,b,c 00101bbb001001010BBBCCCCCC111110. */ +{ "vsub4b", 0x2825003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vsub4b<.cc> b,b,c 00101bbb111001010BBBCCCCCC0QQQQQ. */ +{ "vsub4b", 0x28E50000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vsub4b a,b,u6 00101bbb011001010BBBuuuuuuAAAAAA. */ +{ "vsub4b", 0x28650000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsub4b 0,b,u6 00101bbb011001010BBBuuuuuu111110. */ +{ "vsub4b", 0x2865003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsub4b<.cc> b,b,u6 00101bbb111001010BBBuuuuuu1QQQQQ. */ +{ "vsub4b", 0x28E50020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsub4b b,b,s12 00101bbb101001010BBBssssssSSSSSS. */ +{ "vsub4b", 0x28A50000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsub4b a,limm,c 00101110001001010111CCCCCCAAAAAA. */ +{ "vsub4b", 0x2E257000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vsub4b a,b,limm 00101bbb001001010BBB111110AAAAAA. */ +{ "vsub4b", 0x28250F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vsub4b 0,limm,c 00101110011001010111CCCCCC111110. */ +{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vsub4b 0,b,limm 00101bbb001001010BBB111110111110. */ +{ "vsub4b", 0x28250FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vsub4b<.cc> b,b,limm 00101bbb111001010BBB1111100QQQQQ. */ +{ "vsub4b", 0x28E50F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsub4b<.cc> 0,limm,c 00101110111001010111CCCCCC0QQQQQ. */ +{ "vsub4b", 0x2EE57000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vsub4b a,limm,u6 00101110011001010111uuuuuuAAAAAA. */ +{ "vsub4b", 0x2E657000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub4b 0,limm,u6 00101110011001010111uuuuuu111110. */ +{ "vsub4b", 0x2E65703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub4b<.cc> 0,limm,u6 00101110111001010111uuuuuu1QQQQQ. */ +{ "vsub4b", 0x2EE57020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsub4b 0,limm,s12 00101110101001010111ssssssSSSSSS. */ +{ "vsub4b", 0x2EA57000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsub4b a,limm,limm 00101110001001010111111110AAAAAA. */ +{ "vsub4b", 0x2E257F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsub4b 0,limm,limm 00101110001001010111111110111110. */ +{ "vsub4b", 0x2E257FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsub4b<.cc> 0,limm,limm 001011101110010101111111100QQQQQ. */ +{ "vsub4b", 0x2EE57F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsub4h a,b,c 00101bbb001110010BBBCCCCCCAAAAAA. */ +{ "vsub4h", 0x28390000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vsub4h 0,b,c 00101bbb001110010BBBCCCCCC111110. */ +{ "vsub4h", 0x2839003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vsub4h<.cc> b,b,c 00101bbb111110010BBBCCCCCC0QQQQQ. */ +{ "vsub4h", 0x28F90000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vsub4h a,b,u6 00101bbb011110010BBBuuuuuuAAAAAA. */ +{ "vsub4h", 0x28790000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsub4h 0,b,u6 00101bbb011110010BBBuuuuuu111110. */ +{ "vsub4h", 0x2879003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsub4h<.cc> b,b,u6 00101bbb111110010BBBuuuuuu1QQQQQ. */ +{ "vsub4h", 0x28F90020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsub4h b,b,s12 00101bbb101110010BBBssssssSSSSSS. */ +{ "vsub4h", 0x28B90000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsub4h a,limm,c 00101110001110010111CCCCCCAAAAAA. */ +{ "vsub4h", 0x2E397000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vsub4h a,b,limm 00101bbb001110010BBB111110AAAAAA. */ +{ "vsub4h", 0x28390F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vsub4h 0,limm,c 00101110001110010111CCCCCC111110. */ +{ "vsub4h", 0x2E39703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vsub4h 0,b,limm 00101bbb001110010BBB111110111110. */ +{ "vsub4h", 0x28390FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vsub4h<.cc> b,b,limm 00101bbb111110010BBB1111100QQQQQ. */ +{ "vsub4h", 0x28F90F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsub4h<.cc> 0,limm,c 00101110111110010111CCCCCC0QQQQQ. */ +{ "vsub4h", 0x2EF97000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsub4h a,limm,u6 00101110011110010111uuuuuuAAAAAA. */ +{ "vsub4h", 0x2E797000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub4h 0,limm,u6 00101110011110010111uuuuuu111110. */ +{ "vsub4h", 0x2E79703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsub4h<.cc> 0,limm,u6 00101110111110010111uuuuuu1QQQQQ. */ +{ "vsub4h", 0x2EF97020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsub4h 0,limm,s12 00101110101110010111ssssssSSSSSS. */ +{ "vsub4h", 0x2EB97000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsub4h a,limm,limm 00101110001110010111111110AAAAAA. */ +{ "vsub4h", 0x2E397F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsub4h 0,limm,limm 00101110001110010111111110111110. */ +{ "vsub4h", 0x2E397FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsub4h<.cc> 0,limm,limm 001011101111100101111111100QQQQQ. */ +{ "vsub4h", 0x2EF97F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsubadd a,b,c 00101bbb001111110BBBCCCCCCAAAAAA. */ +{ "vsubadd", 0x283F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vsubadd 0,b,c 00101bbb001111110BBBCCCCCC111110. */ +{ "vsubadd", 0x283F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vsubadd<.cc> b,b,c 00101bbb111111110BBBCCCCCC0QQQQQ. */ +{ "vsubadd", 0x28FF0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vsubadd a,b,u6 00101bbb011111110BBBuuuuuuAAAAAA. */ +{ "vsubadd", 0x287F0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd 0,b,u6 00101bbb011111110BBBuuuuuu111110. */ +{ "vsubadd", 0x287F003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd<.cc> b,b,u6 00101bbb111111110BBBuuuuuu1QQQQQ. */ +{ "vsubadd", 0x28FF0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsubadd b,b,s12 00101bbb101111110BBBssssssSSSSSS. */ +{ "vsubadd", 0x28BF0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsubadd a,limm,c 00101110001111110111CCCCCCAAAAAA. */ +{ "vsubadd", 0x2E3F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vsubadd a,b,limm 00101bbb001111110BBB111110AAAAAA. */ +{ "vsubadd", 0x283F0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vsubadd 0,limm,c 00101110001111110111CCCCCC111110. */ +{ "vsubadd", 0x2E3F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vsubadd 0,b,limm 00101bbb001111110BBB111110111110. */ +{ "vsubadd", 0x283F0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vsubadd<.cc> b,b,limm 00101bbb111111110BBB1111100QQQQQ. */ +{ "vsubadd", 0x28FF0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsubadd<.cc> 0,limm,c 00101110111111110111CCCCCC0QQQQQ. */ +{ "vsubadd", 0x2EFF7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsubadd a,limm,u6 00101110011111110111uuuuuuAAAAAA. */ +{ "vsubadd", 0x2E7F7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd 0,limm,u6 00101110011111110111uuuuuu111110. */ +{ "vsubadd", 0x2E7F703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd<.cc> 0,limm,u6 00101110111111110111uuuuuu1QQQQQ. */ +{ "vsubadd", 0x2EFF7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsubadd 0,limm,s12 00101110101111110111ssssssSSSSSS. */ +{ "vsubadd", 0x2EBF7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsubadd a,limm,limm 00101110001111110111111110AAAAAA. */ +{ "vsubadd", 0x2E3F7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd 0,limm,limm 00101110001111110111111110111110. */ +{ "vsubadd", 0x2E3F7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd<.cc> 0,limm,limm 001011101111111101111111100QQQQQ. */ +{ "vsubadd", 0x2EFF7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsubadd2h a,b,c 00101bbb000101110BBBCCCCCCAAAAAA. */ +{ "vsubadd2h", 0x28170000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, RC }, { 0 }}, + +/* vsubadd2h 0,b,c 00101bbb000101110BBBCCCCCC111110. */ +{ "vsubadd2h", 0x2817003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, RC }, { 0 }}, + +/* vsubadd2h<.cc> b,b,c 00101bbb110101110BBBCCCCCC0QQQQQ. */ +{ "vsubadd2h", 0x28D70000, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, RC }, { C_CC }}, + +/* vsubadd2h a,b,u6 00101bbb010101110BBBuuuuuuAAAAAA. */ +{ "vsubadd2h", 0x28570000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd2h 0,b,u6 00101bbb010101110BBBuuuuuu111110. */ +{ "vsubadd2h", 0x2857003E, 0xF8FF803F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd2h<.cc> b,b,u6 00101bbb110101110BBBuuuuuu1QQQQQ. */ +{ "vsubadd2h", 0x28D70020, 0xF8FF8020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsubadd2h b,b,s12 00101bbb100101110BBBssssssSSSSSS. */ +{ "vsubadd2h", 0x28970000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsubadd2h a,limm,c 00101110000101110111CCCCCCAAAAAA. */ +{ "vsubadd2h", 0x2E177000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, RC }, { 0 }}, + +/* vsubadd2h a,b,limm 00101bbb000101110BBB111110AAAAAA. */ +{ "vsubadd2h", 0x28170F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, RB, LIMM }, { 0 }}, + +/* vsubadd2h 0,limm,c 00101110000101110111CCCCCC111110. */ +{ "vsubadd2h", 0x2E17703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { 0 }}, + +/* vsubadd2h 0,b,limm 00101bbb000101110BBB111110111110. */ +{ "vsubadd2h", 0x28170FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, RB, LIMM }, { 0 }}, + +/* vsubadd2h<.cc> b,b,limm 00101bbb110101110BBB1111100QQQQQ. */ +{ "vsubadd2h", 0x28D70F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsubadd2h<.cc> 0,limm,c 00101110110101110111CCCCCC0QQQQQ. */ +{ "vsubadd2h", 0x2ED77000, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsubadd2h a,limm,u6 00101110010101110111uuuuuuAAAAAA. */ +{ "vsubadd2h", 0x2E577000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd2h 0,limm,u6 00101110010101110111uuuuuu111110. */ +{ "vsubadd2h", 0x2E57703E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd2h<.cc> 0,limm,u6 00101110110101110111uuuuuu1QQQQQ. */ +{ "vsubadd2h", 0x2ED77020, 0xFFFFF020, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsubadd2h 0,limm,s12 00101110100101110111ssssssSSSSSS. */ +{ "vsubadd2h", 0x2E977000, 0xFFFFF000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsubadd2h a,limm,limm 00101110000101110111111110AAAAAA. */ +{ "vsubadd2h", 0x2E177F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd2h 0,limm,limm 00101110000101110111111110111110. */ +{ "vsubadd2h", 0x2E177FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd2h<.cc> 0,limm,limm 001011101101011101111111100QQQQQ. */ +{ "vsubadd2h", 0x2ED77F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, MPY7E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsubadd4h a,b,c 00101bbb001110110BBBCCCCCCAAAAAA. */ +{ "vsubadd4h", 0x283B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, RC }, { 0 }}, + +/* vsubadd4h 0,b,c 00101bbb001110110BBBCCCCCC111110. */ +{ "vsubadd4h", 0x283B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, RC }, { 0 }}, + +/* vsubadd4h<.cc> b,b,c 00101bbb111110110BBBCCCCCC0QQQQQ. */ +{ "vsubadd4h", 0x28FB0000, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, RC }, { C_CC }}, + +/* vsubadd4h a,b,u6 00101bbb011110110BBBuuuuuuAAAAAA. */ +{ "vsubadd4h", 0x287B0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd4h 0,b,u6 00101bbb011110110BBBuuuuuu111110. */ +{ "vsubadd4h", 0x287B003E, 0xF8FF803F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadd4h<.cc> b,b,u6 00101bbb111110110BBBuuuuuu1QQQQQ. */ +{ "vsubadd4h", 0x28FB0020, 0xF8FF8020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsubadd4h b,b,s12 00101bbb101110110BBBssssssSSSSSS. */ +{ "vsubadd4h", 0x28BB0000, 0xF8FF8000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsubadd4h a,limm,c 00101110001110110111CCCCCCAAAAAA. */ +{ "vsubadd4h", 0x2E3B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, RC }, { 0 }}, + +/* vsubadd4h a,b,limm 00101bbb001110110BBB111110AAAAAA. */ +{ "vsubadd4h", 0x283B0F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, RB, LIMM }, { 0 }}, + +/* vsubadd4h 0,limm,c 00101110001110110111CCCCCC111110. */ +{ "vsubadd4h", 0x2E3B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { 0 }}, + +/* vsubadd4h 0,b,limm 00101bbb001110110BBB111110111110. */ +{ "vsubadd4h", 0x283B0FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, RB, LIMM }, { 0 }}, + +/* vsubadd4h<.cc> b,b,limm 00101bbb111110110BBB1111100QQQQQ. */ +{ "vsubadd4h", 0x28FB0F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsubadd4h<.cc> 0,limm,c 00101110111110110111CCCCCC0QQQQQ. */ +{ "vsubadd4h", 0x2EFB7000, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, RC }, { C_CC }}, + +/* vsubadd4h a,limm,u6 00101110011110110111uuuuuuAAAAAA. */ +{ "vsubadd4h", 0x2E7B7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd4h 0,limm,u6 00101110011110110111uuuuuu111110. */ +{ "vsubadd4h", 0x2E7B703E, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadd4h<.cc> 0,limm,u6 00101110111110110111uuuuuu1QQQQQ. */ +{ "vsubadd4h", 0x2EFB7020, 0xFFFFF020, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsubadd4h 0,limm,s12 00101110101110110111ssssssSSSSSS. */ +{ "vsubadd4h", 0x2EBB7000, 0xFFFFF000, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsubadd4h a,limm,limm 00101110001110110111111110AAAAAA. */ +{ "vsubadd4h", 0x2E3B7F80, 0xFFFFFFC0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd4h 0,limm,limm 00101110001110110111111110111110. */ +{ "vsubadd4h", 0x2E3B7FBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadd4h<.cc> 0,limm,limm 001011101111101101111111100QQQQQ. */ +{ "vsubadd4h", 0x2EFB7F80, 0xFFFFFFE0, ARC_OPCODE_ARCv2HS, ARITH, MPY9E, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsubadds2h a,b,c 00101bbb000101111BBBCCCCCCAAAAAA. */ +{ "vsubadds2h", 0x28178000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vsubadds2h 0,b,c 00101bbb000101111BBBCCCCCC111110. */ +{ "vsubadds2h", 0x2817803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vsubadds2h<.cc> b,b,c 00101bbb110101111BBBCCCCCC0QQQQQ. */ +{ "vsubadds2h", 0x28D78000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vsubadds2h a,b,u6 00101bbb010101111BBBuuuuuuAAAAAA. */ +{ "vsubadds2h", 0x28578000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadds2h 0,b,u6 00101bbb010101111BBBuuuuuu111110. */ +{ "vsubadds2h", 0x2857803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsubadds2h<.cc> b,b,u6 00101bbb110101111BBBuuuuuu1QQQQQ. */ +{ "vsubadds2h", 0x28D78020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsubadds2h b,b,s12 00101bbb100101111BBBssssssSSSSSS. */ +{ "vsubadds2h", 0x28978000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsubadds2h a,limm,c 00101110000101111111CCCCCCAAAAAA. */ +{ "vsubadds2h", 0x2E17F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vsubadds2h a,b,limm 00101bbb000101111BBB111110AAAAAA. */ +{ "vsubadds2h", 0x28178F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vsubadds2h 0,limm,c 00101110000101111111CCCCCC111110. */ +{ "vsubadds2h", 0x2E17F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vsubadds2h 0,b,limm 00101bbb000101111BBB111110111110. */ +{ "vsubadds2h", 0x28178FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vsubadds2h<.cc> b,b,limm 00101bbb110101111BBB1111100QQQQQ. */ +{ "vsubadds2h", 0x28D78F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsubadds2h<.cc> 0,limm,c 00101110110101111111CCCCCC0QQQQQ. */ +{ "vsubadds2h", 0x2ED7F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vsubadds2h a,limm,u6 00101110010101111111uuuuuuAAAAAA. */ +{ "vsubadds2h", 0x2E57F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadds2h 0,limm,u6 00101110010101111111uuuuuu111110. */ +{ "vsubadds2h", 0x2E57F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubadds2h<.cc> 0,limm,u6 00101110110101111111uuuuuu1QQQQQ. */ +{ "vsubadds2h", 0x2ED7F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsubadds2h 0,limm,s12 00101110100101111111ssssssSSSSSS. */ +{ "vsubadds2h", 0x2E97F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsubadds2h a,limm,limm 00101110000101111111111110AAAAAA. */ +{ "vsubadds2h", 0x2E17FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadds2h 0,limm,limm 00101110000101111111111110111110. */ +{ "vsubadds2h", 0x2E17FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsubadds2h<.cc> 0,limm,limm 001011101101011111111111100QQQQQ. */ +{ "vsubadds2h", 0x2ED7FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* vsubs2h a,b,c 00101bbb000101011BBBCCCCCCAAAAAA. */ +{ "vsubs2h", 0x28158000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }}, + +/* vsubs2h 0,b,c 00101bbb000101011BBBCCCCCC111110. */ +{ "vsubs2h", 0x2815803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, RC }, { 0 }}, + +/* vsubs2h<.cc> b,b,c 00101bbb110101011BBBCCCCCC0QQQQQ. */ +{ "vsubs2h", 0x28D58000, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, RC }, { C_CC }}, + +/* vsubs2h a,b,u6 00101bbb010101011BBBuuuuuuAAAAAA. */ +{ "vsubs2h", 0x28558000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, UIMM6_20 }, { 0 }}, + +/* vsubs2h 0,b,u6 00101bbb010101011BBBuuuuuu111110. */ +{ "vsubs2h", 0x2855803E, 0xF8FF803F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, UIMM6_20 }, { 0 }}, + +/* vsubs2h<.cc> b,b,u6 00101bbb110101011BBBuuuuuu1QQQQQ. */ +{ "vsubs2h", 0x28D58020, 0xF8FF8020, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, UIMM6_20 }, { C_CC }}, + +/* vsubs2h b,b,s12 00101bbb100101011BBBssssssSSSSSS. */ +{ "vsubs2h", 0x28958000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, SIMM12_20 }, { 0 }}, + +/* vsubs2h a,limm,c 00101110000101011111CCCCCCAAAAAA. */ +{ "vsubs2h", 0x2E15F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, RC }, { 0 }}, + +/* vsubs2h a,b,limm 00101bbb000101011BBB111110AAAAAA. */ +{ "vsubs2h", 0x28158F80, 0xF8FF8FC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, LIMM }, { 0 }}, + +/* vsubs2h 0,limm,c 00101110000101011111CCCCCC111110. */ +{ "vsubs2h", 0x2E15F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { 0 }}, + +/* vsubs2h 0,b,limm 00101bbb000101011BBB111110111110. */ +{ "vsubs2h", 0x28158FBE, 0xF8FF8FFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, RB, LIMM }, { 0 }}, + +/* vsubs2h<.cc> b,b,limm 00101bbb110101011BBB1111100QQQQQ. */ +{ "vsubs2h", 0x28D58F80, 0xF8FF8FE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RB, RBdup, LIMM }, { C_CC }}, + +/* vsubs2h<.cc> 0,limm,c 00101110110101011111CCCCCC0QQQQQ. */ +{ "vsubs2h", 0x2ED5F000, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, RC }, { C_CC }}, + +/* vsubs2h a,limm,u6 00101110010101011111uuuuuuAAAAAA. */ +{ "vsubs2h", 0x2E55F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubs2h 0,limm,u6 00101110010101011111uuuuuu111110. */ +{ "vsubs2h", 0x2E55F03E, 0xFFFFF03F, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }}, + +/* vsubs2h<.cc> 0,limm,u6 00101110110101011111uuuuuu1QQQQQ. */ +{ "vsubs2h", 0x2ED5F020, 0xFFFFF020, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, UIMM6_20 }, { C_CC }}, + +/* vsubs2h 0,limm,s12 00101110100101011111ssssssSSSSSS. */ +{ "vsubs2h", 0x2E95F000, 0xFFFFF000, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, SIMM12_20 }, { 0 }}, + +/* vsubs2h a,limm,limm 00101110000101011111111110AAAAAA. */ +{ "vsubs2h", 0x2E15FF80, 0xFFFFFFC0, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, LIMM, LIMMdup }, { 0 }}, + +/* vsubs2h 0,limm,limm 00101110000101011111111110111110. */ +{ "vsubs2h", 0x2E15FFBE, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { 0 }}, + +/* vsubs2h<.cc> 0,limm,limm 001011101101010111111111100QQQQQ. */ +{ "vsubs2h", 0x2ED5FF80, 0xFFFFFFE0, ARC_OPCODE_ARCv2EM, DSP, NONE, { ZA, LIMM, LIMMdup }, { C_CC }}, + +/* wevt c 00100000001011110001CCCCCC111111. */ +{ "wevt", 0x202F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }}, + +/* wevt u6 00100000011011110001uuuuuu111111. */ +{ "wevt", 0x206F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }}, + +/* wlfc c 00100001001011110001CCCCCC111111. */ +{ "wlfc", 0x212F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { RC }, { 0 }}, + +/* wlfc u6 00100001011011110001uuuuuu111111. */ +{ "wlfc", 0x216F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_20 }, { 0 }}, + +/* xbfu<.f> a,b,c 00100bbb00101101FBBBCCCCCCAAAAAA. */ +{ "xbfu", 0x202D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, RC }, { C_F }}, + +/* xbfu<.f> 0,b,c 00100bbb00101101FBBBCCCCCC111110. */ +{ "xbfu", 0x202D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, RC }, { C_F }}, + +/* xbfu<.f><.cc> b,b,c 00100bbb11101101FBBBCCCCCC0QQQQQ. */ +{ "xbfu", 0x20ED0000, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* xbfu<.f> a,b,u6 00100bbb01101101FBBBuuuuuuAAAAAA. */ +{ "xbfu", 0x206D0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, UIMM6_20 }, { C_F }}, + +/* xbfu<.f> 0,b,u6 00100bbb01101101FBBBuuuuuu111110. */ +{ "xbfu", 0x206D003E, 0xF8FF003F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* xbfu<.f><.cc> b,b,u6 00100bbb11101101FBBBuuuuuu1QQQQQ. */ +{ "xbfu", 0x20ED0020, 0xF8FF0020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* xbfu<.f> b,b,s12 00100bbb10101101FBBBssssssSSSSSS. */ +{ "xbfu", 0x20AD0000, 0xF8FF0000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* xbfu<.f> a,limm,c 0010011000101101F111CCCCCCAAAAAA. */ +{ "xbfu", 0x262D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, RC }, { C_F }}, + +/* xbfu<.f> a,b,limm 00100bbb00101101FBBB111110AAAAAA. */ +{ "xbfu", 0x202D0F80, 0xF8FF0FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, RB, LIMM }, { C_F }}, + +/* xbfu<.f> 0,limm,c 0010011000101101F111CCCCCC111110. */ +{ "xbfu", 0x262D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F }}, + +/* xbfu<.f> 0,b,limm 00100bbb00101101FBBB111110111110. */ +{ "xbfu", 0x202D0FBE, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, RB, LIMM }, { C_F }}, + +/* xbfu<.f><.cc> b,b,limm 00100bbb11101101FBBB1111100QQQQQ. */ +{ "xbfu", 0x20ED0F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* xbfu<.f><.cc> 0,limm,c 0010011011101101F111CCCCCC0QQQQQ. */ +{ "xbfu", 0x26ED7000, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* xbfu<.f> a,limm,u6 0010011001101101F111uuuuuuAAAAAA. */ +{ "xbfu", 0x266D7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* xbfu<.f> 0,limm,u6 0010011001101101F111uuuuuu111110. */ +{ "xbfu", 0x266D703E, 0xFFFF703F, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* xbfu<.f><.cc> 0,limm,u6 0010011011101101F111uuuuuu1QQQQQ. */ +{ "xbfu", 0x26ED7020, 0xFFFF7020, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* xbfu<.f> 0,limm,s12 0010011010101101F111ssssssSSSSSS. */ +{ "xbfu", 0x26AD7000, 0xFFFF7000, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* xbfu<.f> a,limm,limm 0010011000101101F111111110AAAAAA. */ +{ "xbfu", 0x262D7F80, 0xFFFF7FC0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { RA, LIMM, LIMMdup }, { C_F }}, + +/* xbfu<.f> 0,limm,limm 0010011000101101F111111110111110. */ +{ "xbfu", 0x262D7FBE, 0xFFFF7FFF, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* xbfu<.f><.cc> 0,limm,limm 0010011011101101F1111111100QQQQQ. */ +{ "xbfu", 0x26ED7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2HS, ARITH, SHFT2, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* xor<.f> a,b,c 00100bbb00000111FBBBCCCCCCAAAAAA. */ +{ "xor", 0x20070000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }}, + +/* xor<.f> 0,b,c 00100bbb00000111FBBBCCCCCC111110. */ +{ "xor", 0x2007003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, RC }, { C_F }}, + +/* xor<.f><.cc> b,b,c 00100bbb11000111FBBBCCCCCC0QQQQQ. */ +{ "xor", 0x20C70000, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* xor<.f> a,b,u6 00100bbb01000111FBBBuuuuuuAAAAAA. */ +{ "xor", 0x20470000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* xor<.f> 0,b,u6 00100bbb01000111FBBBuuuuuu111110. */ +{ "xor", 0x2047003E, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, UIMM6_20 }, { C_F }}, + +/* xor<.f><.cc> b,b,u6 00100bbb11000111FBBBuuuuuu1QQQQQ. */ +{ "xor", 0x20C70020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* xor<.f> b,b,s12 00100bbb10000111FBBBssssssSSSSSS. */ +{ "xor", 0x20870000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* xor<.f> a,limm,c 0010011000000111F111CCCCCCAAAAAA. */ +{ "xor", 0x26077000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, RC }, { C_F }}, + +/* xor<.f> a,b,limm 00100bbb00000111FBBB111110AAAAAA. */ +{ "xor", 0x20070F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, LIMM }, { C_F }}, + +/* xor<.f> 0,limm,c 0010011000000111F111CCCCCC111110. */ +{ "xor", 0x2607703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F }}, + +/* xor<.f> 0,b,limm 00100bbb00000111FBBB111110111110. */ +{ "xor", 0x20070FBE, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, RB, LIMM }, { C_F }}, + +/* xor<.f><.cc> 0,limm,c 0010011011000111F111CCCCCC0QQQQQ. */ +{ "xor", 0x26C77000, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, RC }, { C_F, C_CC }}, + +/* xor<.f><.cc> b,b,limm 00100bbb11000111FBBB1111100QQQQQ. */ +{ "xor", 0x20C70F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + +/* xor<.f> a,limm,u6 0010011001000111F111uuuuuuAAAAAA. */ +{ "xor", 0x26477000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, UIMM6_20 }, { C_F }}, + +/* xor<.f> 0,limm,u6 0010011001000111F111uuuuuu111110. */ +{ "xor", 0x2647703E, 0xFFFF703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, + +/* xor<.f><.cc> 0,limm,u6 0010011011000111F111uuuuuu1QQQQQ. */ +{ "xor", 0x26C77020, 0xFFFF7020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, UIMM6_20 }, { C_F, C_CC }}, + +/* xor<.f> 0,limm,s12 0010011010000111F111ssssssSSSSSS. */ +{ "xor", 0x26877000, 0xFFFF7000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, SIMM12_20 }, { C_F }}, + +/* xor<.f> a,limm,limm 0010011000000111F111111110AAAAAA. */ +{ "xor", 0x26077F80, 0xFFFF7FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, LIMM, LIMMdup }, { C_F }}, + +/* xor<.f> 0,limm,limm 0010011000000111F111111110111110. */ +{ "xor", 0x26077FBE, 0xFFFF7FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F }}, + +/* xor<.f><.cc> 0,limm,limm 0010011011000111F1111111100QQQQQ. */ +{ "xor", 0x26C77F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }}, + +/* xor_s b,b,c 01111bbbccc00111. */ +{ "xor_s", 0x00007807, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, RC_S }, { 0 }}, + +/* xpkqb<.f> a,b,c 00110bbb00100010FBBBCCCCCCAAAAAA. */ +{ "xpkqb", 0x30220000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,c 00110bbb11100010FBBBCCCCCC0QQQQQ. */ +{ "xpkqb", 0x30E20000, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, RC }, { C_F, C_CC }}, + +/* xpkqb<.f> a,b,u6 00110bbb01100010FBBBuuuuuuAAAAAA. */ +{ "xpkqb", 0x30620000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,u6 00110bbb11100010FBBBuuuuuu1QQQQQ. */ +{ "xpkqb", 0x30E20020, 0xF8FF0020, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, UIMM6_20 }, { C_F, C_CC }}, + +/* xpkqb<.f> b,b,s12 00110bbb10100010FBBBssssssSSSSSS. */ + +{ "xpkqb", 0x30A20000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_F }}, + +/* xpkqb<.f> a,limm,c 0011011000100010F111CCCCCCAAAAAA. */ +{ "xpkqb", 0x36227000, 0xFFFF7000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, LIMM, RC }, { C_F }}, + +/* xpkqb<.f> a,b,limm 00110bbb00100010FBBB111110AAAAAA. */ +{ "xpkqb", 0x30220F80, 0xF8FF0FC0, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, LIMM }, { C_F }}, + +/* xpkqb<.f><.cc> b,b,limm 00110bbb11100010FBBB1111100QQQQQ. */ +{ "xpkqb", 0x30E20F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, + |