diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 22 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 20 |
4 files changed, 51 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4899711..7ecb512 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2009-12-03 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (FXSAVE_Fixup): New. + (FXSAVE): Likewise. + (mod_table): Use FXSAVE on fxsave and fxrstor. + + * i386-opc.tbl: Add fxsave64 and fxrstor64. + * i386-tbl.h: Regenerated. + 2009-12-02 Nick Clifton <nickc@redhat.com> Richard Earnshaw <rearnsha@arm.com> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index a9bb2b1..0e5b0ab 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -110,6 +110,7 @@ static void REP_Fixup (int, int); static void CMPXCHG8B_Fixup (int, int); static void XMM_Fixup (int, int); static void CRC32_Fixup (int, int); +static void FXSAVE_Fixup (int, int); static void OP_LWPCB_E (int, int); static void OP_LWP_E (int, int); static void OP_LWP_I (int, int); @@ -358,6 +359,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define OPSUF { OP_3DNowSuffix, 0 } #define CMP { CMP_Fixup, 0 } #define XMM0 { XMM_Fixup, 0 } +#define FXSAVE { FXSAVE_Fixup, 0 } #define Vex_2src_1 { OP_Vex_2src_1, 0 } #define Vex_2src_2 { OP_Vex_2src_2, 0 } @@ -9541,12 +9543,12 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_0 */ - { "fxsave", { M } }, + { "fxsave", { FXSAVE } }, { "(bad)", { XX } }, }, { /* MOD_0FAE_REG_1 */ - { "fxrstor", { M } }, + { "fxrstor", { FXSAVE } }, { "(bad)", { XX } }, }, { @@ -13641,6 +13643,22 @@ skip: OP_E (bytemode, sizeflag); } +static void +FXSAVE_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "fxsave" and "fxrstor". */ + USED_REX (REX_W); + if (rex & REX_W) + { + char *p = mnemonicendp; + *p++ = '6'; + *p++ = '4'; + *p = '\0'; + mnemonicendp = p; + } + OP_M (bytemode, sizeflag); +} + /* Display the destination register operand for instructions with VEX. */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 37dccab..3f8bcaa 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -848,7 +848,9 @@ cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ld sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } fxsave, 1, 0xfae, 0x0, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxsave64, 1, 0xfae, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } fxrstor, 1, 0xfae, 0x1, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +fxrstor64, 1, 0xfae, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } rdpmc, 0, 0xf33, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } // official undefined instr. ud2, 0, 0xf0b, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 9f2f7fb..1e98a6d 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -6902,6 +6902,16 @@ const insn_template i386_optab[] = { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } }, + { "fxsave64", 1, 0xfae, 0x0, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, + 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0 } } } }, { "fxrstor", 1, 0xfae, 0x1, 2, { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -6912,6 +6922,16 @@ const insn_template i386_optab[] = { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } }, + { "fxrstor64", 1, 0xfae, 0x1, 2, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 0, 0 } }, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, + 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0 } } } }, { "rdpmc", 0, 0xf33, None, 2, { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |