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-rw-r--r--opcodes/ChangeLog4
-rw-r--r--opcodes/arm-dis.c2
2 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b8eea11..5e5a752 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2006-07-05 Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
+
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 977fcf1..a375578 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -280,7 +280,7 @@ static const struct opcode32 coprocessor_opcodes[] =
{FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
{FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%16-19,0-3d"},
{FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%16-19,0-3d"},
- {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %y4"},
+ {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
{FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
{FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
{FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},