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-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/s390-dis.c25
-rw-r--r--opcodes/s390-opc.c16
-rw-r--r--opcodes/s390-opc.txt12
4 files changed, 47 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7688357..8a7b998 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
+
+ * s390-dis.c (print_insn_s390): Pick instruction with most
+ specific mask.
+ * s390-opc.c: Add unused bits to the insn mask.
+ * s390-opc.txt: Reorder some instructions to prefer more recent
+ versions.
+
2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
* arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c
index b9eeb79..37ed2e7 100644
--- a/opcodes/s390-dis.c
+++ b/opcodes/s390-dis.c
@@ -166,6 +166,8 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
if (status == 0)
{
+ const struct s390_opcode *op;
+
/* Find the first match in the opcode table. */
opcode_end = s390_opcodes + s390_num_opcodes;
for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
@@ -178,6 +180,7 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
/* Check architecture. */
if (!(opcode->modes & current_arch_mask))
continue;
+
/* Check signature of the opcode. */
if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
|| (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
@@ -186,6 +189,28 @@ print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
|| (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
continue;
+ /* Advance to an opcode with a more specific mask. */
+ for (op = opcode + 1; op < opcode_end; op++)
+ {
+ if ((buffer[0] & op->mask[0]) != op->opcode[0])
+ break;
+
+ if ((buffer[1] & op->mask[1]) != op->opcode[1]
+ || (buffer[2] & op->mask[2]) != op->opcode[2]
+ || (buffer[3] & op->mask[3]) != op->opcode[3]
+ || (buffer[4] & op->mask[4]) != op->opcode[4]
+ || (buffer[5] & op->mask[5]) != op->opcode[5])
+ continue;
+
+ if (((int)opcode->mask[0] + opcode->mask[1] +
+ opcode->mask[2] + opcode->mask[3] +
+ opcode->mask[4] + opcode->mask[5]) <
+ ((int)op->mask[0] + op->mask[1] +
+ op->mask[2] + op->mask[3] +
+ op->mask[4] + op->mask[5]))
+ opcode = op;
+ }
+
/* The instruction is valid. */
if (opcode->operands[0] != 0)
(*info->fprintf_func) (info->stream, "%s\t", opcode->name);
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index dd13a92..1a6628d 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -398,10 +398,10 @@ const struct s390_operand s390_operands[] =
#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
-#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff }
#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
@@ -412,10 +412,10 @@ const struct s390_operand s390_operands[] =
#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
-#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff }
+#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
+#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff }
#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index f556226..36a2d03 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -107,10 +107,10 @@ b7 lctl RS_CCRD "load control" g5 esa,zarch
82 lpsw S_RD "load PSW" g5 esa,zarch
18 lr RR_RR "load" g5 esa,zarch
b1 lra RX_RRRD "load real address" g5 esa,zarch
-25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
-35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch
+25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch
35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch
+35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch
22 ltdr RR_FF "load and test (long)" g5 esa,zarch
32 lter RR_FF "load and test (short)" g5 esa,zarch
12 ltr RR_RR "load and test" g5 esa,zarch
@@ -119,10 +119,10 @@ b24b lura RRE_RR "load using real address" g5 esa,zarch
af mc SI_URD "monitor call" g5 esa,zarch
6c md RX_FRRD "multiply (long)" g5 esa,zarch
2c mdr RR_FF "multiply (long)" g5 esa,zarch
-7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch
-3c mer RR_FF "multiply (short to long)" g5 esa,zarch
+7c me RX_FRRD "multiply (short to long)" g5 esa,zarch
3c mder RR_FF "multiply short to long hfp" g5 esa,zarch
+3c mer RR_FF "multiply (short to long)" g5 esa,zarch
4c mh RX_RRRD "multiply halfword" g5 esa,zarch
fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch
1c mr RR_RR "multiply" g5 esa,zarch
@@ -259,7 +259,9 @@ a8 mvcle RS_RRRD "move long extended" g5 esa,zarch
a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch
b252 msr RRE_RR "multiply single" g5 esa,zarch
71 ms RX_RRRD "multiply single" g5 esa,zarch
+a700 tmlh RI_RU "test under mask low high" g5 esa,zarch
a700 tmh RI_RU "test under mask high" g5 esa,zarch
+a701 tmll RI_RU "test under mask low low" g5 esa,zarch
a701 tml RI_RU "test under mask low" g5 esa,zarch
0700 nopr RR_0R_OPT "no operation" g5 esa,zarch
0700 b*8r RR_0R "conditional branch" g5 esa,zarch
@@ -366,8 +368,6 @@ b277 rp S_RD "resume program" g5 esa,zarch
b27d stsi S_RD "store system information" g5 esa,zarch
01ff trap2 E "trap" g5 esa,zarch
b2ff trap4 S_RD "trap4" g5 esa,zarch
-a700 tmlh RI_RU "test under mask low high" g5 esa,zarch
-a701 tmll RI_RU "test under mask low low" g5 esa,zarch
b278 stcke S_RD "store clock extended" g5 esa,zarch
b2a5 tre RRE_RR "translate extended" g5 esa,zarch
eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch
generated by cgit v1.1 at 2024-11-24 09:31:53 +0000