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-rw-r--r--opcodes/ChangeLog11
-rw-r--r--opcodes/micromips-opc.c10
-rw-r--r--opcodes/mips-dis.c20
-rw-r--r--opcodes/mips-opc.c10
4 files changed, 49 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0a59fab..7c603f1 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,14 @@
+2011-08-09 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
+ and "mips64r2".
+ (print_insn_args, print_insn_micromips): Handle MCU.
+ * micromips-opc.c (MC): New macro.
+ (micromips_opcodes): Add "aclr", "aset" and "iret".
+ * mips-opc.c (MC): New macro.
+ (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
+
2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
* micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 0d5b11d..852081e 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -99,6 +99,9 @@
#define I1 INSN_ISA1
#define I3 INSN_ISA3
+/* MIPS MCU (MicroController) ASE support. */
+#define MC INSN_MCU
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
@@ -138,6 +141,9 @@ const struct mips_opcode micromips_opcodes[] =
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, MC },
+{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC },
+{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
@@ -170,6 +176,9 @@ const struct mips_opcode micromips_opcodes[] =
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, MC },
+{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC },
+{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC },
/* b is at the top of the table. */
/* bal is at the top of the table. */
{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
@@ -508,6 +517,7 @@ const struct mips_opcode micromips_opcodes[] =
{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_T|RD_S|FP_S|FP_D, 0, I1 },
{"floor.w.s", "T,V", 0x54000b3b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_t|RD_s, 0, I1 },
+{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, MC },
{"jr", "mj", 0x4580, 0xffe0, UBD, RD_mj, I1 },
{"jr", "s", 0x00000f3c, 0xffe0ffff, UBD|RD_s, BD32, I1 }, /* jalr */
{"jrs", "s", 0x00004f3c, 0xffe0ffff, UBD|RD_s, BD16, I1 }, /* jalrs */
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 75f9bb7..4e18d8a 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -564,7 +564,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
(ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
- | INSN_MIPS3D | INSN_MT),
+ | INSN_MIPS3D | INSN_MT | INSN_MCU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -578,7 +578,7 @@ const struct mips_arch_choice mips_arch_choices[] =
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
(ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
- | INSN_DSP64 | INSN_MT | INSN_MDMX),
+ | INSN_DSP64 | INSN_MT | INSN_MDMX | INSN_MCU),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
mips_hwr_names_mips3264r2 },
@@ -1170,6 +1170,18 @@ print_insn_args (const char *d,
(*info->fprintf_func) (info->stream, "%d", delta);
break;
+ case '~':
+ delta = (l >> OP_SH_OFFSET12) & OP_MASK_OFFSET12;
+ if (delta & 0x800)
+ delta |= ~0x7ff;
+ (*info->fprintf_func) (info->stream, "%d", delta);
+ break;
+
+ case '\\':
+ (*info->fprintf_func) (info->stream, "0x%lx",
+ (l >> OP_SH_3BITPOS) & OP_MASK_3BITPOS);
+ break;
+
case '\'':
(*info->fprintf_func) (info->stream, "0x%lx",
(l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
@@ -2388,6 +2400,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
iprintf (is, "0x%lx", GET_OP (insn, SHAMT));
break;
+ case '\\':
+ iprintf (is, "0x%lx", GET_OP (insn, 3BITPOS));
+ break;
+
case '|':
iprintf (is, "0x%lx", GET_OP (insn, TRAP));
break;
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index f8770a4..7adf337 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -173,6 +173,9 @@
#define RD_Z INSN2_READ_FPR_Z
#define RD_d INSN2_READ_GPR_D
+/* MIPS MCU (MicroController) ASE support. */
+#define MC INSN_MCU
+
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
@@ -272,6 +275,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F },
{"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E },
+{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, MC },
+{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC },
+{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC },
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
{"add", "D,S,T", 0x45c00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S, 0, IL2E },
@@ -312,6 +318,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, MC },
+{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC },
+{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC },
{"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT },
/* b is at the top of the table. */
/* bal is at the top of the table. */
@@ -778,6 +787,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
+{"iret", "", 0x42000038, 0xffffffff, NODS, 0, MC },
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
the same hazard barrier effect. */
generated by cgit v1.1 at 2024-11-22 21:58:19 +0000