diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 12 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 15 | ||||
| -rw-r--r-- | opcodes/mips16-opc.c | 21 |
3 files changed, 32 insertions, 16 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6b3b56c..2832beb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2010-07-06 Maciej W. Rozycki <macro@codesourcery.com> + + * mips-dis.c (print_mips16_insn_arg): Remove branch instruction + type and delay slot determination. + (print_insn_mips16): Extend branch instruction type and delay + slot determination to cover all instructions. + * mips16-opc.c (BR): Remove macro. + (UBR, CBR): New macros. + (mips16_opcodes): Update branch annotation for "b", "beqz", + "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" + and "jrc". + 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index bcfef72..01e446c 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1660,7 +1660,6 @@ print_mips16_insn_arg (char type, signedp = 1; pcrel = 1; branch = 1; - info->insn_type = dis_condbranch; break; case 'q': nbits = 11; @@ -1668,7 +1667,6 @@ print_mips16_insn_arg (char type, signedp = 1; pcrel = 1; branch = 1; - info->insn_type = dis_branch; break; case 'A': nbits = 8; @@ -1789,8 +1787,6 @@ print_mips16_insn_arg (char type, } info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; (*info->print_address_func) (info->target, info); - info->insn_type = dis_jsr; - info->branch_delay_insns = 1; break; case 'l': @@ -2082,12 +2078,19 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) info); } + /* Figure out branch instruction type and delay slot information. */ if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) + info->branch_delay_insns = 1; + if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY + | MIPS16_INSN_UNCOND_BRANCH)) != 0) { - info->branch_delay_insns = 1; - if (info->insn_type != dis_jsr) + if ((op->pinfo & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_jsr; + else info->insn_type = dis_branch; } + else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0) + info->insn_type = dis_condbranch; return length; } diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c index 0243196..c42ab27 100644 --- a/opcodes/mips16-opc.c +++ b/opcodes/mips16-opc.c @@ -33,7 +33,8 @@ the opcodes table. */ #define UBD INSN_UNCOND_BRANCH_DELAY -#define BR MIPS16_INSN_BRANCH +#define UBR MIPS16_INSN_UNCOND_BRANCH +#define CBR MIPS16_INSN_COND_BRANCH #define WR_x MIPS16_INSN_WRITE_X #define WR_y MIPS16_INSN_WRITE_Y @@ -85,10 +86,10 @@ const struct mips_opcode mips16_opcodes[] = {"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 }, {"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 }, {"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, -{"b", "q", 0x1000, 0xf800, BR, 0, I1 }, +{"b", "q", 0x1000, 0xf800, UBR, 0, I1 }, {"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 }, {"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 }, -{"beqz", "x,p", 0x2000, 0xf800, BR|RD_x, 0, I1 }, +{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 }, {"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 }, {"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 }, {"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 }, @@ -107,10 +108,10 @@ const struct mips_opcode mips16_opcodes[] = {"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 }, {"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 }, {"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 }, -{"bnez", "x,p", 0x2800, 0xf800, BR|RD_x, 0, I1 }, +{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 }, {"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 }, -{"bteqz", "p", 0x6000, 0xff00, BR|RD_T, 0, I1 }, -{"btnez", "p", 0x6100, 0xff00, BR|RD_T, 0, I1 }, +{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 }, +{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1 }, {"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, {"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 }, {"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 }, @@ -226,10 +227,10 @@ const struct mips_opcode mips16_opcodes[] = {"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 }, {"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 }, /* MIPS16e additions */ -{"jalrc", "x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 }, -{"jalrc", "R,x", 0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0, I32 }, -{"jrc", "x", 0xe880, 0xf8ff, RD_x|TRAP, 0, I32 }, -{"jrc", "R", 0xe8a0, 0xffff, RD_31|TRAP, 0, I32 }, +{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, +{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|TRAP, 0, I32 }, +{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|TRAP, 0, I32 }, +{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|TRAP, 0, I32 }, {"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0, I32 }, {"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0, I32 }, {"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 }, |