diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 83 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 120 |
2 files changed, 161 insertions, 42 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index afe48fd..4ca1d76 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2003-06-10 Gary Hade <garyhade@us.ibm.com> + Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define. + (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New. + (powerpc_opcodes): Add "attn", "lq" and "stq". + 2003-06-10 Richard Sandiford <rsandifo@redhat.com> * h8300-dis.c (bfd_h8_disassemble): Don't print brackets round @@ -52,9 +59,9 @@ 2003-05-17 Andreas Jaeger <aj@suse.de> - * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. - (libopcodes_la_DEPENDENCIES): Add libbfd.la. - * Makefile.in: Regenerated. + * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. + (libopcodes_la_DEPENDENCIES): Add libbfd.la. + * Makefile.in: Regenerated. 2003-05-16 Nick Clifton <nickc@redhat.com> @@ -118,7 +125,7 @@ 2003-03-25 Stan Cox <scox@redhat.com> Nick Clifton <nickc@redhat.com> - + Contribute support for Intel's iWMMXt chip - an ARM variant: * arm-dis.c (regnames): Add iWMMXt register names. @@ -226,24 +233,24 @@ 2002-01-02 Ben Elliston <bje@redhat.com> Jeff Johnston <jjohnstn@redhat.com> - * iq2000-asm.c: New file. - * iq2000-desc.c: Likewise. - * iq2000-desc.h: Likewise. - * iq2000-dis.c: Likewise. - * iq2000-ibld.c: Likewise. - * iq2000-opc.c: Likewise. - * iq2000-opc.h: Likewise. - * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. - (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, - iq2000-ibld.c, iq2000-opc.c. - (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, - iq2000-ibld.lo, iq2000-opc.lo. - (CLEANFILES): Add stamp-iq2000. - (IQ2000_DEPS): New macro. - (stamp-iq2000): New target. - * Makefile.in: Regenerate. - * configure.in: Handle bfd_iq2000_arch. - * configure: Regenerate. + * iq2000-asm.c: New file. + * iq2000-desc.c: Likewise. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * iq2000-opc.c: Likewise. + * iq2000-opc.h: Likewise. + * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. + (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c. + (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, + iq2000-ibld.lo, iq2000-opc.lo. + (CLEANFILES): Add stamp-iq2000. + (IQ2000_DEPS): New macro. + (stamp-iq2000): New target. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_iq2000_arch. + * configure: Regenerate. 2003-01-02 Chris Demetriou <cgd@broadcom.com> @@ -439,7 +446,7 @@ (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate. - + 2002-11-25 Aldy Hernandez <aldyh@redhat.com> * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa, @@ -517,7 +524,7 @@ * xstormy16-desc.c: Regenerate. * xstormy16-opc.c: Regenerate. * xstormy16-opc.h: Regenerate. - + 2002-11-18 Klee Dienes <kdienes@apple.com> * avr-dis.c: Include libiberty.h (for xmalloc). @@ -599,18 +606,18 @@ 2002-11-07 Klee Dienes <kdienes@apple.com> - * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' - argument to ia64-gen. + * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' + argument to ia64-gen. Regenerate dependencies for ia64-len.lo. * Makefile.in: Regenerate. - * ia64-gen.c: Convert to use getopt(). Add the standard GNU - options, as well as '--srcdir', which controls the directory in - which ia64-gen looks for the sources it uses to generate the - output table. Add a 'const' to the declaration of the final - output table. Call xmalloc_set_program_name to set the program - name. + * ia64-gen.c: Convert to use getopt(). Add the standard GNU + options, as well as '--srcdir', which controls the directory in + which ia64-gen looks for the sources it uses to generate the + output table. Add a 'const' to the declaration of the final + output table. Call xmalloc_set_program_name to set the program + name. * ia64-asmtab.c: Regenerate. - + 2002-11-07 Nick Clifton <nickc@redhat.com> * ia64-gen.c: Fix comment formatting and compile time warnings. @@ -624,7 +631,7 @@ 2002-11-06 Aldy Hernandez <aldyh@redhat.com> - * opcodes/ppc-opc.c: Change RD to RS for evmerge*. + * opcodes/ppc-opc.c: Change RD to RS for evmerge*. 2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu> @@ -639,10 +646,10 @@ at the end. 2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 27eb23e..a6e9313 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -68,6 +68,10 @@ static unsigned long insert_boe PARAMS ((unsigned long, long, int, const char **)); static long extract_boe PARAMS ((unsigned long, int, int *)); +static unsigned long insert_dq + PARAMS ((unsigned long, long, int, const char **)); +static long extract_dq + PARAMS ((unsigned long, int, int *)); static unsigned long insert_ds PARAMS ((unsigned long, long, int, const char **)); static long extract_ds @@ -104,12 +108,18 @@ static unsigned long insert_ral PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_ram PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_raq + PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_ras PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_rbs PARAMS ((unsigned long, long, int, const char **)); static long extract_rbs PARAMS ((unsigned long, int, int *)); +static unsigned long insert_rsq + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_rtq + PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_sh6 PARAMS ((unsigned long, long, int, const char **)); static long extract_sh6 @@ -279,9 +289,15 @@ const struct powerpc_operand powerpc_operands[] = #define DES DE + 1 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ +#define DQ DES + 1 + { 16, 0, insert_dq, extract_dq, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ -#define DS DES + 1 +#define DS DQ + 1 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, @@ -389,15 +405,20 @@ const struct powerpc_operand powerpc_operands[] = { 16, 0, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ + /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ #define RA NSI + 1 #define RA_MASK (0x1f << 16) { 5, 16, 0, 0, PPC_OPERAND_GPR }, + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ +#define RAQ RA + 1 + { 5, 16, insert_raq, 0, PPC_OPERAND_GPR }, + /* The RA field in a D or X form instruction which is an updating load, which means that the RA field may not be zero and may not equal the RT field. */ -#define RAL RA + 1 +#define RAL RAQ + 1 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, /* The RA field in an lmw instruction, which has special value @@ -430,8 +451,18 @@ const struct powerpc_operand powerpc_operands[] = #define RT_MASK (0x1f << 21) { 5, 21, 0, 0, PPC_OPERAND_GPR }, + /* The RS field of the DS form stq instruction, which has special + value restrictions. */ +#define RSQ RS + 1 + { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR }, + + /* The RT field of the DQ form lq instruction, which has special + value restrictions. */ +#define RTQ RSQ + 1 + { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR }, + /* The SH field in an X or M form instruction. */ -#define SH RS + 1 +#define SH RTQ + 1 #define SH_MASK (0x1f << 11) { 5, 11, 0, 0, 0 }, @@ -870,6 +901,32 @@ extract_boe (insn, dialect, invalid) return value & 0x1e; } + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ + +/*ARGSUSED*/ +static unsigned long +insert_dq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char ** errmsg ATTRIBUTE_UNUSED; +{ + if ((value & 0xf) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 16"); + return insn | (value & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_dq (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn & 0xfff0) ^ 0x8000) - 0x8000; +} + static unsigned long insert_ev2 (insn, value, dialect, errmsg) unsigned long insn; @@ -1253,6 +1310,24 @@ insert_ram (insn, value, dialect, errmsg) return insn | ((value & 0x1f) << 16); } + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_raq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + long rtvalue = (insn & RT_MASK) >> 21; + + if (value == rtvalue && errmsg != NULL) + *errmsg = _("source and target register operands must be different"); + return insn | ((value & 0x1f) << 16); +} + /* The RA field in a D or X form instruction which is an updating store or an updating floating point load, which means that the RA field may not be zero. */ @@ -1298,6 +1373,38 @@ extract_rbs (insn, dialect, invalid) return 0; } + /* The RT field of the DQ form lq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_rtq (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 1) != 0 && errmsg != NULL) + *errmsg = _("target register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + + /* The RS field of the DS form stq instruction, which has special + value restrictions. */ + +/*ARGSUSED*/ +static unsigned long +insert_rsq (insn, value, dialect, errmsg) + unsigned long insn; + long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value & 1) != 0 && errmsg != NULL) + *errmsg = _("source register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + /* The SH field in an MD form instruction. This is split. */ /*ARGSUSED*/ @@ -1768,6 +1875,7 @@ extract_tbr (insn, dialect, invalid) sorted by major opcode. */ const struct powerpc_opcode powerpc_opcodes[] = { +{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, @@ -4335,6 +4443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, +{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, + { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, @@ -4411,6 +4521,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, +{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } }, + { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, |