diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/micromips-opc.c | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8e6a052..d412db9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com> + Maciej W. Rozycki <macro@imgtec.com> + + * micromips-opc.c (I36): New macro. + (micromips_opcodes): Add "eretnc". + 2017-06-30 Maciej W. Rozycki <macro@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index dcd235f..d8edd28 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -253,6 +253,7 @@ decode_micromips_operand (const char *p) are accepted as 64-bit microMIPS ISA. */ #define I1 INSN_ISA1 #define I3 INSN_ISA3 +#define I36 INSN_ISA32R5 /* MIPS DSP ASE support. */ #define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */ @@ -687,6 +688,7 @@ const struct mips_opcode micromips_opcodes[] = {"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 }, {"ei", "s", 0x0000577c, 0xffe0ffff, WR_1|WR_C0, 0, I1, 0, 0 }, {"eret", "", 0x0000f37c, 0xffffffff, NODS, 0, I1, 0, 0 }, +{"eretnc", "", 0x0001f37c, 0xffffffff, NODS, 0, I36, 0, 0 }, {"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 }, {"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, |