diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rwxr-xr-x | opcodes/configure | 1 | ||||
| -rw-r--r-- | opcodes/configure.ac | 1 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 8 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 502 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 624 |
6 files changed, 1147 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3337f63..bd8e59d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +2016-11-01 Palmer Dabbelt <palmer@dabbelt.com> + Andrew Waterman <andrew@sifive.com> + + Add support for RISC-V architecture. + * configure.ac: Add entry for bfd_riscv_arch. + * configure: Regenerate. + * disassemble.c (disassembler): Add support for riscv. + (disassembler_usage): Likewise. + * riscv-dis.c: New file. + * riscv-opc.c: New file. + 2016-10-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. diff --git a/opcodes/configure b/opcodes/configure index 031da2f..6ef3844 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12685,6 +12685,7 @@ if test x${all_targets} = xfalse ; then bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; + bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index c7f4783..3475d49 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -309,6 +309,7 @@ if test x${all_targets} = xfalse ; then bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; + bfd_riscv_arch) ta="$ta riscv-dis.lo riscv-opc.lo" ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";; bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 45ae34e..e1fb65c 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -375,6 +375,11 @@ disassembler (bfd *abfd) disassemble = print_insn_little_powerpc; break; #endif +#ifdef ARCH_riscv + case bfd_arch_riscv: + disassemble = print_insn_riscv; + break; +#endif #ifdef ARCH_rs6000 case bfd_arch_rs6000: if (bfd_get_mach (abfd) == bfd_mach_ppc_620) @@ -559,6 +564,9 @@ disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif +#ifdef ARCH_riscv + print_riscv_disassembler_options (stream); +#endif #ifdef ARCH_i386 print_i386_disassembler_options (stream); #endif diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c new file mode 100644 index 0000000..3b4e1e0 --- /dev/null +++ b/opcodes/riscv-dis.c @@ -0,0 +1,502 @@ +/* RISC-V disassembler + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opcode/riscv.h" +#include "opintl.h" +#include "elf-bfd.h" +#include "elf/riscv.h" + +#include <stdint.h> +#include <ctype.h> + +struct riscv_private_data +{ + bfd_vma gp; + bfd_vma print_addr; + bfd_vma hi_addr[OP_MASK_RD + 1]; +}; + +static const char * const *riscv_gpr_names; +static const char * const *riscv_fpr_names; + +/* Other options. */ +static int no_aliases; /* If set disassemble as most general inst. */ + +static void +set_default_riscv_dis_options (void) +{ + riscv_gpr_names = riscv_gpr_names_abi; + riscv_fpr_names = riscv_fpr_names_abi; + no_aliases = 0; +} + +static void +parse_riscv_dis_option (const char *option) +{ + if (strcmp (option, "no-aliases") == 0) + no_aliases = 1; + else if (strcmp (option, "numeric") == 0) + { + riscv_gpr_names = riscv_gpr_names_numeric; + riscv_fpr_names = riscv_fpr_names_numeric; + } + else + { + /* Invalid option. */ + fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option); + } +} + +static void +parse_riscv_dis_options (const char *opts_in) +{ + char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; + + set_default_riscv_dis_options (); + + for ( ; opt_end != NULL; opt = opt_end + 1) + { + if ((opt_end = strchr (opt, ',')) != NULL) + *opt_end = 0; + parse_riscv_dis_option (opt); + } + + free (opts); +} + +/* Print one argument from an array. */ + +static void +arg_print (struct disassemble_info *info, unsigned long val, + const char* const* array, size_t size) +{ + const char *s = val >= size || array[val] == NULL ? "unknown" : array[val]; + (*info->fprintf_func) (info->stream, "%s", s); +} + +static void +maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset) +{ + if (pd->hi_addr[base_reg] != (bfd_vma)-1) + { + pd->print_addr = pd->hi_addr[base_reg] + offset; + pd->hi_addr[base_reg] = -1; + } + else if (base_reg == X_GP && pd->gp != (bfd_vma)-1) + pd->print_addr = pd->gp + offset; + else if (base_reg == X_TP || base_reg == 0) + pd->print_addr = offset; +} + +/* Print insn arguments for 32/64-bit code. */ + +static void +print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) +{ + struct riscv_private_data *pd = info->private_data; + int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1; + int rd = (l >> OP_SH_RD) & OP_MASK_RD; + fprintf_ftype print = info->fprintf_func; + + if (*d != '\0') + print (info->stream, "\t"); + + for (; *d != '\0'; d++) + { + switch (*d) + { + case 'C': /* RVC */ + switch (*++d) + { + case 's': /* RS1 x8-x15 */ + case 'w': /* RS1 x8-x15 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS1S, l) + 8]); + break; + case 't': /* RS2 x8-x15 */ + case 'x': /* RS2 x8-x15 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); + break; + case 'U': /* RS1, constrained to equal RD */ + print (info->stream, "%s", riscv_gpr_names[rd]); + break; + case 'c': /* RS1, constrained to equal sp */ + print (info->stream, "%s", riscv_gpr_names[X_SP]); + break; + case 'V': /* RS2 */ + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); + break; + case 'i': + print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); + break; + case 'j': + print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); + break; + case 'k': + print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); + break; + case 'l': + print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); + break; + case 'm': + print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); + break; + case 'n': + print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); + break; + case 'K': + print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); + break; + case 'L': + print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); + break; + case 'M': + print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); + break; + case 'N': + print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); + break; + case 'p': + info->target = EXTRACT_RVC_B_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + case 'a': + info->target = EXTRACT_RVC_J_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + case 'u': + print (info->stream, "0x%x", + (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); + break; + case '>': + print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); + break; + case '<': + print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); + break; + case 'T': /* floating-point RS2 */ + print (info->stream, "%s", + riscv_fpr_names[EXTRACT_OPERAND (CRS2, l)]); + break; + case 'D': /* floating-point RS2 x8-x15 */ + print (info->stream, "%s", + riscv_fpr_names[EXTRACT_OPERAND (CRS2S, l) + 8]); + break; + } + break; + + case ',': + case '(': + case ')': + case '[': + case ']': + print (info->stream, "%c", *d); + break; + + case '0': + /* Only print constant 0 if it is the last argument */ + if (!d[1]) + print (info->stream, "0"); + break; + + case 'b': + case 's': + print (info->stream, "%s", riscv_gpr_names[rs1]); + break; + + case 't': + print (info->stream, "%s", + riscv_gpr_names[EXTRACT_OPERAND (RS2, l)]); + break; + + case 'u': + print (info->stream, "0x%x", + (unsigned)EXTRACT_UTYPE_IMM (l) >> RISCV_IMM_BITS); + break; + + case 'm': + arg_print (info, EXTRACT_OPERAND (RM, l), + riscv_rm, ARRAY_SIZE (riscv_rm)); + break; + + case 'P': + arg_print (info, EXTRACT_OPERAND (PRED, l), + riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); + break; + + case 'Q': + arg_print (info, EXTRACT_OPERAND (SUCC, l), + riscv_pred_succ, ARRAY_SIZE (riscv_pred_succ)); + break; + + case 'o': + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + case 'j': + if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) + || (l & MASK_JALR) == MATCH_JALR) + maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_ITYPE_IMM (l)); + break; + + case 'q': + maybe_print_address (pd, rs1, EXTRACT_STYPE_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_STYPE_IMM (l)); + break; + + case 'a': + info->target = EXTRACT_UJTYPE_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + + case 'p': + info->target = EXTRACT_SBTYPE_IMM (l) + pc; + (*info->print_address_func) (info->target, info); + break; + + case 'd': + if ((l & MASK_AUIPC) == MATCH_AUIPC) + pd->hi_addr[rd] = pc + EXTRACT_UTYPE_IMM (l); + else if ((l & MASK_LUI) == MATCH_LUI) + pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); + else if ((l & MASK_C_LUI) == MATCH_C_LUI) + pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); + print (info->stream, "%s", riscv_gpr_names[rd]); + break; + + case 'z': + print (info->stream, "%s", riscv_gpr_names[0]); + break; + + case '>': + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMT, l)); + break; + + case '<': + print (info->stream, "0x%x", (int)EXTRACT_OPERAND (SHAMTW, l)); + break; + + case 'S': + case 'U': + print (info->stream, "%s", riscv_fpr_names[rs1]); + break; + + case 'T': + print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS2, l)]); + break; + + case 'D': + print (info->stream, "%s", riscv_fpr_names[rd]); + break; + + case 'R': + print (info->stream, "%s", riscv_fpr_names[EXTRACT_OPERAND (RS3, l)]); + break; + + case 'E': + { + const char* csr_name = NULL; + unsigned int csr = EXTRACT_OPERAND (CSR, l); + switch (csr) + { +#define DECLARE_CSR(name, num) case num: csr_name = #name; break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + if (csr_name) + print (info->stream, "%s", csr_name); + else + print (info->stream, "0x%x", csr); + break; + } + + case 'Z': + print (info->stream, "%d", rs1); + break; + + default: + /* xgettext:c-format */ + print (info->stream, _("# internal error, undefined modifier (%c)"), + *d); + return; + } + } +} + +/* Print the RISC-V instruction at address MEMADDR in debugged memory, + on using INFO. Returns length of the instruction, in bytes. + BIGENDIAN must be 1 if this is big-endian code, 0 if + this is little-endian code. */ + +static int +riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +{ + const struct riscv_opcode *op; + static bfd_boolean init = 0; + static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; + struct riscv_private_data *pd; + int insnlen; + +#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) + + /* Build a hash table to shorten the search time. */ + if (! init) + { + for (op = riscv_opcodes; op->name; op++) + if (!riscv_hash[OP_HASH_IDX (op->match)]) + riscv_hash[OP_HASH_IDX (op->match)] = op; + + init = 1; + } + + if (info->private_data == NULL) + { + int i; + + pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); + pd->gp = -1; + pd->print_addr = -1; + for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) + pd->hi_addr[i] = -1; + + for (i = 0; i < info->symtab_size; i++) + if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0) + pd->gp = bfd_asymbol_value (info->symtab[i]); + } + else + pd = info->private_data; + + insnlen = riscv_insn_length (word); + + info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2; + info->bytes_per_line = 8; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + op = riscv_hash[OP_HASH_IDX (word)]; + if (op != NULL) + { + int xlen = 0; + + /* The incoming section might not always be complete. */ + if (info->section != NULL) + { + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } + + for (; op->name; op++) + { + /* Does the opcode match? */ + if (! (op->match_func) (op, word)) + continue; + /* Is this a pseudo-instruction and may we print it as such? */ + if (no_aliases && (op->pinfo & INSN_ALIAS)) + continue; + /* Is this instruction restricted to a certain value of XLEN? */ + if (isdigit (op->subset[0]) && atoi (op->subset) != xlen) + continue; + + /* It's a match. */ + (*info->fprintf_func) (info->stream, "%s", op->name); + print_insn_args (op->args, word, memaddr, info); + + /* Try to disassemble multi-instruction addressing sequences. */ + if (pd->print_addr != (bfd_vma)-1) + { + info->target = pd->print_addr; + (*info->fprintf_func) (info->stream, " # "); + (*info->print_address_func) (info->target, info); + pd->print_addr = -1; + } + + return insnlen; + } + } + + /* We did not find a match, so just print the instruction bits. */ + info->insn_type = dis_noninsn; + (*info->fprintf_func) (info->stream, "0x%llx", (unsigned long long)word); + return insnlen; +} + +int +print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) +{ + bfd_byte packet[2]; + insn_t insn = 0; + bfd_vma n; + int status; + + if (info->disassembler_options != NULL) + { + parse_riscv_dis_options (info->disassembler_options); + /* Avoid repeatedly parsing the options. */ + info->disassembler_options = NULL; + } + else if (riscv_gpr_names == NULL) + set_default_riscv_dis_options (); + + /* Instructions are a sequence of 2-byte packets in little-endian order. */ + for (n = 0; n < sizeof (insn) && n < riscv_insn_length (insn); n += 2) + { + status = (*info->read_memory_func) (memaddr + n, packet, 2, info); + if (status != 0) + { + /* Don't fail just because we fell off the end. */ + if (n > 0) + break; + (*info->memory_error_func) (status, memaddr, info); + return status; + } + + insn |= ((insn_t) bfd_getl16 (packet)) << (8 * n); + } + + return riscv_disassemble_insn (memaddr, insn, info); +} + +void +print_riscv_disassembler_options (FILE *stream) +{ + fprintf (stream, _("\n\ +The following RISC-V-specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _("\n\ + numeric Print numeric reigster names, rather than ABI names.\n")); + + fprintf (stream, _("\n\ + no-aliases Disassemble only into canonical instructions, rather\n\ + than into pseudoinstructions.\n")); + + fprintf (stream, _("\n")); +} diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c new file mode 100644 index 0000000..1d8d579 --- /dev/null +++ b/opcodes/riscv-opc.c @@ -0,0 +1,624 @@ +/* RISC-V opcode list + Copyright 2011-2016 Free Software Foundation, Inc. + + Contributed by Andrew Waterman (andrew@sifive.com). + Based on MIPS target. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + +#include "sysdep.h" +#include "opcode/riscv.h" +#include <stdio.h> + +/* Register names used by gas and objdump. */ + +const char * const riscv_gpr_names_numeric[NGPR] = +{ + "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", + "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", + "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31" +}; + +const char * const riscv_gpr_names_abi[NGPR] = +{ + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" +}; + +const char * const riscv_fpr_names_numeric[NFPR] = +{ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" +}; + +const char * const riscv_fpr_names_abi[NFPR] = +{ + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" +}; + +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. */ + +#define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) +#define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) +#define MASK_RD (OP_MASK_RD << OP_SH_RD) +#define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) +#define MASK_IMM ENCODE_ITYPE_IMM(-1U) +#define MASK_RVC_IMM ENCODE_RVC_IMM(-1U) +#define MASK_UIMM ENCODE_UTYPE_IMM(-1U) +#define MASK_RM (OP_MASK_RM << OP_SH_RM) +#define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) +#define MASK_SUCC (OP_MASK_SUCC << OP_SH_SUCC) +#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ) +#define MASK_RL (OP_MASK_RL << OP_SH_RL) +#define MASK_AQRL (MASK_AQ | MASK_RL) + +static int +match_opcode (const struct riscv_opcode *op, insn_t insn) +{ + return ((insn ^ op->match) & op->mask) == 0; +} + +static int +match_never (const struct riscv_opcode *op ATTRIBUTE_UNUSED, + insn_t insn ATTRIBUTE_UNUSED) +{ + return 0; +} + +static int +match_rs1_eq_rs2 (const struct riscv_opcode *op, insn_t insn) +{ + int rs1 = (insn & MASK_RS1) >> OP_SH_RS1; + int rs2 = (insn & MASK_RS2) >> OP_SH_RS2; + return match_opcode (op, insn) && rs1 == rs2; +} + +static int +match_rd_nonzero (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) && ((insn & MASK_RD) != 0); +} + +static int +match_c_add (const struct riscv_opcode *op, insn_t insn) +{ + return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0); +} + +static int +match_c_lui (const struct riscv_opcode *op, insn_t insn) +{ + return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2); +} + +const struct riscv_opcode riscv_opcodes[] = +{ +/* name, isa, operands, match, mask, match_func, pinfo. */ +{"unimp", "C", "", 0, 0xffffU, match_opcode, 0 }, +{"unimp", "I", "", MATCH_CSRRW | (CSR_CYCLE << OP_SH_CSR), 0xffffffffU, match_opcode, 0 }, /* csrw cycle, x0 */ +{"ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"ebreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, 0 }, +{"sbreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, INSN_ALIAS }, +{"sbreak", "I", "", MATCH_EBREAK, MASK_EBREAK, match_opcode, INSN_ALIAS }, +{"ret", "C", "", MATCH_C_JR | (X_RA << OP_SH_RD), MASK_C_JR | MASK_RD, match_opcode, INSN_ALIAS }, +{"ret", "I", "", MATCH_JALR | (X_RA << OP_SH_RS1), MASK_JALR | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, INSN_ALIAS }, +{"jr", "I", "s", MATCH_JALR, MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jr", "I", "s,j", MATCH_JALR, MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{"jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, INSN_ALIAS }, +{"jalr", "I", "s", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jalr", "I", "s,j", MATCH_JALR | (X_RA << OP_SH_RD), MASK_JALR | MASK_RD, match_opcode, INSN_ALIAS }, +{"jalr", "I", "d,s", MATCH_JALR, MASK_JALR | MASK_IMM, match_opcode, INSN_ALIAS }, +{"jalr", "I", "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, 0 }, +{"j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS }, +{"j", "I", "a", MATCH_JAL, MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS }, +{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS }, +{"jal", "I", "d,a", MATCH_JAL, MASK_JAL, match_opcode, 0 }, +{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO }, +{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO }, +{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO }, +{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS }, +{"nop", "I", "", MATCH_ADDI, MASK_ADDI | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"lui", "I", "d,u", MATCH_LUI, MASK_LUI, match_opcode, 0 }, +{"li", "C", "d,Cv", MATCH_C_LUI, MASK_C_LUI, match_c_lui, INSN_ALIAS }, +{"li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, INSN_ALIAS }, +{"li", "C", "d,0", MATCH_C_LI, MASK_C_LI | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{"li", "I", "d,j", MATCH_ADDI, MASK_ADDI | MASK_RS1, match_opcode, INSN_ALIAS }, /* addi */ +{"li", "I", "d,I", 0, (int) M_LI, match_never, INSN_MACRO }, +{"mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"mv", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"move", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS }, +{"move", "I", "d,s", MATCH_ADDI, MASK_ADDI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"andi", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"andi", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 }, +{"and", "C", "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", "C", "Cs,Ct,Cw", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS }, +{"and", "C", "Cs,Cw,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS }, +{"and", "I", "d,s,t", MATCH_AND, MASK_AND, match_opcode, 0 }, +{"and", "I", "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, INSN_ALIAS }, +{"beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS }, +{"beqz", "I", "s,p", MATCH_BEQ, MASK_BEQ | MASK_RS2, match_opcode, INSN_ALIAS }, +{"beq", "I", "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, 0 }, +{"blez", "I", "t,p", MATCH_BGE, MASK_BGE | MASK_RS1, match_opcode, INSN_ALIAS }, +{"bgez", "I", "s,p", MATCH_BGE, MASK_BGE | MASK_RS2, match_opcode, INSN_ALIAS }, +{"ble", "I", "t,s,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_ALIAS }, +{"bleu", "I", "t,s,p", MATCH_BGEU, MASK_BGEU, match_opcode, INSN_ALIAS }, +{"bge", "I", "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, 0 }, +{"bgeu", "I", "s,t,p", MATCH_BGEU, MASK_BGEU, match_opcode, 0 }, +{"bltz", "I", "s,p", MATCH_BLT, MASK_BLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{"bgtz", "I", "t,p", MATCH_BLT, MASK_BLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{"blt", "I", "s,t,p", MATCH_BLT, MASK_BLT, match_opcode, 0 }, +{"bltu", "I", "s,t,p", MATCH_BLTU, MASK_BLTU, match_opcode, 0 }, +{"bgt", "I", "t,s,p", MATCH_BLT, MASK_BLT, match_opcode, INSN_ALIAS }, +{"bgtu", "I", "t,s,p", MATCH_BLTU, MASK_BLTU, match_opcode, INSN_ALIAS }, +{"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, +{"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, +{"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, +{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, +{"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, +{"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, +{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, +{"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, +{"la", "I", "d,A", 0, (int) M_LA, match_never, INSN_MACRO }, +{"lla", "I", "d,A", 0, (int) M_LLA, match_never, INSN_MACRO }, +{"la.tls.gd", "I", "d,A", 0, (int) M_LA_TLS_GD, match_never, INSN_MACRO }, +{"la.tls.ie", "I", "d,A", 0, (int) M_LA_TLS_IE, match_never, INSN_MACRO }, +{"neg", "I", "d,t", MATCH_SUB, MASK_SUB | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"slli", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{"slli", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, 0 }, +{"sll", "C", "d,CU,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, INSN_ALIAS }, +{"sll", "I", "d,s,t", MATCH_SLL, MASK_SLL, match_opcode, 0 }, +{"sll", "I", "d,s,>", MATCH_SLLI, MASK_SLLI, match_opcode, INSN_ALIAS }, +{"srli", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srli", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, 0 }, +{"srl", "C", "Cs,Cw,C>", MATCH_C_SRLI, MASK_C_SRLI, match_rd_nonzero, INSN_ALIAS }, +{"srl", "I", "d,s,t", MATCH_SRL, MASK_SRL, match_opcode, 0 }, +{"srl", "I", "d,s,>", MATCH_SRLI, MASK_SRLI, match_opcode, INSN_ALIAS }, +{"srai", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"srai", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, 0 }, +{"sra", "C", "Cs,Cw,C>", MATCH_C_SRAI, MASK_C_SRAI, match_rd_nonzero, INSN_ALIAS }, +{"sra", "I", "d,s,t", MATCH_SRA, MASK_SRA, match_opcode, 0 }, +{"sra", "I", "d,s,>", MATCH_SRAI, MASK_SRAI, match_opcode, INSN_ALIAS }, +{"sub", "C", "Cs,Cw,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, INSN_ALIAS }, +{"sub", "I", "d,s,t", MATCH_SUB, MASK_SUB, match_opcode, 0 }, +{"lb", "I", "d,o(s)", MATCH_LB, MASK_LB, match_opcode, 0 }, +{"lb", "I", "d,A", 0, (int) M_LB, match_never, INSN_MACRO }, +{"lbu", "I", "d,o(s)", MATCH_LBU, MASK_LBU, match_opcode, 0 }, +{"lbu", "I", "d,A", 0, (int) M_LBU, match_never, INSN_MACRO }, +{"lh", "I", "d,o(s)", MATCH_LH, MASK_LH, match_opcode, 0 }, +{"lh", "I", "d,A", 0, (int) M_LH, match_never, INSN_MACRO }, +{"lhu", "I", "d,o(s)", MATCH_LHU, MASK_LHU, match_opcode, 0 }, +{"lhu", "I", "d,A", 0, (int) M_LHU, match_never, INSN_MACRO }, +{"lw", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, INSN_ALIAS }, +{"lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, INSN_ALIAS }, +{"lw", "I", "d,o(s)", MATCH_LW, MASK_LW, match_opcode, 0 }, +{"lw", "I", "d,A", 0, (int) M_LW, match_never, INSN_MACRO }, +{"not", "I", "d,s", MATCH_XORI | MASK_IMM, MASK_XORI | MASK_IMM, match_opcode, INSN_ALIAS }, +{"ori", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, 0 }, +{"or", "C", "Cs,Cw,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", "C", "Cs,Ct,Cw", MATCH_C_OR, MASK_C_OR, match_opcode, INSN_ALIAS }, +{"or", "I", "d,s,t", MATCH_OR, MASK_OR, match_opcode, 0 }, +{"or", "I", "d,s,j", MATCH_ORI, MASK_ORI, match_opcode, INSN_ALIAS }, +{"auipc", "I", "d,u", MATCH_AUIPC, MASK_AUIPC, match_opcode, 0 }, +{"seqz", "I", "d,s", MATCH_SLTIU | ENCODE_ITYPE_IMM(1), MASK_SLTIU | MASK_IMM, match_opcode, INSN_ALIAS }, +{"snez", "I", "d,t", MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS }, +{"sltz", "I", "d,s", MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS }, +{"sgtz", "I", "d,t", MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS }, +{"slti", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS }, +{"slt", "I", "d,s,t", MATCH_SLT, MASK_SLT, match_opcode, 0 }, +{"slt", "I", "d,s,j", MATCH_SLTI, MASK_SLTI, match_opcode, 0 }, +{"sltiu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 }, +{"sltu", "I", "d,s,t", MATCH_SLTU, MASK_SLTU, match_opcode, 0 }, +{"sltu", "I", "d,s,j", MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS }, +{"sgt", "I", "d,t,s", MATCH_SLT, MASK_SLT, match_opcode, INSN_ALIAS }, +{"sgtu", "I", "d,t,s", MATCH_SLTU, MASK_SLTU, match_opcode, INSN_ALIAS }, +{"sb", "I", "t,q(s)", MATCH_SB, MASK_SB, match_opcode, 0 }, +{"sb", "I", "t,A,s", 0, (int) M_SB, match_never, INSN_MACRO }, +{"sh", "I", "t,q(s)", MATCH_SH, MASK_SH, match_opcode, 0 }, +{"sh", "I", "t,A,s", 0, (int) M_SH, match_never, INSN_MACRO }, +{"sw", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, INSN_ALIAS }, +{"sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS }, +{"sw", "I", "t,q(s)", MATCH_SW, MASK_SW, match_opcode, 0 }, +{"sw", "I", "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, +{"fence", "I", "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, +{"fence", "I", "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, +{"fence.i", "I", "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, +{"rdcycle", "I", "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, 0 }, +{"rdinstret", "I", "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, 0 }, +{"rdtime", "I", "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, 0 }, +{"rdcycleh", "32I", "d", MATCH_RDCYCLEH, MASK_RDCYCLEH, match_opcode, 0 }, +{"rdinstreth","32I", "d", MATCH_RDINSTRETH, MASK_RDINSTRETH, match_opcode, 0 }, +{"rdtimeh", "32I", "d", MATCH_RDTIMEH, MASK_RDTIMEH, match_opcode, 0 }, +{"ecall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{"scall", "I", "", MATCH_SCALL, MASK_SCALL, match_opcode, 0 }, +{"xori", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, 0 }, +{"xor", "C", "Cs,Cw,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", "C", "Cs,Ct,Cw", MATCH_C_XOR, MASK_C_XOR, match_opcode, INSN_ALIAS }, +{"xor", "I", "d,s,t", MATCH_XOR, MASK_XOR, match_opcode, 0 }, +{"xor", "I", "d,s,j", MATCH_XORI, MASK_XORI, match_opcode, INSN_ALIAS }, +{"lwu", "64I", "d,o(s)", MATCH_LWU, MASK_LWU, match_opcode, 0 }, +{"lwu", "64I", "d,A", 0, (int) M_LWU, match_never, INSN_MACRO }, +{"ld", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, INSN_ALIAS }, +{"ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, INSN_ALIAS }, +{"ld", "64I", "d,o(s)", MATCH_LD, MASK_LD, match_opcode, 0 }, +{"ld", "64I", "d,A", 0, (int) M_LD, match_never, INSN_MACRO }, +{"sd", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, INSN_ALIAS }, +{"sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS }, +{"sd", "64I", "t,q(s)", MATCH_SD, MASK_SD, match_opcode, 0 }, +{"sd", "64I", "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO }, +{"sext.w", "64C", "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW | MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +{"sext.w", "64I", "d,s", MATCH_ADDIW, MASK_ADDIW | MASK_IMM, match_opcode, INSN_ALIAS }, +{"addiw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addiw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, 0 }, +{"addw", "64C", "Cs,Cw,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", "64C", "Cs,Ct,Cw", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, INSN_ALIAS }, +{"addw", "64C", "d,CU,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS }, +{"addw", "64I", "d,s,t", MATCH_ADDW, MASK_ADDW, match_opcode, 0 }, +{"addw", "64I", "d,s,j", MATCH_ADDIW, MASK_ADDIW, match_opcode, INSN_ALIAS }, +{"negw", "64I", "d,t", MATCH_SUBW, MASK_SUBW | MASK_RS1, match_opcode, INSN_ALIAS }, /* sub 0 */ +{"slliw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, 0 }, +{"sllw", "64I", "d,s,t", MATCH_SLLW, MASK_SLLW, match_opcode, 0 }, +{"sllw", "64I", "d,s,<", MATCH_SLLIW, MASK_SLLIW, match_opcode, INSN_ALIAS }, +{"srliw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, 0 }, +{"srlw", "64I", "d,s,t", MATCH_SRLW, MASK_SRLW, match_opcode, 0 }, +{"srlw", "64I", "d,s,<", MATCH_SRLIW, MASK_SRLIW, match_opcode, INSN_ALIAS }, +{"sraiw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, 0 }, +{"sraw", "64I", "d,s,t", MATCH_SRAW, MASK_SRAW, match_opcode, 0 }, +{"sraw", "64I", "d,s,<", MATCH_SRAIW, MASK_SRAIW, match_opcode, INSN_ALIAS }, +{"subw", "64C", "Cs,Cw,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, INSN_ALIAS }, +{"subw", "64I", "d,s,t", MATCH_SUBW, MASK_SUBW, match_opcode, 0 }, + +/* Atomic memory operation instruction subset */ +{"lr.w", "A", "d,0(s)", MATCH_LR_W, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w", "A", "d,t,0(s)", MATCH_SC_W, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w", "A", "d,t,0(s)", MATCH_AMOADD_W, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w", "A", "d,t,0(s)", MATCH_AMOSWAP_W, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w", "A", "d,t,0(s)", MATCH_AMOAND_W, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w", "A", "d,t,0(s)", MATCH_AMOOR_W, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w", "A", "d,t,0(s)", MATCH_AMOXOR_W, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w", "A", "d,t,0(s)", MATCH_AMOMAX_W, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w", "A", "d,t,0(s)", MATCH_AMOMAXU_W, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w", "A", "d,t,0(s)", MATCH_AMOMIN_W, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w", "A", "d,t,0(s)", MATCH_AMOMINU_W, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.aq", "A", "d,0(s)", MATCH_LR_W | MASK_AQ, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.aq", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQ, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.aq", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQ, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.aq", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQ, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.aq", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQ, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.aq", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQ, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.aq", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQ, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.aq", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQ, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.aq", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQ, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.aq", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQ, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.aq", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQ, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.rl", "A", "d,0(s)", MATCH_LR_W | MASK_RL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.rl", "A", "d,t,0(s)", MATCH_SC_W | MASK_RL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.rl", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_RL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.rl", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_RL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.rl", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_RL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.rl", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_RL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.rl", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_RL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.rl", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_RL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.rl", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_RL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.rl", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_RL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.rl", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_RL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.w.sc", "A", "d,0(s)", MATCH_LR_W | MASK_AQRL, MASK_LR_W | MASK_AQRL, match_opcode, 0 }, +{"sc.w.sc", "A", "d,t,0(s)", MATCH_SC_W | MASK_AQRL, MASK_SC_W | MASK_AQRL, match_opcode, 0 }, +{"amoadd.w.sc", "A", "d,t,0(s)", MATCH_AMOADD_W | MASK_AQRL, MASK_AMOADD_W | MASK_AQRL, match_opcode, 0 }, +{"amoswap.w.sc", "A", "d,t,0(s)", MATCH_AMOSWAP_W | MASK_AQRL, MASK_AMOSWAP_W | MASK_AQRL, match_opcode, 0 }, +{"amoand.w.sc", "A", "d,t,0(s)", MATCH_AMOAND_W | MASK_AQRL, MASK_AMOAND_W | MASK_AQRL, match_opcode, 0 }, +{"amoor.w.sc", "A", "d,t,0(s)", MATCH_AMOOR_W | MASK_AQRL, MASK_AMOOR_W | MASK_AQRL, match_opcode, 0 }, +{"amoxor.w.sc", "A", "d,t,0(s)", MATCH_AMOXOR_W | MASK_AQRL, MASK_AMOXOR_W | MASK_AQRL, match_opcode, 0 }, +{"amomax.w.sc", "A", "d,t,0(s)", MATCH_AMOMAX_W | MASK_AQRL, MASK_AMOMAX_W | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.w.sc", "A", "d,t,0(s)", MATCH_AMOMAXU_W | MASK_AQRL, MASK_AMOMAXU_W | MASK_AQRL, match_opcode, 0 }, +{"amomin.w.sc", "A", "d,t,0(s)", MATCH_AMOMIN_W | MASK_AQRL, MASK_AMOMIN_W | MASK_AQRL, match_opcode, 0 }, +{"amominu.w.sc", "A", "d,t,0(s)", MATCH_AMOMINU_W | MASK_AQRL, MASK_AMOMINU_W | MASK_AQRL, match_opcode, 0 }, +{"lr.d", "64A", "d,0(s)", MATCH_LR_D, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d", "64A", "d,t,0(s)", MATCH_SC_D, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d", "64A", "d,t,0(s)", MATCH_AMOADD_D, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d", "64A", "d,t,0(s)", MATCH_AMOSWAP_D, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d", "64A", "d,t,0(s)", MATCH_AMOAND_D, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d", "64A", "d,t,0(s)", MATCH_AMOOR_D, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d", "64A", "d,t,0(s)", MATCH_AMOXOR_D, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d", "64A", "d,t,0(s)", MATCH_AMOMAX_D, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d", "64A", "d,t,0(s)", MATCH_AMOMAXU_D, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d", "64A", "d,t,0(s)", MATCH_AMOMIN_D, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d", "64A", "d,t,0(s)", MATCH_AMOMINU_D, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.aq", "64A", "d,0(s)", MATCH_LR_D | MASK_AQ, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.aq", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQ, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.aq", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQ, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.aq", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQ, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.aq", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQ, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.aq", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQ, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.aq", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQ, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQ, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQ, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.aq", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQ, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.aq", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQ, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.rl", "64A", "d,0(s)", MATCH_LR_D | MASK_RL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.rl", "64A", "d,t,0(s)", MATCH_SC_D | MASK_RL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.rl", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_RL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.rl", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_RL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.rl", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_RL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.rl", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_RL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.rl", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_RL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_RL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_RL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.rl", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_RL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.rl", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_RL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, +{"lr.d.sc", "64A", "d,0(s)", MATCH_LR_D | MASK_AQRL, MASK_LR_D | MASK_AQRL, match_opcode, 0 }, +{"sc.d.sc", "64A", "d,t,0(s)", MATCH_SC_D | MASK_AQRL, MASK_SC_D | MASK_AQRL, match_opcode, 0 }, +{"amoadd.d.sc", "64A", "d,t,0(s)", MATCH_AMOADD_D | MASK_AQRL, MASK_AMOADD_D | MASK_AQRL, match_opcode, 0 }, +{"amoswap.d.sc", "64A", "d,t,0(s)", MATCH_AMOSWAP_D | MASK_AQRL, MASK_AMOSWAP_D | MASK_AQRL, match_opcode, 0 }, +{"amoand.d.sc", "64A", "d,t,0(s)", MATCH_AMOAND_D | MASK_AQRL, MASK_AMOAND_D | MASK_AQRL, match_opcode, 0 }, +{"amoor.d.sc", "64A", "d,t,0(s)", MATCH_AMOOR_D | MASK_AQRL, MASK_AMOOR_D | MASK_AQRL, match_opcode, 0 }, +{"amoxor.d.sc", "64A", "d,t,0(s)", MATCH_AMOXOR_D | MASK_AQRL, MASK_AMOXOR_D | MASK_AQRL, match_opcode, 0 }, +{"amomax.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAX_D | MASK_AQRL, MASK_AMOMAX_D | MASK_AQRL, match_opcode, 0 }, +{"amomaxu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMAXU_D | MASK_AQRL, MASK_AMOMAXU_D | MASK_AQRL, match_opcode, 0 }, +{"amomin.d.sc", "64A", "d,t,0(s)", MATCH_AMOMIN_D | MASK_AQRL, MASK_AMOMIN_D | MASK_AQRL, match_opcode, 0 }, +{"amominu.d.sc", "64A", "d,t,0(s)", MATCH_AMOMINU_D | MASK_AQRL, MASK_AMOMINU_D | MASK_AQRL, match_opcode, 0 }, + +/* Multiply/Divide instruction subset */ +{"mul", "M", "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, +{"mulh", "M", "d,s,t", MATCH_MULH, MASK_MULH, match_opcode, 0 }, +{"mulhu", "M", "d,s,t", MATCH_MULHU, MASK_MULHU, match_opcode, 0 }, +{"mulhsu", "M", "d,s,t", MATCH_MULHSU, MASK_MULHSU, match_opcode, 0 }, +{"div", "M", "d,s,t", MATCH_DIV, MASK_DIV, match_opcode, 0 }, +{"divu", "M", "d,s,t", MATCH_DIVU, MASK_DIVU, match_opcode, 0 }, +{"rem", "M", "d,s,t", MATCH_REM, MASK_REM, match_opcode, 0 }, +{"remu", "M", "d,s,t", MATCH_REMU, MASK_REMU, match_opcode, 0 }, +{"mulw", "64M", "d,s,t", MATCH_MULW, MASK_MULW, match_opcode, 0 }, +{"divw", "64M", "d,s,t", MATCH_DIVW, MASK_DIVW, match_opcode, 0 }, +{"divuw", "64M", "d,s,t", MATCH_DIVUW, MASK_DIVUW, match_opcode, 0 }, +{"remw", "64M", "d,s,t", MATCH_REMW, MASK_REMW, match_opcode, 0 }, +{"remuw", "64M", "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, + +/* Single-precision floating-point instruction subset */ +{"frsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{"fssr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{"fssr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{"frcsr", "F", "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, +{"fscsr", "F", "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, +{"fscsr", "F", "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, +{"frrm", "F", "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, +{"fsrm", "F", "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, +{"fsrm", "F", "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, +{"frflags", "F", "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, +{"fsflags", "F", "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, +{"fsflags", "F", "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, +{"flw", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS }, +{"flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS }, +{"flw", "F", "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, 0 }, +{"flw", "F", "D,A,s", 0, (int) M_FLW, match_never, INSN_MACRO }, +{"fsw", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, INSN_ALIAS }, +{"fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS }, +{"fsw", "F", "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, 0 }, +{"fsw", "F", "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO }, +{"fmv.x.s", "F", "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 }, +{"fmv.s.x", "F", "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 }, +{"fmv.s", "F", "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.s", "F", "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.s", "F", "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.s", "F", "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, +{"fsgnjn.s", "F", "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, +{"fsgnjx.s", "F", "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, +{"fadd.s", "F", "D,S,T", MATCH_FADD_S | MASK_RM, MASK_FADD_S | MASK_RM, match_opcode, 0 }, +{"fadd.s", "F", "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, +{"fsub.s", "F", "D,S,T", MATCH_FSUB_S | MASK_RM, MASK_FSUB_S | MASK_RM, match_opcode, 0 }, +{"fsub.s", "F", "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, +{"fmul.s", "F", "D,S,T", MATCH_FMUL_S | MASK_RM, MASK_FMUL_S | MASK_RM, match_opcode, 0 }, +{"fmul.s", "F", "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, +{"fdiv.s", "F", "D,S,T", MATCH_FDIV_S | MASK_RM, MASK_FDIV_S | MASK_RM, match_opcode, 0 }, +{"fdiv.s", "F", "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, +{"fsqrt.s", "F", "D,S", MATCH_FSQRT_S | MASK_RM, MASK_FSQRT_S | MASK_RM, match_opcode, 0 }, +{"fsqrt.s", "F", "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, +{"fmin.s", "F", "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, +{"fmax.s", "F", "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, +{"fmadd.s", "F", "D,S,T,R", MATCH_FMADD_S | MASK_RM, MASK_FMADD_S | MASK_RM, match_opcode, 0 }, +{"fmadd.s", "F", "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, +{"fnmadd.s", "F", "D,S,T,R", MATCH_FNMADD_S | MASK_RM, MASK_FNMADD_S | MASK_RM, match_opcode, 0 }, +{"fnmadd.s", "F", "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, +{"fmsub.s", "F", "D,S,T,R", MATCH_FMSUB_S | MASK_RM, MASK_FMSUB_S | MASK_RM, match_opcode, 0 }, +{"fmsub.s", "F", "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, +{"fnmsub.s", "F", "D,S,T,R", MATCH_FNMSUB_S | MASK_RM, MASK_FNMSUB_S | MASK_RM, match_opcode, 0 }, +{"fnmsub.s", "F", "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, +{"fcvt.w.s", "F", "d,S", MATCH_FCVT_W_S | MASK_RM, MASK_FCVT_W_S | MASK_RM, match_opcode, 0 }, +{"fcvt.w.s", "F", "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, +{"fcvt.wu.s", "F", "d,S", MATCH_FCVT_WU_S | MASK_RM, MASK_FCVT_WU_S | MASK_RM, match_opcode, 0 }, +{"fcvt.wu.s", "F", "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, +{"fcvt.s.w", "F", "D,s", MATCH_FCVT_S_W | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{"fcvt.s.w", "F", "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, +{"fcvt.s.wu", "F", "D,s", MATCH_FCVT_S_WU | MASK_RM, MASK_FCVT_S_W | MASK_RM, match_opcode, 0 }, +{"fcvt.s.wu", "F", "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, +{"fclass.s", "F", "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, +{"feq.s", "F", "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, +{"flt.s", "F", "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{"fle.s", "F", "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{"fgt.s", "F", "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, +{"fge.s", "F", "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, +{"fcvt.l.s", "64F", "d,S", MATCH_FCVT_L_S | MASK_RM, MASK_FCVT_L_S | MASK_RM, match_opcode, 0 }, +{"fcvt.l.s", "64F", "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, +{"fcvt.lu.s", "64F", "d,S", MATCH_FCVT_LU_S | MASK_RM, MASK_FCVT_LU_S | MASK_RM, match_opcode, 0 }, +{"fcvt.lu.s", "64F", "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, +{"fcvt.s.l", "64F", "D,s", MATCH_FCVT_S_L | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{"fcvt.s.l", "64F", "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, +{"fcvt.s.lu", "64F", "D,s", MATCH_FCVT_S_LU | MASK_RM, MASK_FCVT_S_L | MASK_RM, match_opcode, 0 }, +{"fcvt.s.lu", "64F", "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, + +/* Double-precision floating-point instruction subset */ +{"fld", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS }, +{"fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, INSN_ALIAS }, +{"fld", "D", "D,o(s)", MATCH_FLD, MASK_FLD, match_opcode, 0 }, +{"fld", "D", "D,A,s", 0, (int) M_FLD, match_never, INSN_MACRO }, +{"fsd", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, INSN_ALIAS }, +{"fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS }, +{"fsd", "D", "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, 0 }, +{"fsd", "D", "T,A,s", 0, (int) M_FSD, match_never, INSN_MACRO }, +{"fmv.d", "D", "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fneg.d", "D", "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fabs.d", "D", "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, +{"fsgnj.d", "D", "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, +{"fsgnjn.d", "D", "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, +{"fsgnjx.d", "D", "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, +{"fadd.d", "D", "D,S,T", MATCH_FADD_D | MASK_RM, MASK_FADD_D | MASK_RM, match_opcode, 0 }, +{"fadd.d", "D", "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", "D", "D,S,T", MATCH_FSUB_D | MASK_RM, MASK_FSUB_D | MASK_RM, match_opcode, 0 }, +{"fsub.d", "D", "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", "D", "D,S,T", MATCH_FMUL_D | MASK_RM, MASK_FMUL_D | MASK_RM, match_opcode, 0 }, +{"fmul.d", "D", "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", "D", "D,S,T", MATCH_FDIV_D | MASK_RM, MASK_FDIV_D | MASK_RM, match_opcode, 0 }, +{"fdiv.d", "D", "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", "D", "D,S", MATCH_FSQRT_D | MASK_RM, MASK_FSQRT_D | MASK_RM, match_opcode, 0 }, +{"fsqrt.d", "D", "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fmin.d", "D", "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, +{"fmax.d", "D", "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, +{"fmadd.d", "D", "D,S,T,R", MATCH_FMADD_D | MASK_RM, MASK_FMADD_D | MASK_RM, match_opcode, 0 }, +{"fmadd.d", "D", "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", "D", "D,S,T,R", MATCH_FNMADD_D | MASK_RM, MASK_FNMADD_D | MASK_RM, match_opcode, 0 }, +{"fnmadd.d", "D", "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", "D", "D,S,T,R", MATCH_FMSUB_D | MASK_RM, MASK_FMSUB_D | MASK_RM, match_opcode, 0 }, +{"fmsub.d", "D", "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", "D", "D,S,T,R", MATCH_FNMSUB_D | MASK_RM, MASK_FNMSUB_D | MASK_RM, match_opcode, 0 }, +{"fnmsub.d", "D", "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", "D", "d,S", MATCH_FCVT_W_D | MASK_RM, MASK_FCVT_W_D | MASK_RM, match_opcode, 0 }, +{"fcvt.w.d", "D", "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", "D", "d,S", MATCH_FCVT_WU_D | MASK_RM, MASK_FCVT_WU_D | MASK_RM, match_opcode, 0 }, +{"fcvt.wu.d", "D", "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fcvt.d.w", "D", "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W | MASK_RM, match_opcode, 0 }, +{"fcvt.d.wu", "D", "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU | MASK_RM, match_opcode, 0 }, +{"fcvt.d.s", "D", "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S | MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", "D", "D,S", MATCH_FCVT_S_D | MASK_RM, MASK_FCVT_S_D | MASK_RM, match_opcode, 0 }, +{"fcvt.s.d", "D", "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fclass.d", "D", "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, +{"feq.d", "D", "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, +{"flt.d", "D", "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fle.d", "D", "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fgt.d", "D", "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, +{"fge.d", "D", "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, +{"fmv.x.d", "64D", "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, +{"fmv.d.x", "64D", "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, +{"fcvt.l.d", "64D", "d,S", MATCH_FCVT_L_D | MASK_RM, MASK_FCVT_L_D | MASK_RM, match_opcode, 0 }, +{"fcvt.l.d", "64D", "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", "64D", "d,S", MATCH_FCVT_LU_D | MASK_RM, MASK_FCVT_LU_D | MASK_RM, match_opcode, 0 }, +{"fcvt.lu.d", "64D", "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", "64D", "D,s", MATCH_FCVT_D_L | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{"fcvt.d.l", "64D", "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", "64D", "D,s", MATCH_FCVT_D_LU | MASK_RM, MASK_FCVT_D_L | MASK_RM, match_opcode, 0 }, +{"fcvt.d.lu", "64D", "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, + +/* Compressed instructions. */ +{"c.ebreak", "C", "", MATCH_C_EBREAK, MASK_C_EBREAK, match_opcode, 0 }, +{"c.jr", "C", "d", MATCH_C_JR, MASK_C_JR, match_rd_nonzero, 0 }, +{"c.jalr", "C", "d", MATCH_C_JALR, MASK_C_JALR, match_rd_nonzero, 0 }, +{"c.j", "C", "Ca", MATCH_C_J, MASK_C_J, match_opcode, 0 }, +{"c.jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, 0 }, +{"c.beqz", "C", "Cs,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, 0 }, +{"c.bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, 0 }, +{"c.lwsp", "C", "d,Cm(Cc)", MATCH_C_LWSP, MASK_C_LWSP, match_rd_nonzero, 0 }, +{"c.lw", "C", "Ct,Ck(Cs)", MATCH_C_LW, MASK_C_LW, match_opcode, 0 }, +{"c.swsp", "C", "CV,CM(Cc)", MATCH_C_SWSP, MASK_C_SWSP, match_opcode, 0 }, +{"c.sw", "C", "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, 0 }, +{"c.nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, 0 }, +{"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, +{"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, +{"c.li", "C", "d,Cj", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, +{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, +{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +{"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 }, +{"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, +{"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, +{"c.and", "C", "Cs,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, 0 }, +{"c.or", "C", "Cs,Ct", MATCH_C_OR, MASK_C_OR, match_opcode, 0 }, +{"c.xor", "C", "Cs,Ct", MATCH_C_XOR, MASK_C_XOR, match_opcode, 0 }, +{"c.slli", "C", "d,C>", MATCH_C_SLLI, MASK_C_SLLI, match_rd_nonzero, 0 }, +{"c.srli", "C", "Cs,C>", MATCH_C_SRLI, MASK_C_SRLI, match_opcode, 0 }, +{"c.srai", "C", "Cs,C>", MATCH_C_SRAI, MASK_C_SRAI, match_opcode, 0 }, +{"c.andi", "C", "Cs,Cj", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, 0 }, +{"c.addiw", "64C", "d,Cj", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, 0 }, +{"c.addw", "64C", "Cs,Ct", MATCH_C_ADDW, MASK_C_ADDW, match_opcode, 0 }, +{"c.subw", "64C", "Cs,Ct", MATCH_C_SUBW, MASK_C_SUBW, match_opcode, 0 }, +{"c.ldsp", "64C", "d,Cn(Cc)", MATCH_C_LDSP, MASK_C_LDSP, match_rd_nonzero, 0 }, +{"c.ld", "64C", "Ct,Cl(Cs)", MATCH_C_LD, MASK_C_LD, match_opcode, 0 }, +{"c.sdsp", "64C", "CV,CN(Cc)", MATCH_C_SDSP, MASK_C_SDSP, match_opcode, 0 }, +{"c.sd", "64C", "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, 0 }, +{"c.fldsp", "C", "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, 0 }, +{"c.fld", "C", "CD,Cl(Cs)", MATCH_C_FLD, MASK_C_FLD, match_opcode, 0 }, +{"c.fsdsp", "C", "CT,CN(Cc)", MATCH_C_FSDSP, MASK_C_FSDSP, match_opcode, 0 }, +{"c.fsd", "C", "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, 0 }, +{"c.flwsp", "32C", "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, 0 }, +{"c.flw", "32C", "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, 0 }, +{"c.fswsp", "32C", "CT,CM(Cc)", MATCH_C_FSWSP, MASK_C_FSWSP, match_opcode, 0 }, +{"c.fsw", "32C", "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, 0 }, + +/* Supervisor instructions */ +{"csrr", "I", "d,E", MATCH_CSRRS, MASK_CSRRS | MASK_RS1, match_opcode, 0 }, +{"csrwi", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 }, +{"csrw", "I", "E,s", MATCH_CSRRW, MASK_CSRRW | MASK_RD, match_opcode, 0 }, +{"csrw", "I", "E,Z", MATCH_CSRRWI, MASK_CSRRWI | MASK_RD, match_opcode, 0 }, +{"csrsi", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 }, +{"csrs", "I", "E,s", MATCH_CSRRS, MASK_CSRRS | MASK_RD, match_opcode, 0 }, +{"csrs", "I", "E,Z", MATCH_CSRRSI, MASK_CSRRSI | MASK_RD, match_opcode, 0 }, +{"csrci", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 }, +{"csrc", "I", "E,s", MATCH_CSRRC, MASK_CSRRC | MASK_RD, match_opcode, 0 }, +{"csrc", "I", "E,Z", MATCH_CSRRCI, MASK_CSRRCI | MASK_RD, match_opcode, 0 }, +{"csrrw", "I", "d,E,s", MATCH_CSRRW, MASK_CSRRW, match_opcode, 0 }, +{"csrrw", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{"csrrs", "I", "d,E,s", MATCH_CSRRS, MASK_CSRRS, match_opcode, 0 }, +{"csrrs", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{"csrrc", "I", "d,E,s", MATCH_CSRRC, MASK_CSRRC, match_opcode, 0 }, +{"csrrc", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{"csrrwi", "I", "d,E,Z", MATCH_CSRRWI, MASK_CSRRWI, match_opcode, 0 }, +{"csrrsi", "I", "d,E,Z", MATCH_CSRRSI, MASK_CSRRSI, match_opcode, 0 }, +{"csrrci", "I", "d,E,Z", MATCH_CSRRCI, MASK_CSRRCI, match_opcode, 0 }, +{"uret", "I", "", MATCH_URET, MASK_URET, match_opcode, 0 }, +{"sret", "I", "", MATCH_SRET, MASK_SRET, match_opcode, 0 }, +{"hret", "I", "", MATCH_HRET, MASK_HRET, match_opcode, 0 }, +{"mret", "I", "", MATCH_MRET, MASK_MRET, match_opcode, 0 }, +{"dret", "I", "", MATCH_DRET, MASK_DRET, match_opcode, 0 }, +{"sfence.vm", "I", "", MATCH_SFENCE_VM, MASK_SFENCE_VM | MASK_RS1, match_opcode, 0 }, +{"sfence.vm", "I", "s", MATCH_SFENCE_VM, MASK_SFENCE_VM, match_opcode, 0 }, +{"wfi", "I", "", MATCH_WFI, MASK_WFI, match_opcode, 0 }, + +/* Terminate the list. */ +{0, 0, 0, 0, 0, 0, 0} +}; |