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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-opc.c6
2 files changed, 9 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 8a6ea15..8c0648a 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR UAO immediate operand.
+
2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 1cd5c1b..ae06ee3 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1878,9 +1878,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
case AARCH64_OPND_PSTATEFIELD:
assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
- /* MSR PAN, #uimm4
+ /* MSR UAO, #uimm4
+ MSR PAN, #uimm4
The immediate must be #0 or #1. */
- if (opnd->pstatefield == 0x04 /* PAN. */
+ if ((opnd->pstatefield == 0x03 /* UAO. */
+ || opnd->pstatefield == 0x04) /* PAN. */
&& opnds[1].imm.value > 1)
{
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);