diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/fr30-asm.c | 12 | ||||
| -rw-r--r-- | opcodes/fr30-desc.h | 3 | ||||
| -rw-r--r-- | opcodes/fr30-dis.c | 8 | ||||
| -rw-r--r-- | opcodes/fr30-ibld.c | 39 | ||||
| -rw-r--r-- | opcodes/fr30-opc.c | 4 | ||||
| -rw-r--r-- | opcodes/m32r-asm.c | 6 | ||||
| -rw-r--r-- | opcodes/m32r-desc.h | 3 | ||||
| -rw-r--r-- | opcodes/m32r-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/m32r-ibld.c | 15 | ||||
| -rw-r--r-- | opcodes/m32r-opc.c | 36 | ||||
| -rw-r--r-- | opcodes/m32r-opinst.c | 338 |
12 files changed, 222 insertions, 250 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index b4c9bfa..4834d16 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +1999-08-04 Doug Evans <devans@casey.cygnus.com> + + * fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. + * m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * m32r-opinst.c: Rebuild. + Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> * hppa-dis.c (print_insn_hppa): Replace 'f' by 'v'. Prefix float diff --git a/opcodes/fr30-asm.c b/opcodes/fr30-asm.c index 5f5ccdc..b9f8010 100644 --- a/opcodes/fr30-asm.c +++ b/opcodes/fr30-asm.c @@ -177,7 +177,9 @@ fr30_cgen_parse_operand (cd, opindex, strp, fields) const char ** strp; CGEN_FIELDS * fields; { - const char * errmsg; + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk; switch (opindex) { @@ -188,13 +190,13 @@ fr30_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_cr_names, & fields->f_CRj); break; case FR30_OPERAND_R13 : - errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r13, & fields->f_nil); + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r13, & junk); break; case FR30_OPERAND_R14 : - errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r14, & fields->f_nil); + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r14, & junk); break; case FR30_OPERAND_R15 : - errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r15, & fields->f_nil); + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_r15, & junk); break; case FR30_OPERAND_RI : errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_gr_names, & fields->f_Ri); @@ -265,7 +267,7 @@ fr30_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_signed_integer (cd, strp, FR30_OPERAND_M4, &fields->f_m4); break; case FR30_OPERAND_PS : - errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_ps, & fields->f_nil); + errmsg = cgen_parse_keyword (cd, strp, & fr30_cgen_opval_h_ps, & junk); break; case FR30_OPERAND_REGLIST_HI_LD : errmsg = parse_hi_register_list_ld (cd, strp, FR30_OPERAND_REGLIST_HI_LD, &fields->f_reglist_hi_ld); diff --git a/opcodes/fr30-desc.h b/opcodes/fr30-desc.h index 0289156..a1ff45e 100644 --- a/opcodes/fr30-desc.h +++ b/opcodes/fr30-desc.h @@ -35,6 +35,9 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INSN_LSB0_P 0 +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + /* Maximum size of any insn (in bytes). */ #define CGEN_MAX_INSN_SIZE 6 diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index 0d7c18c..c42915b 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -193,13 +193,13 @@ fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_keyword (cd, info, & fr30_cgen_opval_cr_names, fields->f_CRj, 0); break; case FR30_OPERAND_R13 : - print_keyword (cd, info, & fr30_cgen_opval_h_r13, fields->f_nil, 0); + print_keyword (cd, info, & fr30_cgen_opval_h_r13, 0, 0); break; case FR30_OPERAND_R14 : - print_keyword (cd, info, & fr30_cgen_opval_h_r14, fields->f_nil, 0); + print_keyword (cd, info, & fr30_cgen_opval_h_r14, 0, 0); break; case FR30_OPERAND_R15 : - print_keyword (cd, info, & fr30_cgen_opval_h_r15, fields->f_nil, 0); + print_keyword (cd, info, & fr30_cgen_opval_h_r15, 0, 0); break; case FR30_OPERAND_RI : print_keyword (cd, info, & fr30_cgen_opval_gr_names, fields->f_Ri, 0); @@ -262,7 +262,7 @@ fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_m4 (cd, info, fields->f_m4, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length); break; case FR30_OPERAND_PS : - print_keyword (cd, info, & fr30_cgen_opval_h_ps, fields->f_nil, 0); + print_keyword (cd, info, & fr30_cgen_opval_h_ps, 0, 0); break; case FR30_OPERAND_REGLIST_HI_LD : print_hi_register_list_ld (cd, info, fields->f_reglist_hi_ld, 0, pc, length); diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c index 386613d..2aa4458 100644 --- a/opcodes/fr30-ibld.c +++ b/opcodes/fr30-ibld.c @@ -579,7 +579,7 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) CGEN_INSN_BYTES_PTR buffer; bfd_vma pc; { - const char * errmsg; + const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); switch (opindex) @@ -591,13 +591,10 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) errmsg = insert_normal (cd, fields->f_CRj, 0, 16, 8, 4, 16, total_length, buffer); break; case FR30_OPERAND_R13 : - errmsg = insert_normal (cd, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); break; case FR30_OPERAND_R14 : - errmsg = insert_normal (cd, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); break; case FR30_OPERAND_R15 : - errmsg = insert_normal (cd, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); break; case FR30_OPERAND_RI : errmsg = insert_normal (cd, fields->f_Ri, 0, 0, 12, 4, 16, total_length, buffer); @@ -699,7 +696,6 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) } break; case FR30_OPERAND_PS : - errmsg = insert_normal (cd, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); break; case FR30_OPERAND_REGLIST_HI_LD : errmsg = insert_normal (cd, fields->f_reglist_hi_ld, 0, 0, 8, 8, 16, total_length, buffer); @@ -755,6 +751,8 @@ fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc) } /* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. This function is basically just a big switch statement. Earlier versions used tables to look up the function to use, but @@ -777,7 +775,8 @@ fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) CGEN_FIELDS * fields; bfd_vma pc; { - int length; + /* Assume success (for those operands that are nops). */ + int length = 1; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); switch (opindex) @@ -789,13 +788,10 @@ fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) length = extract_normal (cd, ex_info, insn_value, 0, 16, 8, 4, 16, total_length, pc, & fields->f_CRj); break; case FR30_OPERAND_R13 : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); break; case FR30_OPERAND_R14 : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); break; case FR30_OPERAND_R15 : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); break; case FR30_OPERAND_RI : length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 16, total_length, pc, & fields->f_Ri); @@ -899,7 +895,6 @@ fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) } break; case FR30_OPERAND_PS : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); break; case FR30_OPERAND_REGLIST_HI_LD : length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 16, total_length, pc, & fields->f_reglist_hi_ld); @@ -989,13 +984,13 @@ fr30_cgen_get_int_operand (cd, opindex, fields) value = fields->f_CRj; break; case FR30_OPERAND_R13 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_R14 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_R15 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_RI : value = fields->f_Ri; @@ -1058,7 +1053,7 @@ fr30_cgen_get_int_operand (cd, opindex, fields) value = fields->f_m4; break; case FR30_OPERAND_PS : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_REGLIST_HI_LD : value = fields->f_reglist_hi_ld; @@ -1118,13 +1113,13 @@ fr30_cgen_get_vma_operand (cd, opindex, fields) value = fields->f_CRj; break; case FR30_OPERAND_R13 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_R14 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_R15 : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_RI : value = fields->f_Ri; @@ -1187,7 +1182,7 @@ fr30_cgen_get_vma_operand (cd, opindex, fields) value = fields->f_m4; break; case FR30_OPERAND_PS : - value = fields->f_nil; + value = 0; break; case FR30_OPERAND_REGLIST_HI_LD : value = fields->f_reglist_hi_ld; @@ -1251,13 +1246,10 @@ fr30_cgen_set_int_operand (cd, opindex, fields, value) fields->f_CRj = value; break; case FR30_OPERAND_R13 : - fields->f_nil = value; break; case FR30_OPERAND_R14 : - fields->f_nil = value; break; case FR30_OPERAND_R15 : - fields->f_nil = value; break; case FR30_OPERAND_RI : fields->f_Ri = value; @@ -1320,7 +1312,6 @@ fr30_cgen_set_int_operand (cd, opindex, fields, value) fields->f_m4 = value; break; case FR30_OPERAND_PS : - fields->f_nil = value; break; case FR30_OPERAND_REGLIST_HI_LD : fields->f_reglist_hi_ld = value; @@ -1377,13 +1368,10 @@ fr30_cgen_set_vma_operand (cd, opindex, fields, value) fields->f_CRj = value; break; case FR30_OPERAND_R13 : - fields->f_nil = value; break; case FR30_OPERAND_R14 : - fields->f_nil = value; break; case FR30_OPERAND_R15 : - fields->f_nil = value; break; case FR30_OPERAND_RI : fields->f_Ri = value; @@ -1446,7 +1434,6 @@ fr30_cgen_set_vma_operand (cd, opindex, fields, value) fields->f_m4 = value; break; case FR30_OPERAND_PS : - fields->f_nil = value; break; case FR30_OPERAND_REGLIST_HI_LD : fields->f_reglist_hi_ld = value; diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c index 302100d..5ea7e0a 100644 --- a/opcodes/fr30-opc.c +++ b/opcodes/fr30-opc.c @@ -1182,11 +1182,11 @@ static const CGEN_IFMT ifmt_ldi8m = { }; static const CGEN_IFMT ifmt_ldi20m = { - 16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 } + 16, 32, 0xff00, { F (F_OP1), F (F_OP2), F (F_RI), F (F_I20), 0 } }; static const CGEN_IFMT ifmt_ldi32m = { - 16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 } + 16, 48, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), F (F_I32), 0 } }; #undef F diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 378cd73..0d67c92 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -216,7 +216,9 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) const char ** strp; CGEN_FIELDS * fields; { - const char * errmsg; + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk; switch (opindex) { @@ -248,7 +250,7 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields) errmsg = cgen_parse_keyword (cd, strp, & m32r_cgen_opval_gr_names, & fields->f_r1); break; case M32R_OPERAND_HASH : - errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &fields->f_nil); + errmsg = parse_hash (cd, strp, M32R_OPERAND_HASH, &junk); break; case M32R_OPERAND_HI16 : errmsg = parse_hi16 (cd, strp, M32R_OPERAND_HI16, &fields->f_hi16); diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index 6a3636c..f83dab5 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -35,6 +35,9 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_INSN_LSB0_P 0 +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + /* Maximum size of any insn (in bytes). */ #define CGEN_MAX_INSN_SIZE 4 diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 48c591a..f4fd199 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -180,7 +180,7 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0); break; case M32R_OPERAND_HASH : - print_hash (cd, info, fields->f_nil, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); break; case M32R_OPERAND_HI16 : print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index fa15d7e..5b78547 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -579,7 +579,7 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) CGEN_INSN_BYTES_PTR buffer; bfd_vma pc; { - const char * errmsg; + const char * errmsg = NULL; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); switch (opindex) @@ -612,7 +612,6 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); break; case M32R_OPERAND_HASH : - errmsg = insert_normal (cd, fields->f_nil, 0, 0, 0, 0, 0, total_length, buffer); break; case M32R_OPERAND_HI16 : errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer); @@ -665,6 +664,8 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc) } /* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. This function is basically just a big switch statement. Earlier versions used tables to look up the function to use, but @@ -687,7 +688,8 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) CGEN_FIELDS * fields; bfd_vma pc; { - int length; + /* Assume success (for those operands that are nops). */ + int length = 1; unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); switch (opindex) @@ -723,7 +725,6 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); break; case M32R_OPERAND_HASH : - length = extract_normal (cd, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil); break; case M32R_OPERAND_HI16 : length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16); @@ -816,7 +817,7 @@ m32r_cgen_get_int_operand (cd, opindex, fields) value = fields->f_r1; break; case M32R_OPERAND_HASH : - value = fields->f_nil; + value = 0; break; case M32R_OPERAND_HI16 : value = fields->f_hi16; @@ -894,7 +895,7 @@ m32r_cgen_get_vma_operand (cd, opindex, fields) value = fields->f_r1; break; case M32R_OPERAND_HASH : - value = fields->f_nil; + value = 0; break; case M32R_OPERAND_HI16 : value = fields->f_hi16; @@ -976,7 +977,6 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value) fields->f_r1 = value; break; case M32R_OPERAND_HASH : - fields->f_nil = value; break; case M32R_OPERAND_HI16 : fields->f_hi16 = value; @@ -1051,7 +1051,6 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value) fields->f_r1 = value; break; case M32R_OPERAND_HASH : - fields->f_nil = value; break; case M32R_OPERAND_HI16 : fields->f_hi16 = value; diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 43edf9a..d4504fe 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -798,43 +798,43 @@ static const CGEN_IFMT ifmt_bra24r = { }; static const CGEN_IFMT ifmt_ld_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_ld_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_ldb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_ldb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_ldh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_ldh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_ldub_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_ldub_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_lduh_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_lduh_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_pop = { @@ -846,35 +846,35 @@ static const CGEN_IFMT ifmt_ldi8a = { }; static const CGEN_IFMT ifmt_ldi16a = { - 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0ff0000, { F (F_OP1), F (F_OP2), F (F_R2), F (F_R1), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_st_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_st_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_stb_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_stb_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_sth_2 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0f0, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; static const CGEN_IFMT ifmt_sth_d2 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } + 32, 32, 0xf0f00000, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), F (F_SIMM16), 0 } }; static const CGEN_IFMT ifmt_push = { - 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } + 16, 16, 0xf0ff, { F (F_OP1), F (F_OP2), F (F_R1), F (F_R2), 0 } }; #undef F diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c index 7f3a49f..f9d1e31 100644 --- a/opcodes/m32r-opinst.c +++ b/opcodes/m32r-opinst.c @@ -37,46 +37,46 @@ with this program; if not, write to the Free Software Foundation, Inc., #define COND_REF CGEN_OPINST_COND_REF #define OP_ENT(op) CONCAT2 (M32R_OPERAND_,op) -static const CGEN_OPINST fmt_empty_ops[] = { +static const CGEN_OPINST sfmt_empty_ops[] = { { END } }; -static const CGEN_OPINST fmt_add_ops[] = { +static const CGEN_OPINST sfmt_add_ops[] = { { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_add3_ops[] = { +static const CGEN_OPINST sfmt_add3_ops[] = { { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_and3_ops[] = { +static const CGEN_OPINST sfmt_and3_ops[] = { { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_or3_ops[] = { +static const CGEN_OPINST sfmt_or3_ops[] = { { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_addi_ops[] = { +static const CGEN_OPINST sfmt_addi_ops[] = { { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_addv_ops[] = { +static const CGEN_OPINST sfmt_addv_ops[] = { { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, @@ -84,7 +84,7 @@ static const CGEN_OPINST fmt_addv_ops[] = { { END } }; -static const CGEN_OPINST fmt_addv3_ops[] = { +static const CGEN_OPINST sfmt_addv3_ops[] = { { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, @@ -92,7 +92,7 @@ static const CGEN_OPINST fmt_addv3_ops[] = { { END } }; -static const CGEN_OPINST fmt_addx_ops[] = { +static const CGEN_OPINST sfmt_addx_ops[] = { { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, @@ -101,21 +101,21 @@ static const CGEN_OPINST fmt_addx_ops[] = { { END } }; -static const CGEN_OPINST fmt_bc8_ops[] = { +static const CGEN_OPINST sfmt_bc8_ops[] = { { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, { END } }; -static const CGEN_OPINST fmt_bc24_ops[] = { +static const CGEN_OPINST sfmt_bc24_ops[] = { { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, { END } }; -static const CGEN_OPINST fmt_beq_ops[] = { +static const CGEN_OPINST sfmt_beq_ops[] = { { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, @@ -123,14 +123,14 @@ static const CGEN_OPINST fmt_beq_ops[] = { { END } }; -static const CGEN_OPINST fmt_beqz_ops[] = { +static const CGEN_OPINST sfmt_beqz_ops[] = { { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, { END } }; -static const CGEN_OPINST fmt_bl8_ops[] = { +static const CGEN_OPINST sfmt_bl8_ops[] = { { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, @@ -138,7 +138,7 @@ static const CGEN_OPINST fmt_bl8_ops[] = { { END } }; -static const CGEN_OPINST fmt_bl24_ops[] = { +static const CGEN_OPINST sfmt_bl24_ops[] = { { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, @@ -146,40 +146,40 @@ static const CGEN_OPINST fmt_bl24_ops[] = { { END } }; -static const CGEN_OPINST fmt_bra8_ops[] = { +static const CGEN_OPINST sfmt_bra8_ops[] = { { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_bra24_ops[] = { +static const CGEN_OPINST sfmt_bra24_ops[] = { { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_cmp_ops[] = { +static const CGEN_OPINST sfmt_cmp_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_cmpi_ops[] = { +static const CGEN_OPINST sfmt_cmpi_ops[] = { { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_div_ops[] = { +static const CGEN_OPINST sfmt_div_ops[] = { { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF }, { END } }; -static const CGEN_OPINST fmt_jl_ops[] = { +static const CGEN_OPINST sfmt_jl_ops[] = { { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "h_gr_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 }, @@ -187,58 +187,28 @@ static const CGEN_OPINST fmt_jl_ops[] = { { END } }; -static const CGEN_OPINST fmt_jmp_ops[] = { +static const CGEN_OPINST sfmt_jmp_ops[] = { { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_ld_ops[] = { +static const CGEN_OPINST sfmt_ld_ops[] = { { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_ld_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, +static const CGEN_OPINST sfmt_ld_d_ops[] = { + { INPUT, "h_memory_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_ldb_ops[] = { - { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, - { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, - { END } -}; - -static const CGEN_OPINST fmt_ldb_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, - { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, - { END } -}; - -static const CGEN_OPINST fmt_ldh_ops[] = { - { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, - { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, - { END } -}; - -static const CGEN_OPINST fmt_ldh_d_ops[] = { - { INPUT, "h_memory_add__VM_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, - { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, - { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, - { END } -}; - -static const CGEN_OPINST fmt_ld_plus_ops[] = { +static const CGEN_OPINST sfmt_ld_plus_ops[] = { { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, @@ -246,25 +216,25 @@ static const CGEN_OPINST fmt_ld_plus_ops[] = { { END } }; -static const CGEN_OPINST fmt_ld24_ops[] = { +static const CGEN_OPINST sfmt_ld24_ops[] = { { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_ldi8_ops[] = { +static const CGEN_OPINST sfmt_ldi8_ops[] = { { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_ldi16_ops[] = { +static const CGEN_OPINST sfmt_ldi16_ops[] = { { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_lock_ops[] = { +static const CGEN_OPINST sfmt_lock_ops[] = { { INPUT, "h_memory_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, @@ -272,7 +242,7 @@ static const CGEN_OPINST fmt_lock_ops[] = { { END } }; -static const CGEN_OPINST fmt_machi_ops[] = { +static const CGEN_OPINST sfmt_machi_ops[] = { { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, @@ -280,55 +250,55 @@ static const CGEN_OPINST fmt_machi_ops[] = { { END } }; -static const CGEN_OPINST fmt_mulhi_ops[] = { +static const CGEN_OPINST sfmt_mulhi_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_mv_ops[] = { +static const CGEN_OPINST sfmt_mv_ops[] = { { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_mvfachi_ops[] = { +static const CGEN_OPINST sfmt_mvfachi_ops[] = { { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_mvfc_ops[] = { +static const CGEN_OPINST sfmt_mvfc_ops[] = { { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_mvtachi_ops[] = { +static const CGEN_OPINST sfmt_mvtachi_ops[] = { { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_mvtc_ops[] = { +static const CGEN_OPINST sfmt_mvtc_ops[] = { { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_nop_ops[] = { +static const CGEN_OPINST sfmt_nop_ops[] = { { END } }; -static const CGEN_OPINST fmt_rac_ops[] = { +static const CGEN_OPINST sfmt_rac_ops[] = { { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_rte_ops[] = { +static const CGEN_OPINST sfmt_rte_ops[] = { { INPUT, "h_bbpsw", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 }, { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, { INPUT, "h_cr_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 }, @@ -340,72 +310,72 @@ static const CGEN_OPINST fmt_rte_ops[] = { { END } }; -static const CGEN_OPINST fmt_seth_ops[] = { +static const CGEN_OPINST sfmt_seth_ops[] = { { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_sll3_ops[] = { +static const CGEN_OPINST sfmt_sll3_ops[] = { { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 }, { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_slli_ops[] = { +static const CGEN_OPINST sfmt_slli_ops[] = { { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 }, { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, { END } }; -static const CGEN_OPINST fmt_st_ops[] = { +static const CGEN_OPINST sfmt_st_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_st_d_ops[] = { +static const CGEN_OPINST sfmt_st_d_ops[] = { { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_stb_ops[] = { +static const CGEN_OPINST sfmt_stb_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_stb_d_ops[] = { +static const CGEN_OPINST sfmt_stb_d_ops[] = { { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, + { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_sth_ops[] = { +static const CGEN_OPINST sfmt_sth_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_sth_d_ops[] = { +static const CGEN_OPINST sfmt_sth_d_ops[] = { { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, - { OUTPUT, "h_memory_add__VM_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, + { OUTPUT, "h_memory_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, { END } }; -static const CGEN_OPINST fmt_st_plus_ops[] = { +static const CGEN_OPINST sfmt_st_plus_ops[] = { { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, @@ -413,7 +383,7 @@ static const CGEN_OPINST fmt_st_plus_ops[] = { { END } }; -static const CGEN_OPINST fmt_trap_ops[] = { +static const CGEN_OPINST sfmt_trap_ops[] = { { INPUT, "h_bpsw", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 }, { INPUT, "h_cr_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 }, { INPUT, "h_psw", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 }, @@ -428,7 +398,7 @@ static const CGEN_OPINST fmt_trap_ops[] = { { END } }; -static const CGEN_OPINST fmt_unlock_ops[] = { +static const CGEN_OPINST sfmt_unlock_ops[] = { { INPUT, "h_lock", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 }, { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF }, { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF }, @@ -447,105 +417,105 @@ static const CGEN_OPINST fmt_unlock_ops[] = { static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = { 0, - & fmt_add_ops[0], - & fmt_add3_ops[0], - & fmt_add_ops[0], - & fmt_and3_ops[0], - & fmt_add_ops[0], - & fmt_or3_ops[0], - & fmt_add_ops[0], - & fmt_and3_ops[0], - & fmt_addi_ops[0], - & fmt_addv_ops[0], - & fmt_addv3_ops[0], - & fmt_addx_ops[0], - & fmt_bc8_ops[0], - & fmt_bc24_ops[0], - & fmt_beq_ops[0], - & fmt_beqz_ops[0], - & fmt_beqz_ops[0], - & fmt_beqz_ops[0], - & fmt_beqz_ops[0], - & fmt_beqz_ops[0], - & fmt_beqz_ops[0], - & fmt_bl8_ops[0], - & fmt_bl24_ops[0], - & fmt_bc8_ops[0], - & fmt_bc24_ops[0], - & fmt_beq_ops[0], - & fmt_bra8_ops[0], - & fmt_bra24_ops[0], - & fmt_cmp_ops[0], - & fmt_cmpi_ops[0], - & fmt_cmp_ops[0], - & fmt_cmpi_ops[0], - & fmt_div_ops[0], - & fmt_div_ops[0], - & fmt_div_ops[0], - & fmt_div_ops[0], - & fmt_jl_ops[0], - & fmt_jmp_ops[0], - & fmt_ld_ops[0], - & fmt_ld_d_ops[0], - & fmt_ldb_ops[0], - & fmt_ldb_d_ops[0], - & fmt_ldh_ops[0], - & fmt_ldh_d_ops[0], - & fmt_ldb_ops[0], - & fmt_ldb_d_ops[0], - & fmt_ldh_ops[0], - & fmt_ldh_d_ops[0], - & fmt_ld_plus_ops[0], - & fmt_ld24_ops[0], - & fmt_ldi8_ops[0], - & fmt_ldi16_ops[0], - & fmt_lock_ops[0], - & fmt_machi_ops[0], - & fmt_machi_ops[0], - & fmt_machi_ops[0], - & fmt_machi_ops[0], - & fmt_add_ops[0], - & fmt_mulhi_ops[0], - & fmt_mulhi_ops[0], - & fmt_mulhi_ops[0], - & fmt_mulhi_ops[0], - & fmt_mv_ops[0], - & fmt_mvfachi_ops[0], - & fmt_mvfachi_ops[0], - & fmt_mvfachi_ops[0], - & fmt_mvfc_ops[0], - & fmt_mvtachi_ops[0], - & fmt_mvtachi_ops[0], - & fmt_mvtc_ops[0], - & fmt_mv_ops[0], - & fmt_nop_ops[0], - & fmt_mv_ops[0], - & fmt_rac_ops[0], - & fmt_rac_ops[0], - & fmt_rte_ops[0], - & fmt_seth_ops[0], - & fmt_add_ops[0], - & fmt_sll3_ops[0], - & fmt_slli_ops[0], - & fmt_add_ops[0], - & fmt_sll3_ops[0], - & fmt_slli_ops[0], - & fmt_add_ops[0], - & fmt_sll3_ops[0], - & fmt_slli_ops[0], - & fmt_st_ops[0], - & fmt_st_d_ops[0], - & fmt_stb_ops[0], - & fmt_stb_d_ops[0], - & fmt_sth_ops[0], - & fmt_sth_d_ops[0], - & fmt_st_plus_ops[0], - & fmt_st_plus_ops[0], - & fmt_add_ops[0], - & fmt_addv_ops[0], - & fmt_addx_ops[0], - & fmt_trap_ops[0], - & fmt_unlock_ops[0], + & sfmt_add_ops[0], + & sfmt_add3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_add_ops[0], + & sfmt_or3_ops[0], + & sfmt_add_ops[0], + & sfmt_and3_ops[0], + & sfmt_addi_ops[0], + & sfmt_addv_ops[0], + & sfmt_addv3_ops[0], + & sfmt_addx_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_beqz_ops[0], + & sfmt_bl8_ops[0], + & sfmt_bl24_ops[0], + & sfmt_bc8_ops[0], + & sfmt_bc24_ops[0], + & sfmt_beq_ops[0], + & sfmt_bra8_ops[0], + & sfmt_bra24_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_cmp_ops[0], + & sfmt_cmpi_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_div_ops[0], + & sfmt_jl_ops[0], + & sfmt_jmp_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ld_ops[0], + & sfmt_ld_d_ops[0], + & sfmt_ld_plus_ops[0], + & sfmt_ld24_ops[0], + & sfmt_ldi8_ops[0], + & sfmt_ldi16_ops[0], + & sfmt_lock_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_ops[0], + & sfmt_machi_ops[0], + & sfmt_add_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mulhi_ops[0], + & sfmt_mv_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfachi_ops[0], + & sfmt_mvfc_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtachi_ops[0], + & sfmt_mvtc_ops[0], + & sfmt_mv_ops[0], + & sfmt_nop_ops[0], + & sfmt_mv_ops[0], + & sfmt_rac_ops[0], + & sfmt_rac_ops[0], + & sfmt_rte_ops[0], + & sfmt_seth_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_add_ops[0], + & sfmt_sll3_ops[0], + & sfmt_slli_ops[0], + & sfmt_st_ops[0], + & sfmt_st_d_ops[0], + & sfmt_stb_ops[0], + & sfmt_stb_d_ops[0], + & sfmt_sth_ops[0], + & sfmt_sth_d_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_st_plus_ops[0], + & sfmt_add_ops[0], + & sfmt_addv_ops[0], + & sfmt_addx_ops[0], + & sfmt_trap_ops[0], + & sfmt_unlock_ops[0], }; /* Function to call before using the operand instance table. */ |