diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/.Sanitize | 36 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rwxr-xr-x | opcodes/configure | 40 | ||||
| -rw-r--r-- | opcodes/configure.in | 13 | ||||
| -rw-r--r-- | opcodes/d10v-dis.c | 238 | ||||
| -rw-r--r-- | opcodes/d10v-opc.c | 241 | ||||
| -rw-r--r-- | opcodes/disassemble.c | 10 |
7 files changed, 568 insertions, 20 deletions
diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize index e769094..a48dfd8 100644 --- a/opcodes/.Sanitize +++ b/opcodes/.Sanitize @@ -23,6 +23,14 @@ else lose_these_too="${arc_files} ${lose_these_too}" fi +d10v_files="d10v-dis.c d10v-opc.c" + +if ( echo $* | grep keep\-d10v > /dev/null ) ; then + keep_these_too="${d10v_files} ${keep_these_too}" +else + lose_these_too="${d10v_files} ${lose_these_too}" +fi + # All files listed between the "Things-to-keep:" line and the # "Files-to-sed:" line will be kept. All other files will be removed. # Directories listed in this section will have their own Sanitize @@ -105,6 +113,34 @@ else done fi +d10v_files="ChangeLog Makefile.in configure.in configure disassemble.c" +if ( echo $* | grep keep\-d10v > /dev/null ) ; then + for i in $d10v_files ; do + if test ! -d $i && (grep sanitize-d10v $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Keeping d10v stuff in $i + fi + fi + done +else + for i in $d10v_files ; do + if test ! -d $i && (grep sanitize-d10v $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Removing traces of \"d10v\" from $i... + fi + cp $i new + sed '/start\-sanitize\-d10v/,/end-\sanitize\-d10v/d' < $i > new + if [ -n "${safe}" -a ! -f .Recover/$i ] ; then + if [ -n "${verbose}" ] ; then + echo Caching $i in .Recover... + fi + mv $i .Recover + fi + mv new $i + fi + done +fi + for i in * ; do if test ! -d $i && (grep sanitize $i > /dev/null) ; then echo '***' Some mentions of Sanitize are still left in $i! 1>&2 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6062551..47dc2ee 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +start-sanitize-d10v + Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * configure: (bfd_d10v_arch) Add new case. + * configure.in: (bfd_d10v_arch) Add new case. + * d10v-dis.c: New file. + * d10v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d10v. +end-sanitize-d10v + Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com> * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating diff --git a/opcodes/configure b/opcodes/configure index a75f888..2f930dc 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -1,8 +1,8 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated automatically using autoconf version 2.8 -# Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc. +# Generated automatically using autoconf version 2.10 +# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc. # # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. @@ -336,7 +336,7 @@ EOF verbose=yes ;; -version | --version | --versio | --versi | --vers) - echo "configure generated by autoconf version 2.8" + echo "configure generated by autoconf version 2.10" exit 0 ;; -with-* | --with-*) @@ -1019,14 +1019,17 @@ if test "${commonbfdlib}" = "true"; then COMMON_SHLIB=yes # Rebuild the shared library if libiberty or libbfd changes. SHLIB_DEP="../libiberty/libiberty.a ../bfd/libbfd.a" + BFD_PICLIST=../bfd/piclist else COMMON_SHLIB= SHLIB_DEP= + BFD_PICLIST= fi + echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then @@ -1042,13 +1045,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 1046 "configure" +#line 1049 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1052: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1055: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -1057,13 +1060,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 1061 "configure" +#line 1064 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1067: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1070: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then : @@ -1091,12 +1094,12 @@ if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 1095 "configure" +#line 1098 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:1100: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:1103: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out` if test -z "$ac_err"; then rm -rf conftest* @@ -1163,12 +1166,15 @@ if test x${all_targets} = xfalse ; then case "$arch" in bfd_a29k_arch) ta="$ta a29k-dis.o" ;; bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.o" ;; + bfd_alpha_arch) ta="$ta alpha-dis.o alpha-opc.o" ;; # start-sanitize-arc bfd_arc_arch) ta="$ta arc-dis.o arc-opc.o" ;; # end-sanitize-arc bfd_arm_arch) ta="$ta arm-dis.o" ;; bfd_convex_arch) ;; +# start-sanitize-d10v + bfd_d10v_arch) ta="$ta d10v-dis.o d10v-opc.o " ;; +# end-sanitize-d10v bfd_h8300_arch) ta="$ta h8300-dis.o" ;; bfd_h8500_arch) ta="$ta h8500-dis.o" ;; bfd_hppa_arch) ta="$ta hppa-dis.o" ;; @@ -1183,9 +1189,6 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.o ppc-opc.o" ;; -# start-sanitize-rce - bfd_rce_arch) ta="$ta rce-dis.o" ;; -# end-sanitize-rce bfd_sh_arch) ta="$ta sh-dis.o" ;; bfd_sparc_arch) ta="$ta sparc-dis.o sparc-opc.o" ;; bfd_tahoe_arch) ;; @@ -1305,7 +1308,7 @@ do echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion" exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;; -version | --version | --versio | --versi | --vers | --ver | --ve | --v) - echo "$CONFIG_STATUS generated by autoconf version 2.8" + echo "$CONFIG_STATUS generated by autoconf version 2.10" exit 0 ;; -help | --help | --hel | --he | --h) echo "\$ac_cs_usage"; exit 0 ;; @@ -1374,6 +1377,7 @@ s%@SHLIB_CC@%$SHLIB_CC%g s%@SHLIB_CFLAGS@%$SHLIB_CFLAGS%g s%@COMMON_SHLIB@%$COMMON_SHLIB%g s%@SHLIB_DEP@%$SHLIB_DEP%g +s%@BFD_PICLIST@%$BFD_PICLIST%g s%@SHLINK@%$SHLINK%g s%@CPP@%$CPP%g s%@archdefs@%$archdefs%g @@ -1482,7 +1486,7 @@ rm -f conftest.vals cat > conftest.hdr <<\EOF s/[\\&%]/\\&/g s%[\\$`]%\\&%g -s%#define \([A-Za-z_][A-Za-z0-9_]*\) \(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp +s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp s%ac_d%ac_u%gp s%ac_u%ac_e%gp EOF @@ -1530,6 +1534,12 @@ cat >> $CONFIG_STATUS <<\EOF echo "$ac_file is unchanged" rm -f conftest.h else + # Remove last slash and all that follows it. Not all systems have dirname. + ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'` + if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then + # The file is in a subdirectory. + test ! -d "$ac_dir" && mkdir "$ac_dir" + fi rm -f $ac_file mv conftest.h $ac_file fi diff --git a/opcodes/configure.in b/opcodes/configure.in index 9aed7fe..e8690d1 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -1,4 +1,4 @@ -AC_PREREQ(2.0) +AC_PREREQ(2.5) AC_INIT(z8k-dis.c) # configure.in script for the opcodes library. # Copyright (C) 1995, 1996 Free Software Foundation, Inc. @@ -101,12 +101,15 @@ if test "${commonbfdlib}" = "true"; then COMMON_SHLIB=yes # Rebuild the shared library if libiberty or libbfd changes. SHLIB_DEP="../libiberty/libiberty.a ../bfd/libbfd.a" + BFD_PICLIST=../bfd/piclist else COMMON_SHLIB= SHLIB_DEP= + BFD_PICLIST= fi AC_SUBST(COMMON_SHLIB) AC_SUBST(SHLIB_DEP) +AC_SUBST(BFD_PICLIST) AC_SUBST(SHLINK) AC_CHECK_HEADERS(string.h strings.h) @@ -153,12 +156,15 @@ if test x${all_targets} = xfalse ; then case "$arch" in bfd_a29k_arch) ta="$ta a29k-dis.o" ;; bfd_alliant_arch) ;; - bfd_alpha_arch) ta="$ta alpha-dis.o" ;; + bfd_alpha_arch) ta="$ta alpha-dis.o alpha-opc.o" ;; # start-sanitize-arc bfd_arc_arch) ta="$ta arc-dis.o arc-opc.o" ;; # end-sanitize-arc bfd_arm_arch) ta="$ta arm-dis.o" ;; bfd_convex_arch) ;; +# start-sanitize-d10v + bfd_d10v_arch) ta="$ta d10v-dis.o d10v-opc.o" ;; +# end-sanitize-d10v bfd_h8300_arch) ta="$ta h8300-dis.o" ;; bfd_h8500_arch) ta="$ta h8500-dis.o" ;; bfd_hppa_arch) ta="$ta hppa-dis.o" ;; @@ -173,9 +179,6 @@ if test x${all_targets} = xfalse ; then bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.o ppc-opc.o" ;; -# start-sanitize-rce - bfd_rce_arch) ta="$ta rce-dis.o" ;; -# end-sanitize-rce bfd_sh_arch) ta="$ta sh-dis.o" ;; bfd_sparc_arch) ta="$ta sparc-dis.o sparc-opc.o" ;; bfd_tahoe_arch) ;; diff --git a/opcodes/d10v-dis.c b/opcodes/d10v-dis.c new file mode 100644 index 0000000..a4d5438 --- /dev/null +++ b/opcodes/d10v-dis.c @@ -0,0 +1,238 @@ +/* Disassemble D10V instructions. + Copyright (C) 1996 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include <stdio.h> + +#include "opcode/d10v.h" +#include "dis-asm.h" + +static void dis_2_short PARAMS ((unsigned long insn, char *str, int order)); +static void dis_long PARAMS ((unsigned long insn, char *str)); + +int +print_insn_d10v (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status; + bfd_byte buffer[4]; + unsigned long insn; + char str[64]; + + strcpy (str, "unknown"); + + status = (*info->read_memory_func) (memaddr, buffer, 4, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + insn = bfd_getb32 (buffer); + + status = insn & FM11; + switch (status) { + case 0: + dis_2_short (insn, str, 2); + break; + case FM01: + dis_2_short (insn, str, 0); + break; + case FM10: + dis_2_short (insn, str, 1); + break; + case FM11: + dis_long (insn, str); + break; + } + (*info->fprintf_func) (info->stream, "\t%s", str, insn); + return 4; +} + +static void +print_operand (buf, oper, insn, op) + char *buf; + struct d10v_operand *oper; + unsigned long insn; + struct d10v_opcode *op; +{ + int num, shift; + + if (oper->flags == OPERAND_ATMINUS) + { + strcpy (buf,"@-"); + return; + } + if (oper->flags == OPERAND_MINUS) + { + strcpy (buf,"-"); + return; + } + if (oper->flags == OPERAND_PLUS) + { + strcpy (buf,"+"); + return; + } + if (oper->flags == OPERAND_ATSIGN) + { + strcpy (buf,"@"); + return; + } + if (oper->flags == OPERAND_ATPAR) + { + strcpy (buf,"@("); + return; + } + + shift = oper->shift; + + /* the LONG_L format shifts registers over by 15 */ + if (op->format == LONG_L && (oper->flags & OPERAND_REG)) + shift += 15; + + num = (insn >> shift) & (0x7FFFFFFF >> (31 - oper->bits)); + + if (oper->flags & OPERAND_ACC) + *buf++ = 'a'; + else if (oper->flags & OPERAND_CONTROL) + { + *buf++ ='c'; + *buf++ ='r'; + } + else if(oper->flags & OPERAND_REG) + *buf++ = 'r'; + + if (oper->flags & OPERAND_REG) + sprintf (buf, "%d", num); + else + sprintf (buf, "0x%x", num); +} + + +static void +dis_long (insn, str) + unsigned long insn; + char *str; +{ + int i; + char buf[32]; + struct d10v_opcode *op = (struct d10v_opcode *)d10v_opcodes; + struct d10v_operand *oper; + int need_paren = 0; + + while (op->name) + { + if ((op->format & LONG_OPCODE) && ((op->mask & insn) == op->opcode)) + { + strcpy (str, op->name); + strcat (str, "\t"); + for ( i=0; op->operands[i]; i++) + { + oper = (struct d10v_operand *)&d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (buf, oper, insn, op); + strcat (str, buf); + if (op->operands[i+1] && oper->bits && + d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS && + d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS) + strcat (str,", "); + } + break; + } + op++; + } + if (need_paren) + strcat (str, ")"); +} + +static void +dis_2_short (insn, str, order) + unsigned long insn; + char *str; + int order; +{ + int i,j; + char astr[2][32]; + unsigned int ins[2]; + struct d10v_opcode *op; + char buf[32]; + int match, num_match=0; + struct d10v_operand *oper; + int need_paren = 0; + + ins[0] = (insn & 0x3FFFFFFF) >> 15; + ins[1] = insn & 0x00007FFF; + + *str = 0; + + for(j=0;j<2;j++) + { + op = (struct d10v_opcode *)d10v_opcodes; + match=0; + while (op->name) + { + if ((op->format & SHORT_OPCODE) && ((op->mask & ins[j]) == op->opcode)) + { + strcat (str, op->name); + strcat (str, "\t"); + for (i=0; op->operands[i]; i++) + { + oper = (struct d10v_operand *)&d10v_operands[op->operands[i]]; + if (oper->flags == OPERAND_ATPAR) + need_paren = 1; + print_operand (buf, oper, ins[j], op); + strcat (str, buf); + if (op->operands[i+1] && oper->bits && + d10v_operands[op->operands[i+1]].flags != OPERAND_PLUS && + d10v_operands[op->operands[i+1]].flags != OPERAND_MINUS) + strcat( str,", "); + } + match = 1; + num_match++; + break; + } + op++; + } + if (!match) + strcat (str, "unknown"); + + switch (order) + { + case 0: + strcat ( str, "\t->\t"); + order = -1; + break; + case 1: + strcat (str, "\t<-\t"); + order = -1; + break; + case 2: + strcat (str, "\t||\t"); + order = -1; + break; + default: + break; + } + } + + if (num_match == 0) + sprintf (str, ".long\t0x%08x", insn); + + if (need_paren) + strcat (str, ")"); +} diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c new file mode 100644 index 0000000..86abde8 --- /dev/null +++ b/opcodes/d10v-opc.c @@ -0,0 +1,241 @@ +/* d10v-opc.c -- D10V opcode list + Copyright 1996 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include <stdio.h> +#include "ansidecl.h" +#include "opcode/d10v.h" + +const struct d10v_operand d10v_operands[] = +{ +#define UNUSED (0) + { 0, 0, 0 }, +#define RSRC (UNUSED + 1) + { 4, 1, OPERAND_REG }, +#define RDST (RSRC + 1) + { 4, 5, OPERAND_DEST|OPERAND_REG }, +#define ASRC (RDST + 1) + { 1, 4, OPERAND_ACC|OPERAND_REG }, +#define ADST (ASRC + 1) + { 1, 8, OPERAND_DEST|OPERAND_ACC|OPERAND_REG }, +#define RSRCE (ADST + 1) + { 4, 1, OPERAND_EVEN|OPERAND_REG }, +#define RDSTE (RSRCE + 1) + { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_REG }, +#define NUM16 (RDSTE + 1) + { 16, 0, OPERAND_NUM }, +#define NUM3 (NUM16 + 1) + { 3, 1, OPERAND_NUM }, +#define NUM4 (NUM3 + 1) + { 4, 1, OPERAND_NUM }, +#define NUM8 (NUM4 + 1) /* only used in REPI */ + { 8, 16, OPERAND_NUM }, +#define ANUM16 (NUM8 + 1) + { 16, 0, OPERAND_ADDR }, +#define ANUM8 (ANUM16 + 1) + { 8, 0, OPERAND_ADDR }, +#define ASRC2 (ANUM8 + 1) + { 1, 8, OPERAND_ACC|OPERAND_REG }, +#define RSRC2 (ASRC2 + 1) + { 4, 5, OPERAND_REG }, +#define RSRC2E (RSRC2 + 1) + { 4, 5, OPERAND_REG|OPERAND_EVEN }, +#define ASRC0 (RSRC2E + 1) + { 1, 0, OPERAND_ACC|OPERAND_REG }, +#define ADST0 (ASRC0 + 1) + { 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, +#define FSRC (ADST0 + 1) + { 2, 1, OPERAND_REG | OPERAND_FLAG }, +#define FDST (FSRC + 1) + { 1, 5, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST}, +#define ATSIGN (FDST + 1) + { 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* postincrement */ + { 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* postdecrement */ + { 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* predecrement */ + { 0, 0, OPERAND_ATMINUS}, +#define CSRC (ATMINUS + 1) /* control register */ + { 4, 1, OPERAND_REG|OPERAND_CONTROL}, +#define CDST (CSRC + 1) /* control register */ + { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, +}; + +const struct d10v_opcode d10v_opcodes[] = { + { "abs", SHORT_2, 1, EITHER, PAR, 0x4607, 0x7e1f, { RDST } }, + { "abs", SHORT_2, 1, IU, PAR, 0x5607, 0x7eff, { ADST } }, + { "add", SHORT_2, 1, EITHER, PAR, 0x0200, 0x7e01, { RDST, RSRC } }, + { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } }, + { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } }, + { "add2w", SHORT_2, 2, IU, PAR, 0x1200, 0x7e23, { RDSTE, RSRCE } }, + { "add3", LONG_L, 1, MU, SEQ, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "addi", SHORT_2, 1, EITHER, PAR, 0x201, 0x7e01, { RDST, NUM4 } }, + { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } }, + { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, NUM4 } }, + { "bl", LONG_B, 3, MU, BRANCH_LINK, 0x24800000, 0x3fff8000, { ANUM16 } }, + { "bl.s", SHORT_B, 3, MU, BRANCH_LINK, 0x4900, 0x7f00, { ANUM8 } }, + { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, NUM4 } }, + { "bra", LONG_B, 3, MU, SEQ, 0x24000000, 0x3fff0000, { ANUM16 } }, + { "bra.s", SHORT_B, 3, MU, PAR, 0x4800, 0x7f00, { ANUM8 } }, + { "brf0f", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } }, + { "brf0f.s", SHORT_B, 3, MU, PAR, 0x4a00, 0x7f00, { ANUM8 } }, + { "brf0t", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, + { "brf0t.s", SHORT_B, 3, MU, PAR, 0x4b00, 0x7f00, { ANUM8 } }, + { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, NUM4 } }, + { "btsti", SHORT_2, 1, IU, PAR, 0xe01, 0x7e01, { RDST, NUM4 } }, + { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, + { "cmp", SHORT_2, 1, EITHER, PAR, 0x600, 0x7e01, { RSRC2, RSRC } }, + { "cmp", SHORT_2, 1, IU, PAR, 0x1603, 0x7eef, { ASRC2, ASRC } }, + { "cmpeq", SHORT_2, 1, EITHER, PAR, 0x400, 0x7e01, { RSRC2, RSRC } }, + { "cmpeq", SHORT_2, 1, IU, PAR, 0x1403, 0x7eef, { ASRC2, ASRC } }, + { "cmpeqi", SHORT_2, 1, EITHER, PAR, 0x401, 0x7e01, { RSRC2, NUM4 } }, + { "cmpeqi", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpi", SHORT_2, 1, EITHER, PAR, 0x601, 0x7e01, { RSRC2, NUM4 } }, + { "cmpi", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cmpu", SHORT_2, 1, EITHER, PAR, 0x4600, 0x7e01, { RSRC2, RSRC } }, + { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FSRC } }, + { "dbt", SHORT_2, 5, MU, PAR, 0x5f20, 0x7fff, { 0 } }, + { "exef0f", SHORT_2, 1, EITHER, PAR, 0x4e04, 0x7fff, { 0 } }, + { "exef0t", SHORT_2, 1, EITHER, PAR, 0x4e24, 0x7fff, { 0 } }, + { "exef1f", SHORT_2, 1, EITHER, PAR, 0x4e40, 0x7fff, { 0 } }, + { "exef1t", SHORT_2, 1, EITHER, PAR, 0x4e42, 0x7fff, { 0 } }, + { "exefaf", SHORT_2, 1, EITHER, PAR, 0x4e00, 0x7fff, { 0 } }, + { "exefat", SHORT_2, 1, EITHER, PAR, 0x4e02, 0x7fff, { 0 } }, + { "exetaf", SHORT_2, 1, EITHER, PAR, 0x4e20, 0x7fff, { 0 } }, + { "exetat", SHORT_2, 1, EITHER, PAR, 0x4e22, 0x7fff, { 0 } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } }, + { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } }, + { "jl", SHORT_2, 3, MU, BRANCH_LINK, 0x4d00, 0x7fe1, { RSRC } }, + { "jmp", SHORT_2, 3, MU, PAR, 0x4c00, 0x7fe1, { RSRC } }, + { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ld", SHORT_2, 1, MU, PAR, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } }, + { "ld", SHORT_2, 1, MU, PAR, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } }, + { "ld", SHORT_2, 1, MU, PAR, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } }, + { "ld2w", SHORT_2, 1, MU, PAR, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } }, + { "ld2w", SHORT_2, 1, MU, PAR, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } }, + { "ld2w", SHORT_2, 1, MU, PAR, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } }, + { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldb", SHORT_2, 1, MU, PAR, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "ldi", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } }, + { "ldi", SHORT_2, 1, EITHER, PAR,0x4001, 0x7e01 , { RDST, NUM4 } }, + { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } }, + { "ldub", SHORT_2, 1, MU, PAR, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } }, + { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "max", SHORT_2, 1, IU, PAR, 0x2600, 0x7e01, { RDST, RSRC } }, + { "max", SHORT_2, 1, IU, PAR, 0x3600, 0x7ee3, { ADST, RSRCE } }, + { "max", SHORT_2, 1, IU, PAR, 0x3602, 0x7eef, { ADST, ASRC } }, + { "min", SHORT_2, 1, IU, PAR, 0x2601, 0x7e01 , { RDST, RSRC } }, + { "min", SHORT_2, 1, IU, PAR, 0x3601, 0x7ee3 , { ADST, RSRCE } }, + { "min", SHORT_2, 1, IU, PAR, 0x3603, 0x7eef, { ADST, ASRC } }, + { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } }, + { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } }, + { "mv", SHORT_2, 1, IU, PAR, 0x4000, 0x7e01, { RDST, RSRC } }, + { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } }, + { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } }, + { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } }, + { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } }, + { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } }, + { "mvf0f", SHORT_2, 1, EITHER, PAR, 0x4400, 0x7e01, { RDST, RSRC } }, + { "mvf0t", SHORT_2, 1, EITHER, PAR, 0x4401, 0x7e01, { RDST, RSRC } }, + { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } }, + { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } }, + { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } }, + { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } }, + { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } }, + { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } }, + { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } }, + { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } }, + { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } }, + { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } }, + { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } }, + { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } }, + { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } }, + { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } }, + { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { "rac", SHORT_2, 1, IU, PAR, 0x5201, 0x7e21, { RDSTE, ASRC, NUM3 } }, + { "rachi", SHORT_2, 1, IU, PAR, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } }, + { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } }, + { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { NUM8, ANUM16 } }, + { "rtd", SHORT_2, 3, MU, PAR, 0x5f60, 0x7fff, { 0 } }, + { "rte", SHORT_2, 3, MU, PAR, 0x5f40, 0x7ff, { 0 } }, + { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } }, + { "setf0f", SHORT_2, 1, MU, PAR, 0x4611, 0x7e1f, { RDST } }, + { "setf0t", SHORT_2, 1, MU, PAR, 0x4613, 0x7e1f, { RDST } }, + { "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } }, + { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } }, + { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } }, + { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, NUM4 } }, + { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, NUM4 } }, + { "slx", SHORT_2, 1, IU, PAR, 0x460b, 0x7e1f, { RDST } }, + { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } }, + { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } }, + { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, NUM4 } }, + { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, NUM4 } }, + { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } }, + { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } }, + { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, NUM4 } }, + { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, NUM4 } }, + { "srx", SHORT_2, 1, IU, PAR, 0x4609, 0x7e1f, { RDST } }, + { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "st", SHORT_2, 1, MU, PAR, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + { "st", SHORT_2, 1, MU, PAR, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } }, + { "st", SHORT_2, 1, MU, PAR, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } }, + { "st", SHORT_2, 1, MU, PAR, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } }, + { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } }, + { "st2w", SHORT_2, 1, MU, PAR, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } }, + { "st2w", SHORT_2, 1, MU, PAR, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } }, + { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } }, + { "stb", SHORT_2, 1, MU, PAR, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } }, + /* { "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } }, */ + { "sub", SHORT_2, 1, EITHER, PAR, 0x0, 0x7e01, { RDST, RSRC } }, + { "sub2w", SHORT_2, 1, IU, PAR, 0x1000, 0x7e23, { RDSTE, RSRCE } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } }, + { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } }, + { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, NUM4 } }, + { "trap", SHORT_2, 5, MU, PAR, 0x5f00, 0x7fe1, { NUM4 } }, + { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } }, + { "wait", SHORT_2, 1, MU, PAR, 0x5f80, 0x7fff, { 0 } }, + { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } }, + { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } }, + { 0, 0, 0, 0, 0, 0, 0, { 0 } }, +}; + + diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 26c54ca..b5f646b 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -25,6 +25,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_arc /* end-sanitize-arc */ #define ARCH_arm +/* start-sanitize-d10v */ +#define ARCH_d10v +/* end-sanitize-d10v */ #define ARCH_h8300 #define ARCH_h8500 #define ARCH_hppa @@ -82,6 +85,13 @@ disassembler (abfd) disassemble = print_insn_little_arm; break; #endif +/* start-sanitize-d10v */ +#ifdef ARCH_d10v + case bfd_arch_d10v: + disassemble = print_insn_d10v; + break; +#endif +/* end-sanitize-d10v */ #ifdef ARCH_h8300 case bfd_arch_h8300: if (bfd_get_mach(abfd) == bfd_mach_h8300h) |