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-rw-r--r--opcodes/i386-reg.tbl48
-rw-r--r--opcodes/i386-tbl.h48
2 files changed, 48 insertions, 48 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index d441f36..e314645 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -38,30 +38,30 @@ spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
-r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
-r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
-r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
-r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
-r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
-r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
-r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
-r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
-r16b, Class=Reg|Byte, RegRex2|RegRex64, 0, Dw2Inval, Dw2Inval
-r17b, Class=Reg|Byte, RegRex2|RegRex64, 1, Dw2Inval, Dw2Inval
-r18b, Class=Reg|Byte, RegRex2|RegRex64, 2, Dw2Inval, Dw2Inval
-r19b, Class=Reg|Byte, RegRex2|RegRex64, 3, Dw2Inval, Dw2Inval
-r20b, Class=Reg|Byte, RegRex2|RegRex64, 4, Dw2Inval, Dw2Inval
-r21b, Class=Reg|Byte, RegRex2|RegRex64, 5, Dw2Inval, Dw2Inval
-r22b, Class=Reg|Byte, RegRex2|RegRex64, 6, Dw2Inval, Dw2Inval
-r23b, Class=Reg|Byte, RegRex2|RegRex64, 7, Dw2Inval, Dw2Inval
-r24b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 0, Dw2Inval, Dw2Inval
-r25b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 1, Dw2Inval, Dw2Inval
-r26b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 2, Dw2Inval, Dw2Inval
-r27b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 3, Dw2Inval, Dw2Inval
-r28b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 4, Dw2Inval, Dw2Inval
-r29b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 5, Dw2Inval, Dw2Inval
-r30b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 6, Dw2Inval, Dw2Inval
-r31b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 7, Dw2Inval, Dw2Inval
+r8b, Class=Reg|Byte, RegRex, 0, Dw2Inval, Dw2Inval
+r9b, Class=Reg|Byte, RegRex, 1, Dw2Inval, Dw2Inval
+r10b, Class=Reg|Byte, RegRex, 2, Dw2Inval, Dw2Inval
+r11b, Class=Reg|Byte, RegRex, 3, Dw2Inval, Dw2Inval
+r12b, Class=Reg|Byte, RegRex, 4, Dw2Inval, Dw2Inval
+r13b, Class=Reg|Byte, RegRex, 5, Dw2Inval, Dw2Inval
+r14b, Class=Reg|Byte, RegRex, 6, Dw2Inval, Dw2Inval
+r15b, Class=Reg|Byte, RegRex, 7, Dw2Inval, Dw2Inval
+r16b, Class=Reg|Byte, RegRex2, 0, Dw2Inval, Dw2Inval
+r17b, Class=Reg|Byte, RegRex2, 1, Dw2Inval, Dw2Inval
+r18b, Class=Reg|Byte, RegRex2, 2, Dw2Inval, Dw2Inval
+r19b, Class=Reg|Byte, RegRex2, 3, Dw2Inval, Dw2Inval
+r20b, Class=Reg|Byte, RegRex2, 4, Dw2Inval, Dw2Inval
+r21b, Class=Reg|Byte, RegRex2, 5, Dw2Inval, Dw2Inval
+r22b, Class=Reg|Byte, RegRex2, 6, Dw2Inval, Dw2Inval
+r23b, Class=Reg|Byte, RegRex2, 7, Dw2Inval, Dw2Inval
+r24b, Class=Reg|Byte, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval
+r25b, Class=Reg|Byte, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval
+r26b, Class=Reg|Byte, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval
+r27b, Class=Reg|Byte, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval
+r28b, Class=Reg|Byte, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval
+r29b, Class=Reg|Byte, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval
+r30b, Class=Reg|Byte, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval
+r31b, Class=Reg|Byte, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval
// 16 bit regs
ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e42254b..88354c4 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -48674,99 +48674,99 @@ static const reg_entry i386_regtab[] =
{ "r8b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 0, { Dw2Inval, Dw2Inval } },
+ RegRex, 0, { Dw2Inval, Dw2Inval } },
{ "r9b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 1, { Dw2Inval, Dw2Inval } },
+ RegRex, 1, { Dw2Inval, Dw2Inval } },
{ "r10b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 2, { Dw2Inval, Dw2Inval } },
+ RegRex, 2, { Dw2Inval, Dw2Inval } },
{ "r11b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 3, { Dw2Inval, Dw2Inval } },
+ RegRex, 3, { Dw2Inval, Dw2Inval } },
{ "r12b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 4, { Dw2Inval, Dw2Inval } },
+ RegRex, 4, { Dw2Inval, Dw2Inval } },
{ "r13b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 5, { Dw2Inval, Dw2Inval } },
+ RegRex, 5, { Dw2Inval, Dw2Inval } },
{ "r14b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 6, { Dw2Inval, Dw2Inval } },
+ RegRex, 6, { Dw2Inval, Dw2Inval } },
{ "r15b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex|RegRex64, 7, { Dw2Inval, Dw2Inval } },
+ RegRex, 7, { Dw2Inval, Dw2Inval } },
{ "r16b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 0, { Dw2Inval, Dw2Inval } },
+ RegRex2, 0, { Dw2Inval, Dw2Inval } },
{ "r17b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 1, { Dw2Inval, Dw2Inval } },
+ RegRex2, 1, { Dw2Inval, Dw2Inval } },
{ "r18b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 2, { Dw2Inval, Dw2Inval } },
+ RegRex2, 2, { Dw2Inval, Dw2Inval } },
{ "r19b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 3, { Dw2Inval, Dw2Inval } },
+ RegRex2, 3, { Dw2Inval, Dw2Inval } },
{ "r20b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 4, { Dw2Inval, Dw2Inval } },
+ RegRex2, 4, { Dw2Inval, Dw2Inval } },
{ "r21b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 5, { Dw2Inval, Dw2Inval } },
+ RegRex2, 5, { Dw2Inval, Dw2Inval } },
{ "r22b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 6, { Dw2Inval, Dw2Inval } },
+ RegRex2, 6, { Dw2Inval, Dw2Inval } },
{ "r23b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64, 7, { Dw2Inval, Dw2Inval } },
+ RegRex2, 7, { Dw2Inval, Dw2Inval } },
{ "r24b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 0, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 0, { Dw2Inval, Dw2Inval } },
{ "r25b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 1, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 1, { Dw2Inval, Dw2Inval } },
{ "r26b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 2, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 2, { Dw2Inval, Dw2Inval } },
{ "r27b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 3, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 3, { Dw2Inval, Dw2Inval } },
{ "r28b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 4, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 4, { Dw2Inval, Dw2Inval } },
{ "r29b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 5, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 5, { Dw2Inval, Dw2Inval } },
{ "r30b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 6, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 6, { Dw2Inval, Dw2Inval } },
{ "r31b",
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
- RegRex2|RegRex64|RegRex, 7, { Dw2Inval, Dw2Inval } },
+ RegRex2|RegRex, 7, { Dw2Inval, Dw2Inval } },
{ "ax",
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
generated by cgit v1.1 at 2025-01-10 02:50:37 +0000