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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arm-dis.c8
2 files changed, 13 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d405787..e8714ed 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-06-08 Alex Coplan <alex.coplan@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add dfb.
+ (thumb32_opcodes): Add dfb.
+
2020-06-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.h (reg_entry): Const-qualify reg_name field.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 79a3dc6..de62328 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3685,6 +3685,10 @@ static const struct opcode32 arm_opcodes[] =
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
0xe320f010, 0xffffffff, "esb"},
+ /* V8-R instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+ 0xf57ff04c, 0xffffffff, "dfb"},
+
/* V8 instructions. */
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0x0320f005, 0x0fffffff, "sevl"},
@@ -4735,6 +4739,10 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
+ /* V8-R instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R),
+ 0xf3bf8f4c, 0xffffffff, "dfb%c"},
+
/* CRC32 instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},