diff options
Diffstat (limited to 'opcodes')
37 files changed, 7924 insertions, 923 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 2c5816b..8bbcdff 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,258 @@ +2002-08-16 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex + values as those. + * z8kgen.c (opt): Fix definition of "in rd,imm16" opcode. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-08-19 Elena Zannoni <ezannoni@redhat.com> + + From matthew green <mrg@redhat.com> + + * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and + `-mefs'. Turn off AltiVec for E500 and efs. + (print_insn_powerpc): Don't print an AltiVec instruction if the + dialect is not efs. + + * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, + insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions + for extracting pmrn/evld/evstd/etc operands. + (CRB, CRFD, CRFS, DC, RD): New instruction fields. + (CT): Make this equal to RD + 1. + (PMRN): New operand. + (RA): Update. + (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. + (WS): Update. + (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. + (ISEL, ISEL_MASK): New instruction form and mask for ISEL. + (XISEL, XISEL_MASK): New instruction form and mask for ISEL. + (CTX, CTX_MASK): New instruction form and mask for context cache + instructions. + (UCTX, UCTX_MASK): New instruction form and mask for user context + cache instructions. + (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. + (CLASSIC): New define. + (PPCESPE): New define. + (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New + defines for integer select, cache control, branch + locking, power management, cache locking and machine check + APU instructions, respectively. + (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, + efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, + efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, + efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, + evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, + evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, + evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, + evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, + evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, + evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, + evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, + evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, + evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, + evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, + evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, + evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, + evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, + evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, + evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, + evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, + evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, + evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, + evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, + evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, + evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, + evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, + evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, + evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, + evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, + evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, + evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, + evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, + evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, + evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, + evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, + evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, + evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, + evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, + evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, + evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, + evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, + evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, + evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, + evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, + evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, + evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex + instructions. + (rfmci): New machine check APU instruction. + (isel): New integer select APU instructino. + (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, + dcbtstlse, dcblc, dcblce): New cache control APU instructions. + (mtspefscr, mfspefscr): New instructions. + (mfpmr, mtpmr): New performance monitor APU instructions. + (savecontext): New context cache APU instructions. + (bblels, bbelr): New branch locking APU instructions. + (bblels, bbelr): New instructions. + (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-opc.c: Update call operand to accept the page definition. + Identify instructions that are branches and calls to generate a + RL_JUMP relocation. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c (print_insn): Take into account 68HC12 memory + banks and fix disassembling of call instruction. + (print_indexed_operand): New param to tell whether + it was an indirect addressing operand (for disassembling call). + +2002-08-09 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2002-08-08 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as + aliases to "daddiu" and "addiu". + +2002-07-30 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2002-07-25 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + * po/tr.po: Updated Turkish translation. + * po/fr.po: Updated French translation. + +2002-07-24 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + +2002-07-23 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-07-23 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + * po/pr_BR.po: New Brazilian Portuguese translation. + * po/id.po: Updated Indonesian translation. + * configure.in (LINGUAS): Add pr_BR. + * configure: Regenerate. + +2002-07-18 Denis Chertykov <denisc@overta.ru> + Frank Ch. Eigler <fche@redhat.com> + Alan Lehotsky <alehotsky@cygnus.com> + matthew green <mrg@redhat.com> + + * configure.in: Add support for ip2k. + * configure: Regenerate. + * Makefile.am: Add support for ip2k. + * Makefile.in: Regenerate. + * disassemble.c: Add support for ip2k. + * ip2k-asm.c: New generated file. + * ip2k-desc.c: New generated file. + * ip2k-desc.h: New generated file. + * ip2k-dis.c: New generated file. + * ip2k-ibld.c: New generated file. + * ip2k-opc.c: New generated file. + * ip2k-opc.h: New generated file. + +2002-07-17 David Mosberger <davidm@hpl.hp.com> + + * ia64-opc-b.c (bWhc): New macro. + (mWhc): Ditto. + (OpPaWhcD): Ditto. + (ia64_opcodes_b): Correct patterns for indirect call + instructions to use 3-bit "wh" field. + * ia64-asmtab.c: Regnerate. + +2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. + * mips-opc.c (I16): New define. + (mips_builtin_opcodes): Make jalx an I16 insn. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + * po/POTFILES.in: Add frv-*.[ch]. + * disassemble.c (ARCH_frv): New macro. + (disassembler): Handle bfd_arch_frv. + * configure.in: Support frv_bfd_arch. + * Makefile.am (HFILES): Add frv-*.h. + (CFILES): Add frv-*.c + (ALL_MACHINES): Add frv-*.lo. + (CLEANFILES): Add stamp-frv. + (FRV_DEPS): New variable. + (stamp-frv): New target. + (frv-asm.lo): New target. + (frv-desc.lo): New target. + (frv-dis.lo): New target. + (frv-ibld.lo): New target. + (frv-opc.lo): New target. + (frv-*.[ch]): New files. + +2002-06-18 Ben Elliston <bje@redhat.com> + + * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. + * Makefile.in: Regenerate. + +2002-06-08 Alan Modra <amodra@bigpond.net.au> + + * a29k-dis.c: Replace CONST with const. + * h8300-dis.c: Likewise. + * m68k-dis.c: Likewise. + * or32-dis.c: Likewise. + * sparc-dis.c: Likewise. + +2002-06-04 Jason Thorpe <thorpej@wasabisystems.com> + + * configure.in: Add "sh5*-*" to list of targets which include + sh64 support. + * configure: Regenerate. + +2002-05-31 Chris G. Demetriou <cgd@broadcom.com> + + * mips-opc.c: Clean up a few whitespace issues, and sort a + few entries understanding that 'x' follows 'w' in the alphabet. + +2002-05-31 Chris G. Demetriou <cgd@broadcom.com> + Ed Satterthwaite <ehs@broadcom.com> + + * mips-opc.c: Add support for SB-1 MDMX subset and extensions. + +2002-05-31 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-05-30 Chris G. Demetriou <cgd@broadcom.com> + Ed Satterthwaite <ehs@broadcom.com> + + * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', + and 'Z' formats, for MDMX. + (mips_isa_type): Add MDMX instructions to the ISA + bit mask for bfd_mach_mipsisa64. + * mips-opc.c: Add support for MDMX instructions. + (MX): New definition. + + * mips-dis.c: Update copyright years to include 2002. + +2002-05-30 Diego Novillo <dnovillo@redhat.com> + + * d10v-opc.c (d10v_opcodes): `btsti' does not modify its + arguments. + 2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> * configure.in: Add DLX configuraton support. @@ -14,7 +269,7 @@ * arc-dis.c: Use #include "" instead of <> for local header files. * m68k-dis.c: Likewise. -Wed May 22 20:11:51 2002 J"orn Rennecke <joern.rennecke@superh.com> +2002-05-22 J"orn Rennecke <joern.rennecke@superh.com> * Makefile.am (sh-dis.lo): Compile with @archdefs@. * Makefile.in: regenerate. @@ -26,7 +281,7 @@ Wed May 22 20:11:51 2002 J"orn Rennecke <joern.rennecke@superh.com> * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. -Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com> +2002-05-17 J"orn Rennecke <joern.rennecke@superh.com> * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. * sh-dis.c (LITTLE_BIT): Delete. @@ -152,7 +407,7 @@ Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com> * ppc-opc.c: Add optional field to mtmsrd. (MTMSRD_L, XRLARB_MASK): Define. -Mon Mar 18 21:10:43 CET 2002 Jan Hubicka <jh@suse.cz> +2002-03-18 Jan Hubicka <jh@suse.cz> * i386-dis.c (prefix_name): Fix handling of 32bit address prefix in 64bit mode. @@ -262,7 +517,7 @@ Mon Mar 18 21:10:43 CET 2002 Jan Hubicka <jh@suse.cz> 2002-02-20 Tom Rix <trix@redhat.com> - * ppc-opc.c (powerpc_operands): Add WS feild. Use for tlbre, tlbwe. + * ppc-opc.c (powerpc_operands): Add WS field. Use for tlbre, tlbwe. 2002-02-19 Martin Schwidefsky <schwidefsky@de.ibm.com> @@ -1642,7 +1897,7 @@ Mon Mar 18 21:10:43 CET 2002 Jan Hubicka <jh@suse.cz> * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. * ia64-asmtab.c: Regenerate. -Mon Feb 12 17:41:26 CET 2001 Jan Hubicka <jh@suse.cz> +2001-02-12 Jan Hubicka <jh@suse.cz> * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison instructions. @@ -1681,7 +1936,7 @@ Mon Feb 12 17:41:26 CET 2001 Jan Hubicka <jh@suse.cz> * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. * m32r-desc.h: Regenerate. -Thu Feb 1 16:29:06 MET 2001 Jan Hubicka <jh@suse.cz> +2001-02-01 Jan Hubicka <jh@suse.cz> * i386-dis.c (dis386_att, grps): Use 'T' for push/pop (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax @@ -1694,7 +1949,7 @@ Thu Feb 1 16:29:06 MET 2001 Jan Hubicka <jh@suse.cz> * disassemble.c: Remove spurious white space. -Sat Jan 13 01:48:24 MET 2001 Jan Hubicka <jh@suse.cz> +2001-01-13 Jan Hubicka <jh@suse.cz> * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret templates. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 0996b2e..d2f043c 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -26,9 +26,11 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -66,6 +68,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -84,6 +91,11 @@ CFILES = \ ia64-opc.c \ ia64-gen.c \ ia64-asmtab.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -168,6 +180,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -178,6 +195,11 @@ ALL_MACHINES = \ i960-dis.lo \ ia64-dis.lo \ ia64-opc.lo \ + ip2k-asm.lo \ + ip2k-desc.lo \ + ip2k-dis.lo \ + ip2k-ibld.lo \ + ip2k-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -301,7 +323,7 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -311,7 +333,7 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ @@ -319,13 +341,17 @@ CGENDEPS = ../cgen/stamp-cgen \ cgen-asm.in cgen-dis.in cgen-ibld.in if CGEN_MAINT +IP2K_DEPS = stamp-ip2k M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 +FRV_DEPS = stamp-frv OPENRISC_DEPS = stamp-openrisc XSTORMY16_DEPS = stamp-xstormy16 else +IP2K_DEPS = M32R_DEPS = FR30_DEPS = +FRV_DEPS = OPENRISC_DEPS = XSTORMY16_DEPS = endif @@ -338,6 +364,11 @@ run-cgen: .PHONY: run-cgen # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) + @true +stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= extrafiles= + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc @@ -348,6 +379,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30- stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -474,8 +510,7 @@ d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/dlx.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -496,6 +531,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/libiberty.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/safe-ctype.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h $(INCDIR)/libiberty.h $(INCDIR)/elf/frv.h \ + $(INCDIR)/elf/reloc-macros.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h @@ -538,6 +590,22 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c +ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/libiberty.h +ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h +ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h +ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 3602cbd..c2a5c5a 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -136,9 +136,11 @@ LIBIBERTY = ../libiberty/libiberty.a HFILES = \ arm-opc.h \ fr30-desc.h fr30-opc.h \ + frv-desc.h frv-opc.h \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -177,6 +179,11 @@ CFILES = \ fr30-dis.c \ fr30-ibld.c \ fr30-opc.c \ + frv-asm.c \ + frv-desc.c \ + frv-dis.c \ + frv-ibld.c \ + frv-opc.c \ h8300-dis.c \ h8500-dis.c \ hppa-dis.c \ @@ -195,6 +202,11 @@ CFILES = \ ia64-opc.c \ ia64-gen.c \ ia64-asmtab.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -280,6 +292,11 @@ ALL_MACHINES = \ fr30-dis.lo \ fr30-ibld.lo \ fr30-opc.lo \ + frv-asm.lo \ + frv-desc.lo \ + frv-dis.lo \ + frv-ibld.lo \ + frv-opc.lo \ h8300-dis.lo \ h8500-dis.lo \ hppa-dis.lo \ @@ -290,6 +307,11 @@ ALL_MACHINES = \ i960-dis.lo \ ia64-dis.lo \ ia64-opc.lo \ + ip2k-asm.lo \ + ip2k-desc.lo \ + ip2k-dis.lo \ + ip2k-ibld.lo \ + ip2k-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -368,7 +390,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -378,17 +400,21 @@ CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v -CGENDEPS = ../cgen/stamp-cgen \ +CGENDEPS = \ $(CGENDIR)/desc.scm $(CGENDIR)/desc-cpu.scm \ $(CGENDIR)/opcodes.scm $(CGENDIR)/opc-asmdis.scm \ $(CGENDIR)/opc-ibld.scm $(CGENDIR)/opc-itab.scm \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in +@CGEN_MAINT_TRUE@IP2K_DEPS = @CGEN_MAINT_TRUE@stamp-ip2k +@CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@M32R_DEPS = @CGEN_MAINT_TRUE@stamp-m32r @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@FRV_DEPS = @CGEN_MAINT_TRUE@stamp-frv +@CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc @CGEN_MAINT_FALSE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 @@ -421,7 +447,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST) -TAR = gtar +TAR = tar GZIP_ENV = --best SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES) OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS) @@ -834,6 +860,11 @@ run-cgen: .PHONY: run-cgen # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) + @true +stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= extrafiles= + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc @@ -844,6 +875,11 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30- stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) + @true +stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= + $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc @@ -970,8 +1006,7 @@ d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/dlx.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -992,6 +1027,23 @@ fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/libiberty.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/safe-ctype.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h $(INCDIR)/libiberty.h $(INCDIR)/elf/frv.h \ + $(INCDIR)/elf/reloc-macros.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/symcat.h opintl.h @@ -1034,6 +1086,22 @@ ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c +ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/libiberty.h +ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h +ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h +ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ diff --git a/opcodes/a29k-dis.c b/opcodes/a29k-dis.c index 0e937ba..a3090c3 100644 --- a/opcodes/a29k-dis.c +++ b/opcodes/a29k-dis.c @@ -1,5 +1,5 @@ /* Instruction printing code for the AMD 29000 - Copyright 1990, 1993, 1994, 1995, 1998, 2000, 2001 + Copyright 1990, 1993, 1994, 1995, 1998, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Cygnus Support. Written by Jim Kingdon. @@ -153,7 +153,7 @@ print_insn (memaddr, info) find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; - struct a29k_opcode CONST * opcode; + struct a29k_opcode const * opcode; { int status = diff --git a/opcodes/configure b/opcodes/configure index a83d43d..9b6992b 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -2625,7 +2625,7 @@ else fi -ALL_LINGUAS="fr sv tr es da de id" +ALL_LINGUAS="fr sv tr es da de id pt_BR" echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 echo "configure:2631: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. @@ -4614,6 +4614,7 @@ if test x${all_targets} = xfalse ; then bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -4642,7 +4643,7 @@ if test x${all_targets} = xfalse ; then # Include it just for ELF targets, since the SH5 bfd:s are ELF only. for t in $target $canon_targets; do case $t in - all | sh64-* | sh-*-*elf* | shl-*-*elf* | shle-*-*elf* | \ + all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ sh-*-linux* | shl-*-linux*) ta="$ta sh64-dis.lo sh64-opc.lo" archdefs="$archdefs -DINCLUDE_SHMEDIA" @@ -4663,6 +4664,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) { echo "configure: error: *** unknown target architecture $arch" 1>&2; exit 1; } ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 96e5a6b..3ce5e37 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -78,7 +78,7 @@ AC_EXEEXT AC_PROG_CC -ALL_LINGUAS="fr sv tr es da de id" +ALL_LINGUAS="fr sv tr es da de id pt_BR" CY_GNU_GETTEXT . ${srcdir}/../bfd/configure.host @@ -189,6 +189,7 @@ if test x${all_targets} = xfalse ; then bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -217,7 +218,7 @@ if test x${all_targets} = xfalse ; then # Include it just for ELF targets, since the SH5 bfd:s are ELF only. for t in $target $canon_targets; do case $t in - all | sh64-* | sh-*-*elf* | shl-*-*elf* | shle-*-*elf* | \ + all | sh5*-* | sh64*-* | sh-*-*elf* | shl*-*-*elf* | \ sh-*-linux* | shl-*-linux*) ta="$ta sh64-dis.lo sh64-opc.lo" archdefs="$archdefs -DINCLUDE_SHMEDIA" @@ -238,6 +239,7 @@ if test x${all_targets} = xfalse ; then bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; + bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; "") ;; *) AC_MSG_ERROR(*** unknown target architecture $arch) ;; diff --git a/opcodes/d10v-opc.c b/opcodes/d10v-opc.c index b2ce10f..8682177 100644 --- a/opcodes/d10v-opc.c +++ b/opcodes/d10v-opc.c @@ -1,5 +1,5 @@ /* d10v-opc.c -- D10V opcode list - Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Written by Martin Hunt, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -196,7 +196,7 @@ const struct d10v_opcode d10v_opcodes[] = { { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } }, { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } }, { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } }, - { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RDST, UNUM4 } }, + { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } }, { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } }, { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } }, { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } }, diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index bfb22c2..88fa635 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -36,6 +36,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_i386 #define ARCH_i860 #define ARCH_i960 +#define ARCH_ip2k #define ARCH_ia64 #define ARCH_fr30 #define ARCH_m32r @@ -66,6 +67,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_w65 #define ARCH_xstormy16 #define ARCH_z8k +#define ARCH_frv #define INCLUDE_SHMEDIA #endif @@ -178,6 +180,11 @@ disassembler (abfd) disassemble = print_insn_ia64; break; #endif +#ifdef ARCH_ip2k + case bfd_arch_ip2k: + disassemble = print_insn_ip2k; + break; +#endif #ifdef ARCH_fr30 case bfd_arch_fr30: disassemble = print_insn_fr30; @@ -336,6 +343,11 @@ disassembler (abfd) disassemble = print_insn_vax; break; #endif +#ifdef ARCH_frv + case bfd_arch_frv: + disassemble = print_insn_frv; + break; +#endif default: return 0; } diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c index c521c77..d14fda9 100644 --- a/opcodes/h8300-dis.c +++ b/opcodes/h8300-dis.c @@ -1,5 +1,6 @@ /* Disassemble h8300 instructions. - Copyright 1993, 1994, 1996, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright 1993, 1994, 1996, 1998, 2000, 2001, 2002 + Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -69,17 +70,17 @@ bfd_h8_disassemble (addr, info, mode) int mode; { /* Find the first entry in the table for this opcode. */ - static CONST char *regnames[] = + static const char *regnames[] = { "r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h", "r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l" }; - static CONST char *wregnames[] = + static const char *wregnames[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7" }; - static CONST char *lregnames[] = + static const char *lregnames[] = { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7" @@ -92,7 +93,7 @@ bfd_h8_disassemble (addr, info, mode) int plen = 0; static boolean init = 0; struct h8_opcode *q; - char CONST **pregnames = mode != 0 ? lregnames : wregnames; + char const **pregnames = mode != 0 ? lregnames : wregnames; int status; int l; unsigned char data[20]; diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c index 45f60eb..f007f71 100644 --- a/opcodes/ia64-asmtab.c +++ b/opcodes/ia64-asmtab.c @@ -4203,8 +4203,8 @@ main_table[] = { { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 681, }, { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1843, }, { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1844, }, - { 14, 4, 1, 0x0000002000000000ull, 0x000001ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, }, - { 14, 4, 1, 0x0000002000000000ull, 0x000001ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, }, { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 835, }, { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 682, }, { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 683, }, @@ -4585,7 +4585,7 @@ main_table[] = { }; static const char dis_table[] = { -0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70, +0xa0, 0xc2, 0xa0, 0xa0, 0x2c, 0xc0, 0xa0, 0x2a, 0xc0, 0xa0, 0x1a, 0x70, 0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x31, 0x48, 0x24, 0x31, 0x40, 0x90, 0x28, 0x24, 0x31, 0x38, 0x24, 0x31, 0x30, 0x90, 0x50, 0x90, 0x28, 0x24, 0x31, 0x20, 0x24, 0x31, 0x18, 0x90, 0x28, 0x24, 0x31, @@ -4659,557 +4659,558 @@ static const char dis_table[] = { 0x83, 0x37, 0x1b, 0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x2e, 0x60, 0x24, 0x2e, 0x58, 0x90, 0x28, 0x24, 0x2e, 0x50, 0x24, 0x2e, 0x48, 0x90, 0x50, 0x90, 0x28, 0x24, 0x2e, 0x38, 0x24, 0x2e, 0x30, 0x90, -0x28, 0x24, 0x2e, 0x28, 0x24, 0x2e, 0x20, 0xa8, 0x08, 0xe0, 0x0d, 0xe0, -0x96, 0x38, 0x95, 0xe8, 0x9b, 0x48, 0x05, 0xa8, 0x91, 0xa0, 0x90, 0xd0, -0x90, 0x70, 0x90, 0x38, 0xa4, 0x1c, 0x88, 0x33, 0x92, 0xa4, 0x1c, 0x78, -0x33, 0x90, 0x90, 0x38, 0xa4, 0x1c, 0x68, 0x33, 0x8e, 0x80, 0x33, 0x8c, -0x90, 0x60, 0x90, 0x28, 0x24, 0x1c, 0x28, 0xa4, 0x1c, 0x18, 0x33, 0x84, -0x90, 0x38, 0xa4, 0x1c, 0x08, 0x33, 0x82, 0xa4, 0x1c, 0x50, 0x33, 0x8b, -0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x1c, 0x40, 0x33, 0x89, 0xa4, -0x1c, 0x30, 0x33, 0x87, 0x90, 0x38, 0xa4, 0x2d, 0xd8, 0x35, 0xc1, 0xa4, -0x2d, 0x78, 0x35, 0xb5, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2a, 0xb0, 0x35, -0x62, 0xa4, 0x2a, 0x80, 0x35, 0x5c, 0x10, 0x10, 0xa4, 0x1b, 0xf8, 0x33, -0x80, 0x91, 0x50, 0x90, 0x90, 0x90, 0x50, 0x90, 0x28, 0x24, 0x1c, 0xb8, +0x28, 0x24, 0x2e, 0x28, 0x24, 0x2e, 0x20, 0xa8, 0x09, 0x00, 0x0e, 0x20, +0x96, 0x48, 0x95, 0xe8, 0x93, 0x38, 0x91, 0xa0, 0x90, 0xd0, 0x90, 0x70, +0x90, 0x38, 0xa4, 0x1c, 0x88, 0x33, 0x92, 0xa4, 0x1c, 0x78, 0x33, 0x90, +0x90, 0x38, 0xa4, 0x1c, 0x68, 0x33, 0x8e, 0x80, 0x33, 0x8c, 0x90, 0x60, +0x90, 0x28, 0x24, 0x1c, 0x28, 0xa4, 0x1c, 0x18, 0x33, 0x84, 0x90, 0x38, +0xa4, 0x1c, 0x08, 0x33, 0x82, 0xa4, 0x1c, 0x50, 0x33, 0x8b, 0x90, 0xe0, +0x90, 0x70, 0x90, 0x38, 0xa4, 0x1c, 0x40, 0x33, 0x89, 0xa4, 0x1c, 0x30, +0x33, 0x87, 0x90, 0x38, 0xa4, 0x2d, 0xd8, 0x35, 0xc1, 0xa4, 0x2d, 0x78, +0x35, 0xb5, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2a, 0xb0, 0x35, 0x62, 0xa4, +0x2a, 0x80, 0x35, 0x5c, 0x10, 0x10, 0xa4, 0x1b, 0xf8, 0x33, 0x80, 0x99, +0x60, 0x02, 0x70, 0x90, 0x90, 0x90, 0x50, 0x90, 0x28, 0x24, 0x1c, 0xb8, 0x80, 0x33, 0x9e, 0x80, 0xa4, 0x1c, 0xc0, 0x33, 0x9c, 0x90, 0x50, 0x90, 0x28, 0x24, 0x1c, 0xc8, 0x80, 0x33, 0x9f, 0x90, 0x38, 0xa4, 0x1c, 0xd0, 0x33, 0x9d, 0xa4, 0x1c, 0x98, 0x33, 0x94, 0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2d, 0x08, 0x35, 0xa9, 0xa4, 0x2c, 0x68, 0x35, 0x96, 0x90, 0x38, 0xa4, 0x2c, 0x00, 0x35, 0x87, 0xa4, 0x2b, 0x70, 0x35, 0x76, 0x81, -0xa4, 0x1c, 0xa8, 0x33, 0x96, 0xe4, 0xe1, 0xc5, 0x00, 0x37, 0x16, 0xed, -0x21, 0xc3, 0xa0, 0xdf, 0x80, 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0x23, 0x40, +0x85, 0x34, 0x9c, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x2a, +0x80, 0x85, 0x34, 0xbd, 0xcb, 0x61, 0x23, 0x00, 0x85, 0x34, 0x9b, 0x92, +0x38, 0x81, 0x91, 0x68, 0x91, 0x18, 0x90, 0x80, 0x90, 0x40, 0x80, 0xa4, +0x45, 0x48, 0x38, 0xaa, 0x80, 0xa4, 0x45, 0x40, 0x38, 0xa7, 0x90, 0x28, +0x81, 0x38, 0xa6, 0x90, 0x38, 0xa4, 0x45, 0x20, 0x38, 0xa5, 0xa4, 0x45, +0x10, 0x38, 0xa3, 0x90, 0x28, 0x80, 0x38, 0xa1, 0x80, 0x38, 0xa0, 0x80, +0x90, 0x40, 0x10, 0x10, 0x80, 0x24, 0x44, 0xf8, 0x10, 0x10, 0x90, 0x38, +0xa4, 0x44, 0xe8, 0x38, 0x9e, 0xa4, 0x44, 0xd8, 0x38, 0x9c, 0x90, 0x50, +0x80, 0xc9, 0xa2, 0x26, 0x00, 0x85, 0x38, 0x99, 0x80, 0x38, 0x97, 0x9a, +0xd0, 0x03, 0xe0, 0x91, 0x60, 0x90, 0xb0, 0x88, 0x00, 0x68, 0x84, 0x10, +0x10, 0xc9, 0xe1, 0x2a, 0x00, 0x85, 0x34, 0xb9, 0xcb, 0x61, 0x22, 0x80, +0x85, 0x34, 0x99, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x29, +0xc0, 0x85, 0x34, 0xb7, 0xcb, 0x61, 0x22, 0x40, 0x85, 0x34, 0x98, 0x90, +0xb0, 0x88, 0x00, 0x68, 0x84, 0x10, 0x10, 0xc9, 0xe1, 0x29, 0x80, 0x85, +0x34, 0xb5, 0xcb, 0x61, 0x22, 0x00, 0x85, 0x34, 0x97, 0x88, 0x00, 0x68, +0x84, 0x10, 0x10, 0xc9, 0xe1, 0x29, 0x40, 0x85, 0x34, 0xb3, 0xcb, 0x61, +0x21, 0xc0, 0x85, 0x34, 0x96, 0x90, 0x90, 0x90, 0x48, 0xcb, 0xa1, 0x20, +0x00, 0x85, 0x34, 0x85, 0xcb, 0xa1, 0x1f, 0xc0, 0x85, 0x34, 0x84, 0x90, +0x48, 0xcb, 0xa1, 0x1f, 0x80, 0x85, 0x34, 0x83, 0xcb, 0xa1, 0x1f, 0x40, +0x85, 0x34, 0x82, 0xcb, 0xa2, 0x1d, 0x00, 0x80, 0x38, 0x75, 0x92, 0x40, +0x91, 0x20, 0x90, 0x90, 0x90, 0x48, 0x8c, 0x23, 0x60, 0x84, 0x24, 0x23, +0xd8, 0x8c, 0x23, 0x58, 0x84, 0x24, 0x23, 0xd0, 0x90, 0x48, 0x8c, 0x23, +0x50, 0x84, 0x24, 0x23, 0xc8, 0x8c, 0x23, 0x48, 0x84, 0x24, 0x23, 0xc0, +0x90, 0x90, 0x90, 0x48, 0x8c, 0x23, 0x38, 0x84, 0x24, 0x23, 0xb0, 0x8c, +0x23, 0x30, 0x84, 0x24, 0x23, 0xa8, 0x90, 0x48, 0x8c, 0x23, 0x28, 0x84, +0x24, 0x23, 0xa0, 0x8c, 0x23, 0x20, 0x84, 0x24, 0x23, 0x98, 0x91, 0x20, +0x90, 0x90, 0x90, 0x48, 0x8c, 0x23, 0x10, 0x84, 0x24, 0x23, 0x88, 0x8c, +0x23, 0x08, 0x84, 0x24, 0x23, 0x80, 0x90, 0x48, 0x8c, 0x23, 0x00, 0x84, +0x24, 0x23, 0x78, 0x8c, 0x22, 0xf8, 0x84, 0x24, 0x23, 0x70, 0x90, 0x38, +0xa4, 0x22, 0xe0, 0x34, 0x5d, 0xa4, 0x22, 0xd0, 0x34, 0x5b, 0xa0, 0x0f, +0x50, 0xa0, 0x09, 0x08, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, +0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x1c, 0x00, 0x38, 0x6c, 0xe5, 0x22, +0x18, 0x00, 0x38, 0x6a, 0xcb, 0x61, 0x12, 0x40, 0x85, 0x34, 0x58, 0x98, +0x50, 0x00, 0x80, 0xe5, 0x22, 0x14, 0x00, 0x38, 0x4c, 0xe5, 0x22, 0x10, +0x00, 0x38, 0x4a, 0xcb, 0x61, 0x12, 0x00, 0x85, 0x34, 0x57, 0x90, 0x48, +0xcb, 0xa1, 0x11, 0xc0, 0x85, 0x34, 0x56, 0xcb, 0xa1, 0x11, 0x80, 0x85, +0x34, 0x55, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, +0x09, 0x00, 0x38, 0x30, 0xe5, 0x22, 0x03, 0x00, 0x38, 0x18, 0xcb, 0x61, +0x11, 0x00, 0x85, 0x34, 0x53, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0xfd, +0x00, 0x38, 0x00, 0xe5, 0x21, 0xf7, 0x00, 0x37, 0xe8, 0xcb, 0x61, 0x10, +0xc0, 0x85, 0x34, 0x52, 0x90, 0x48, 0xcb, 0xa1, 0x10, 0x80, 0x85, 0x34, +0x51, 0xcb, 0xa1, 0x10, 0x40, 0x85, 0x34, 0x50, 0x92, 0x20, 0x91, 0x30, +0x90, 0xb8, 0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0xa0, 0x84, +0x30, 0x3e, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0x80, 0x84, 0x30, 0x3c, 0xd5, +0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x28, 0xc0, 0xc0, 0x81, 0x30, 0x24, +0x90, 0x78, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x1c, 0xc0, 0xc0, +0x81, 0x30, 0x18, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x10, 0xc0, +0xc0, 0x81, 0x30, 0x0c, 0x91, 0x70, 0x90, 0xd8, 0xd5, 0x03, 0x80, 0xc8, +0xe1, 0xf3, 0x00, 0x81, 0x8c, 0x01, 0xc0, 0x84, 0x30, 0x40, 0xc8, 0xe1, +0xf4, 0x00, 0x81, 0x8c, 0x01, 0x90, 0x84, 0x30, 0x3d, 0xd5, 0x02, 0x80, +0xc8, 0xe1, 0xf2, 0x80, 0x81, 0x30, 0x2c, 0xc8, 0xe1, 0xef, 0x80, 0x81, +0x30, 0x26, 0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0xe9, 0x80, 0x81, +0x30, 0x20, 0xc8, 0xe1, 0xea, 0x80, 0x81, 0x30, 0x1a, 0xd5, 0x02, 0x80, +0xc8, 0xe1, 0xe9, 0x00, 0x81, 0x30, 0x14, 0xc8, 0xe1, 0xe6, 0x00, 0x81, +0x30, 0x0e, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, +0x00, 0x80, 0xe5, 0x22, 0x16, 0x00, 0x38, 0x54, 0xe5, 0x22, 0x17, 0x00, +0x38, 0x66, 0xcb, 0x61, 0x0f, 0xc0, 0x85, 0x34, 0x4e, 0x98, 0x50, 0x00, +0x80, 0xe5, 0x22, 0x0e, 0x00, 0x38, 0x34, 0xe5, 0x22, 0x0f, 0x00, 0x38, +0x46, 0xcb, 0x61, 0x0f, 0x80, 0x85, 0x34, 0x4d, 0x90, 0x48, 0xcb, 0xa1, +0x0f, 0x40, 0x85, 0x34, 0x4c, 0xcb, 0xa1, 0x0f, 0x00, 0x85, 0x34, 0x4b, +0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x07, 0x00, +0x38, 0x28, 0xe5, 0x22, 0x01, 0x00, 0x38, 0x10, 0xcb, 0x61, 0x0d, 0x40, +0x85, 0x34, 0x3a, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x21, 0xfb, 0x00, 0x37, +0xf8, 0xe5, 0x21, 0xf5, 0x00, 0x37, 0xe0, 0xcb, 0x61, 0x0d, 0x00, 0x85, +0x34, 0x39, 0x90, 0x48, 0xcb, 0xa1, 0x0c, 0xc0, 0x85, 0x34, 0x38, 0xcb, +0xa1, 0x0c, 0x80, 0x85, 0x34, 0x37, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, 0x01, 0x80, 0x30, 0x07, +0x90, 0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, 0xe5, 0x20, 0x00, 0x00, +0x30, 0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xed, 0x00, 0x37, 0xae, +0xe5, 0x21, 0xee, 0x40, 0x37, 0xc4, 0x90, 0x40, 0xe5, 0x21, 0xe3, 0x80, +0x37, 0x88, 0xe5, 0x21, 0xe4, 0xc0, 0x37, 0x9e, 0x80, 0x99, 0x28, 0x02, +0xf0, 0x8c, 0x21, 0x48, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x19, 0x00, +0x38, 0x62, 0xe5, 0x22, 0x17, 0x80, 0x38, 0x68, 0x90, 0x40, 0xe5, 0x22, +0x11, 0x00, 0x38, 0x42, 0xe5, 0x22, 0x0f, 0x80, 0x38, 0x48, 0x91, 0x48, +0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x08, 0x00, 0x38, 0x2c, +0xe5, 0x22, 0x02, 0x00, 0x38, 0x14, 0xcb, 0x61, 0x0b, 0x00, 0x85, 0x34, +0x30, 0x90, 0x40, 0xe5, 0x21, 0xfc, 0x00, 0x37, 0xfc, 0xe5, 0x21, 0xf6, +0x00, 0x37, 0xe4, 0x90, 0x48, 0xcb, 0xa1, 0x0a, 0x80, 0x85, 0x34, 0x2e, +0xcb, 0xa1, 0x0a, 0xc0, 0x85, 0x34, 0x2f, 0x10, 0x10, 0x90, 0x80, 0x90, +0x40, 0xe5, 0x21, 0xf0, 0x80, 0x37, 0xc0, 0xe5, 0x21, 0xef, 0x00, 0x37, +0xc8, 0x90, 0x40, 0xe5, 0x21, 0xe7, 0x00, 0x37, 0x9a, 0xe5, 0x21, 0xe5, +0x80, 0x37, 0xa2, }; static const struct ia64_dis_names ia64_dis_names[] = { diff --git a/opcodes/ia64-opc-b.c b/opcodes/ia64-opc-b.c index 9772b37..9a4a850 100644 --- a/opcodes/ia64-opc-b.c +++ b/opcodes/ia64-opc-b.c @@ -32,6 +32,7 @@ #define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) #define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) #define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32) #define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) #define mBtype bBtype (-1) @@ -41,11 +42,14 @@ #define mPr bPr (-1) #define mWha bWha (-1) #define mWhb bWhb (-1) +#define mWhc bWhc (-1) #define mX6 bX6 (-1) #define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) #define OpPaWhaD(a,b,c,d) \ (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpPaWhcD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD) #define OpBtypePaWhaD(a,b,c,d,e) \ (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ (mOp | mBtype | mPa | mWha | mD) @@ -188,30 +192,30 @@ struct ia64_opcode ia64_opcodes_b[] = {"break.b", B0, OpX6 (0, 0x00), {IMMU21}}, - {"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}}, - {"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO}, - {"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}}, - {"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO}, - {"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}}, - {"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO}, - {"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}}, - {"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO}, - {"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}}, - {"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO}, - {"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}}, - {"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO}, - {"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}}, - {"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO}, - {"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}}, - {"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO}, - {"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}}, - {"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}}, - {"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}}, - {"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}}, - {"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}}, - {"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}}, - {"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}}, - {"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}}, + {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}}, + {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}}, + {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}}, + {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}}, + {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}}, + {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}}, + {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}}, + {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}}, + {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}}, + {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}}, + {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}}, + {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}}, + {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}}, + {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}}, + {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}}, + {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}}, #define BRP(a,b,c) \ B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED @@ -470,6 +474,7 @@ struct ia64_opcode ia64_opcodes_b[] = #undef bPr #undef bWha #undef bWhb +#undef bWhc #undef bX6 #undef mBtype #undef mD @@ -478,9 +483,11 @@ struct ia64_opcode ia64_opcodes_b[] = #undef mPr #undef mWha #undef mWhb +#undef mWhc #undef mX6 #undef OpX6 #undef OpPaWhaD +#undef OpPaWhcD #undef OpBtypePaWhaD #undef OpBtypePaWhaDPr #undef OpX6BtypePaWhaD diff --git a/opcodes/ip2k-asm.c b/opcodes/ip2k-asm.c new file mode 100644 index 0000000..c2163b0 --- /dev/null +++ b/opcodes/ip2k-asm.c @@ -0,0 +1,977 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ + +static const char * +parse_fr (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + char *old_strp; + char *afteroffset; + enum cgen_parse_operand_result result_type; + bfd_vma value; + extern CGEN_KEYWORD ip2k_cgen_opval_register_names; + long tempvalue; + + old_strp = *strp; + afteroffset = NULL; + + + /* Check here to see if you're about to try parsing a w as the first arg */ + /* and return an error if you are. */ + if ( (strncmp(*strp,"w",1)==0) || (strncmp(*strp,"W",1)==0) ) + { + (*strp)++; + + if ( (strncmp(*strp,",",1)==0) || isspace(**strp) ) + { + /* We've been passed a w. Return with an error message so that */ + /* cgen will try the next parsing option. */ + errmsg = _("W keyword invalid in FR operand slot."); + return errmsg; + } + *strp = old_strp; + } + + + /* Attempt parse as register keyword. */ + /* old_strp = *strp; */ + + errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, valuep); + if ( *strp != NULL ) + if (errmsg == NULL) + return errmsg; + + /* Attempt to parse for "(IP)" */ + afteroffset = strstr(*strp,"(IP)"); + + if ( afteroffset == NULL) + { + /* Make sure it's not in lower case */ + afteroffset = strstr(*strp,"(ip)"); + } + + if ( afteroffset != NULL ) + { + if ( afteroffset != *strp ) + { + /* Invalid offset present.*/ + errmsg = _("offset(IP) is not a valid form"); + return errmsg; + } + else + { + *strp += 4; + *valuep = 0; + errmsg = NULL; + return errmsg; + } + } + + /* Attempt to parse for DP. ex: mov w, offset(DP) */ + /* mov offset(DP),w */ + + /* Try parsing it as an address and see what comes back */ + + afteroffset = strstr(*strp,"(DP)"); + + if ( afteroffset == NULL) + { + /* Maybe it's in lower case */ + afteroffset = strstr(*strp,"(dp)"); + } + + if ( afteroffset != NULL ) + { + if ( afteroffset == *strp ) + { + /* No offset present. Use 0 by default. */ + tempvalue = 0; + errmsg = NULL; + } + else + { + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET, + & result_type, & tempvalue); + } + + if (errmsg == NULL) + { + if ( (tempvalue >= 0) && (tempvalue <= 127) ) + { + /* Value is ok. Fix up the first 2 bits and return */ + *valuep = 0x0100 | tempvalue; + *strp += 4; /* skip over the (DP) in *strp */ + return errmsg; + } else + { + /* Found something there in front of (DP) but it's out of range. */ + errmsg = _("(DP) offset out of range."); + return errmsg; + } + + } + } + + + /* Attempt to parse for SP. ex: mov w, offset(SP) */ + /* mov offset(SP), w */ + + + afteroffset = strstr(*strp,"(SP)"); + + if (afteroffset == NULL) + { + /* Maybe it's in lower case. */ + afteroffset = strstr(*strp, "(sp)"); + } + + if ( afteroffset != NULL ) + { + if ( afteroffset == *strp ) + { + /* No offset present. Use 0 by default. */ + tempvalue = 0; + errmsg = NULL; + } + else + { + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR_OFFSET, + & result_type, & tempvalue); + } + if (errmsg == NULL) + { + if ( (tempvalue >= 0) && (tempvalue <= 127) ) + { + /* Value is ok. Fix up the first 2 bits and return */ + *valuep = 0x0180 | tempvalue; + *strp += 4; /* skip over the (SP) in *strp */ + return errmsg; + } else + { + /* Found something there in front of (SP) but it's out of range. */ + errmsg = _("(SP) offset out of range."); + return errmsg; + } + + } + } + + + /* Attempt to parse as an address. */ + *strp = old_strp; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9, + & result_type, & value); + if (errmsg == NULL) + { + *valuep = value; + + /* if a parenthesis is found, warn about invalid form */ + + if (**strp == '(') + { + errmsg = _("illegal use of parentheses"); + } + /* if a numeric value is specified, ensure that it is between 1 and 255 */ + else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + if (value < 0x1 || value > 0xff) + errmsg = _("operand out of range (not between 1 and 255)"); + } + } + return errmsg; +} + +static const char * +parse_addr16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + long value; + + if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16H ) + code = BFD_RELOC_IP2K_HI8DATA; + else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16L ) + code = BFD_RELOC_IP2K_LO8DATA; + else + { + /* Something is very wrong. opindex has to be one of the above. */ + errmsg = _("parse_addr16: invalid opindex."); + return errmsg; + } + + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + /* We either have a relocation or a number now. */ + if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER ) + { + /* We got a number back. */ + if ( code == BFD_RELOC_IP2K_HI8DATA ) + value >>= 8; + else /* code = BFD_RELOC_IP2K_LOW8DATA */ + value &= 0x00FF; + } + *valuep = value; + } + + return errmsg; +} + + + static const char * + parse_addr16_p (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_IP2K_PAGE3; + long value; + + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER ) + *valuep = (value >> 13) & 0x7; + else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED ) + *valuep = value; + } + return errmsg; + } + + + static const char * + parse_addr16_cjp (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + long value; + + if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP ) + code = BFD_RELOC_IP2K_ADDR16CJP; + else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P ) + code = BFD_RELOC_IP2K_PAGE3; + + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if (errmsg == NULL) + { + if ( result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER ) + { + if ( (value & 0x1) == 0) /* If the address is even .... */ + { + if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16CJP ) + *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ + else if ( opindex == (CGEN_OPERAND_TYPE)IP2K_OPERAND_ADDR16P ) + *valuep = (value >> 14) & 0x7; + } + else + errmsg = _("Byte address required. - must be even."); + }else if ( result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED ) + { + /* This will happen for things like (s2-s1) where s2 and s1 */ + /* are labels. */ + *valuep = value; + } + else + errmsg = _("cgen_parse_address returned a symbol. Literal required."); + } + return errmsg; + } + + +static const char * +parse_lit8 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_reloc_code_real_type code = BFD_RELOC_NONE; + long value; + + /* Parse %OP relocating operators. */ + if (strncmp (*strp, "%bank", 5) == 0) + { + *strp += 5; + code = BFD_RELOC_IP2K_BANK; + } + else if (strncmp (*strp, "%lo8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_LO8DATA; + } + else if (strncmp (*strp, "%hi8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_HI8DATA; + } + else if (strncmp (*strp, "%ex8data", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_EX8DATA; + } + else if (strncmp (*strp, "%lo8insn", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_LO8INSN; + } + else if (strncmp (*strp, "%hi8insn", 8) == 0) + { + *strp += 8; + code = BFD_RELOC_IP2K_HI8INSN; + } + + + /* Parse %op operand. */ + if (code != BFD_RELOC_NONE) + { + errmsg = cgen_parse_address (cd, strp, opindex, code, + & result_type, & value); + if ((errmsg == NULL) && + (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED)) + errmsg = _("%operator operand is not a symbol"); + + *valuep = value; + } + /* Parse as a number. */ + else + { + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + + /* Truncate to eight bits to accept both signed and unsigned input. */ + if (errmsg == NULL) + *valuep &= 0xFF; + } + + return errmsg; +} + +static const char * +parse_bit3 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + char mode = 0; + long count = 0; + unsigned long value; + + if (strncmp (*strp, "%bit", 4) == 0) + { + *strp += 4; + mode = 1; + } + else if (strncmp (*strp, "%msbbit", 7) == 0) + { + *strp += 7; + mode = 1; + } + else if (strncmp (*strp, "%lsbbit", 7) == 0) + { + *strp += 7; + mode = 2; + } + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); + if (errmsg) { + return errmsg; + } + + if (mode) { + value = (unsigned long) *valuep; + if (value == 0) { + errmsg = _("Attempt to find bit index of 0"); + return errmsg; + } + + if (mode == 1) { + count = 31; + while ((value & 0x80000000) == 0) { + count--; + value <<= 1; + } + } else if (mode == 2) { + count = 0; + while ((value & 0x00000001) == 0) { + count++; + value >>= 1; + } + } + + *valuep = count; + } + + return errmsg; +} + + +/* -- dis.c */ + +const char * ip2k_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +ip2k_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16CJP, &fields->f_addr16cjp); + break; + case IP2K_OPERAND_ADDR16H : + errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16H, &fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16L : + errmsg = parse_addr16 (cd, strp, IP2K_OPERAND_ADDR16L, &fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16P : + errmsg = parse_addr16_cjp (cd, strp, IP2K_OPERAND_ADDR16P, &fields->f_page3); + break; + case IP2K_OPERAND_BITNO : + errmsg = parse_bit3 (cd, strp, IP2K_OPERAND_BITNO, &fields->f_bitno); + break; + case IP2K_OPERAND_CBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_CBIT, &junk); + break; + case IP2K_OPERAND_DCBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_DCBIT, &junk); + break; + case IP2K_OPERAND_FR : + errmsg = parse_fr (cd, strp, IP2K_OPERAND_FR, &fields->f_reg); + break; + case IP2K_OPERAND_LIT8 : + errmsg = parse_lit8 (cd, strp, IP2K_OPERAND_LIT8, &fields->f_imm8); + break; + case IP2K_OPERAND_PABITS : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_PABITS, &junk); + break; + case IP2K_OPERAND_RETI3 : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_RETI3, &fields->f_reti3); + break; + case IP2K_OPERAND_ZBIT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IP2K_OPERAND_ZBIT, &junk); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const ip2k_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +ip2k_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + ip2k_cgen_init_opcode_table (cd); + ip2k_cgen_init_ibld_table (cd); + cd->parse_handlers = & ip2k_cgen_parse_handlers[0]; + cd->parse_operand = ip2k_cgen_parse_operand; +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by ip2k_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +ip2k_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +ip2k_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! ip2k_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +ip2k_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! ip2k_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/ip2k-desc.c b/opcodes/ip2k-desc.c new file mode 100644 index 0000000..a676e77 --- /dev/null +++ b/opcodes/ip2k-desc.c @@ -0,0 +1,1219 @@ +/* CPU data for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include <stdio.h> +#include <stdarg.h> +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "ip2022", MACH_IP2022 }, + { "ip2022ext", MACH_IP2022EXT }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "ip2k", ISA_IP2K }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "EXT-SKIP-INSN", &bool_attr[0], &bool_attr[0] }, + { "SKIPA", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA ip2k_cgen_isa_table[] = { + { "ip2k", 16, 16, 16, 16 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH ip2k_cgen_mach_table[] = { + { "ip2022", "ip2022", MACH_IP2022, 0 }, + { "ip2022ext", "ip2022ext", MACH_IP2022EXT, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY ip2k_cgen_opval_register_names_entries[] = +{ + { "ADDRSEL", 2, {0, {0}}, 0, 0 }, + { "ADDRX", 3, {0, {0}}, 0, 0 }, + { "IPH", 4, {0, {0}}, 0, 0 }, + { "IPL", 5, {0, {0}}, 0, 0 }, + { "SPH", 6, {0, {0}}, 0, 0 }, + { "SPL", 7, {0, {0}}, 0, 0 }, + { "PCH", 8, {0, {0}}, 0, 0 }, + { "PCL", 9, {0, {0}}, 0, 0 }, + { "WREG", 10, {0, {0}}, 0, 0 }, + { "STATUS", 11, {0, {0}}, 0, 0 }, + { "DPH", 12, {0, {0}}, 0, 0 }, + { "DPL", 13, {0, {0}}, 0, 0 }, + { "SPDREG", 14, {0, {0}}, 0, 0 }, + { "MULH", 15, {0, {0}}, 0, 0 }, + { "ADDRH", 16, {0, {0}}, 0, 0 }, + { "ADDRL", 17, {0, {0}}, 0, 0 }, + { "DATAH", 18, {0, {0}}, 0, 0 }, + { "DATAL", 19, {0, {0}}, 0, 0 }, + { "INTVECH", 20, {0, {0}}, 0, 0 }, + { "INTVECL", 21, {0, {0}}, 0, 0 }, + { "INTSPD", 22, {0, {0}}, 0, 0 }, + { "INTF", 23, {0, {0}}, 0, 0 }, + { "INTE", 24, {0, {0}}, 0, 0 }, + { "INTED", 25, {0, {0}}, 0, 0 }, + { "FCFG", 26, {0, {0}}, 0, 0 }, + { "TCTRL", 27, {0, {0}}, 0, 0 }, + { "XCFG", 28, {0, {0}}, 0, 0 }, + { "EMCFG", 29, {0, {0}}, 0, 0 }, + { "IPCH", 30, {0, {0}}, 0, 0 }, + { "IPCL", 31, {0, {0}}, 0, 0 }, + { "RAIN", 32, {0, {0}}, 0, 0 }, + { "RAOUT", 33, {0, {0}}, 0, 0 }, + { "RADIR", 34, {0, {0}}, 0, 0 }, + { "LFSRH", 35, {0, {0}}, 0, 0 }, + { "RBIN", 36, {0, {0}}, 0, 0 }, + { "RBOUT", 37, {0, {0}}, 0, 0 }, + { "RBDIR", 38, {0, {0}}, 0, 0 }, + { "LFSRL", 39, {0, {0}}, 0, 0 }, + { "RCIN", 40, {0, {0}}, 0, 0 }, + { "RCOUT", 41, {0, {0}}, 0, 0 }, + { "RCDIR", 42, {0, {0}}, 0, 0 }, + { "LFSRA", 43, {0, {0}}, 0, 0 }, + { "RDIN", 44, {0, {0}}, 0, 0 }, + { "RDOUT", 45, {0, {0}}, 0, 0 }, + { "RDDIR", 46, {0, {0}}, 0, 0 }, + { "REIN", 48, {0, {0}}, 0, 0 }, + { "REOUT", 49, {0, {0}}, 0, 0 }, + { "REDIR", 50, {0, {0}}, 0, 0 }, + { "RFIN", 52, {0, {0}}, 0, 0 }, + { "RFOUT", 53, {0, {0}}, 0, 0 }, + { "RFDIR", 54, {0, {0}}, 0, 0 }, + { "RGOUT", 57, {0, {0}}, 0, 0 }, + { "RGDIR", 58, {0, {0}}, 0, 0 }, + { "RTTMR", 64, {0, {0}}, 0, 0 }, + { "RTCFG", 65, {0, {0}}, 0, 0 }, + { "T0TMR", 66, {0, {0}}, 0, 0 }, + { "T0CFG", 67, {0, {0}}, 0, 0 }, + { "T1CNTH", 68, {0, {0}}, 0, 0 }, + { "T1CNTL", 69, {0, {0}}, 0, 0 }, + { "T1CAP1H", 70, {0, {0}}, 0, 0 }, + { "T1CAP1L", 71, {0, {0}}, 0, 0 }, + { "T1CAP2H", 72, {0, {0}}, 0, 0 }, + { "T1CMP2H", 72, {0, {0}}, 0, 0 }, + { "T1CAP2L", 73, {0, {0}}, 0, 0 }, + { "T1CMP2L", 73, {0, {0}}, 0, 0 }, + { "T1CMP1H", 74, {0, {0}}, 0, 0 }, + { "T1CMP1L", 75, {0, {0}}, 0, 0 }, + { "T1CFG1H", 76, {0, {0}}, 0, 0 }, + { "T1CFG1L", 77, {0, {0}}, 0, 0 }, + { "T1CFG2H", 78, {0, {0}}, 0, 0 }, + { "T1CFG2L", 79, {0, {0}}, 0, 0 }, + { "ADCH", 80, {0, {0}}, 0, 0 }, + { "ADCL", 81, {0, {0}}, 0, 0 }, + { "ADCCFG", 82, {0, {0}}, 0, 0 }, + { "ADCTMR", 83, {0, {0}}, 0, 0 }, + { "T2CNTH", 84, {0, {0}}, 0, 0 }, + { "T2CNTL", 85, {0, {0}}, 0, 0 }, + { "T2CAP1H", 86, {0, {0}}, 0, 0 }, + { "T2CAP1L", 87, {0, {0}}, 0, 0 }, + { "T2CAP2H", 88, {0, {0}}, 0, 0 }, + { "T2CMP2H", 88, {0, {0}}, 0, 0 }, + { "T2CAP2L", 89, {0, {0}}, 0, 0 }, + { "T2CMP2L", 89, {0, {0}}, 0, 0 }, + { "T2CMP1H", 90, {0, {0}}, 0, 0 }, + { "T2CMP1L", 91, {0, {0}}, 0, 0 }, + { "T2CFG1H", 92, {0, {0}}, 0, 0 }, + { "T2CFG1L", 93, {0, {0}}, 0, 0 }, + { "T2CFG2H", 94, {0, {0}}, 0, 0 }, + { "T2CFG2L", 95, {0, {0}}, 0, 0 }, + { "S1TMRH", 96, {0, {0}}, 0, 0 }, + { "S1TMRL", 97, {0, {0}}, 0, 0 }, + { "S1TBUFH", 98, {0, {0}}, 0, 0 }, + { "S1TBUFL", 99, {0, {0}}, 0, 0 }, + { "S1TCFG", 100, {0, {0}}, 0, 0 }, + { "S1RCNT", 101, {0, {0}}, 0, 0 }, + { "S1RBUFH", 102, {0, {0}}, 0, 0 }, + { "S1RBUFL", 103, {0, {0}}, 0, 0 }, + { "S1RCFG", 104, {0, {0}}, 0, 0 }, + { "S1RSYNC", 105, {0, {0}}, 0, 0 }, + { "S1INTF", 106, {0, {0}}, 0, 0 }, + { "S1INTE", 107, {0, {0}}, 0, 0 }, + { "S1MODE", 108, {0, {0}}, 0, 0 }, + { "S1SMASK", 109, {0, {0}}, 0, 0 }, + { "PSPCFG", 110, {0, {0}}, 0, 0 }, + { "CMPCFG", 111, {0, {0}}, 0, 0 }, + { "S2TMRH", 112, {0, {0}}, 0, 0 }, + { "S2TMRL", 113, {0, {0}}, 0, 0 }, + { "S2TBUFH", 114, {0, {0}}, 0, 0 }, + { "S2TBUFL", 115, {0, {0}}, 0, 0 }, + { "S2TCFG", 116, {0, {0}}, 0, 0 }, + { "S2RCNT", 117, {0, {0}}, 0, 0 }, + { "S2RBUFH", 118, {0, {0}}, 0, 0 }, + { "S2RBUFL", 119, {0, {0}}, 0, 0 }, + { "S2RCFG", 120, {0, {0}}, 0, 0 }, + { "S2RSYNC", 121, {0, {0}}, 0, 0 }, + { "S2INTF", 122, {0, {0}}, 0, 0 }, + { "S2INTE", 123, {0, {0}}, 0, 0 }, + { "S2MODE", 124, {0, {0}}, 0, 0 }, + { "S2SMASK", 125, {0, {0}}, 0, 0 }, + { "CALLH", 126, {0, {0}}, 0, 0 }, + { "CALLL", 127, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD ip2k_cgen_opval_register_names = +{ + & ip2k_cgen_opval_register_names_entries[0], + 121, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY ip2k_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-registers", HW_H_REGISTERS, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, + { "h-stack", HW_H_STACK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-pabits", HW_H_PABITS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-dcbit", HW_H_DCBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, + { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, + { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } +}; + +#undef A + + +/* The instruction field table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_IFLD_##a) +#else +#define A(a) (1 << CGEN_IFLD_/**/a) +#endif + +const CGEN_IFLD ip2k_cgen_ifld_table[] = +{ + { IP2K_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_REG, "f-reg", 0, 16, 8, 9, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { IP2K_F_ADDR16CJP, "f-addr16cjp", 0, 16, 12, 13, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { IP2K_F_DIR, "f-dir", 0, 16, 9, 1, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_BITNO, "f-bitno", 0, 16, 11, 3, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP3, "f-op3", 0, 16, 15, 3, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP4MID, "f-op4mid", 0, 16, 11, 4, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP6, "f-op6", 0, 16, 15, 6, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP6_10LOW, "f-op6-10low", 0, 16, 9, 10, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_OP6_7LOW, "f-op6-7low", 0, 16, 9, 7, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_RETI3, "f-reti3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } }, + { IP2K_F_SKIPB, "f-skipb", 0, 16, 12, 1, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, + { IP2K_F_PAGE3, "f-page3", 0, 16, 2, 3, { 0, { (1<<MACH_BASE) } } }, + { 0, 0, 0, 0, 0, 0, {0, {0}} } +}; + +#undef A + + + +/* multi ifield declarations */ + + + +/* multi ifield definitions */ + + +/* The operand table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_OPERAND_##a) +#else +#define A(a) (1 << CGEN_OPERAND_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IP2K_OPERAND_##op +#else +#define OPERAND(op) IP2K_OPERAND_/**/op +#endif + +const CGEN_OPERAND ip2k_cgen_operand_table[] = +{ +/* pc: program counter */ + { "pc", IP2K_OPERAND_PC, HW_H_PC, 0, 0, + { 0, &(ip2k_cgen_ifld_table[0]) }, + { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, +/* addr16cjp: 13-bit address */ + { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13, + { 0, &(ip2k_cgen_ifld_table[4]) }, + { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, +/* fr: register */ + { "fr", IP2K_OPERAND_FR, HW_H_REGISTERS, 8, 9, + { 0, &(ip2k_cgen_ifld_table[3]) }, + { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } }, +/* lit8: 8-bit signed literal */ + { "lit8", IP2K_OPERAND_LIT8, HW_H_SINT, 7, 8, + { 0, &(ip2k_cgen_ifld_table[2]) }, + { 0, { (1<<MACH_BASE) } } }, +/* bitno: bit number */ + { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3, + { 0, &(ip2k_cgen_ifld_table[6]) }, + { 0, { (1<<MACH_BASE) } } }, +/* addr16p: page number */ + { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3, + { 0, &(ip2k_cgen_ifld_table[16]) }, + { 0, { (1<<MACH_BASE) } } }, +/* addr16h: high 8 bits of address */ + { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8, + { 0, &(ip2k_cgen_ifld_table[2]) }, + { 0, { (1<<MACH_BASE) } } }, +/* addr16l: low 8 bits of address */ + { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8, + { 0, &(ip2k_cgen_ifld_table[2]) }, + { 0, { (1<<MACH_BASE) } } }, +/* reti3: reti flags */ + { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3, + { 0, &(ip2k_cgen_ifld_table[14]) }, + { 0, { (1<<MACH_BASE) } } }, +/* pabits: page bits */ + { "pabits", IP2K_OPERAND_PABITS, HW_H_PABITS, 0, 0, + { 0, 0 }, + { 0, { (1<<MACH_BASE) } } }, +/* zbit: zero bit */ + { "zbit", IP2K_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, + { 0, 0 }, + { 0, { (1<<MACH_BASE) } } }, +/* cbit: carry bit */ + { "cbit", IP2K_OPERAND_CBIT, HW_H_CBIT, 0, 0, + { 0, 0 }, + { 0, { (1<<MACH_BASE) } } }, +/* dcbit: digit carry bit */ + { "dcbit", IP2K_OPERAND_DCBIT, HW_H_DCBIT, 0, 0, + { 0, 0 }, + { 0, { (1<<MACH_BASE) } } }, + { 0, 0, 0, 0, 0, {0, {0}} } +}; + +#undef A + + +/* The instruction table. */ + +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif + +static const CGEN_IBASE ip2k_cgen_insn_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { 0, 0, 0, 0, {0, {0}} }, +/* jmp $addr16cjp */ + { + IP2K_INSN_JMP, "jmp", "jmp", 16, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + }, +/* call $addr16cjp */ + { + IP2K_INSN_CALL, "call", "call", 16, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + }, +/* sb $fr,$bitno */ + { + IP2K_INSN_SB, "sb", "sb", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* snb $fr,$bitno */ + { + IP2K_INSN_SNB, "snb", "snb", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* setb $fr,$bitno */ + { + IP2K_INSN_SETB, "setb", "setb", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* clrb $fr,$bitno */ + { + IP2K_INSN_CLRB, "clrb", "clrb", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* xor W,#$lit8 */ + { + IP2K_INSN_XORW_L, "xorw_l", "xor", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* and W,#$lit8 */ + { + IP2K_INSN_ANDW_L, "andw_l", "and", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* or W,#$lit8 */ + { + IP2K_INSN_ORW_L, "orw_l", "or", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* add W,#$lit8 */ + { + IP2K_INSN_ADDW_L, "addw_l", "add", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* sub W,#$lit8 */ + { + IP2K_INSN_SUBW_L, "subw_l", "sub", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* cmp W,#$lit8 */ + { + IP2K_INSN_CMPW_L, "cmpw_l", "cmp", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* retw #$lit8 */ + { + IP2K_INSN_RETW_L, "retw_l", "retw", 16, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + }, +/* cse W,#$lit8 */ + { + IP2K_INSN_CSEW_L, "csew_l", "cse", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* csne W,#$lit8 */ + { + IP2K_INSN_CSNEW_L, "csnew_l", "csne", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* push #$lit8 */ + { + IP2K_INSN_PUSH_L, "push_l", "push", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* muls W,#$lit8 */ + { + IP2K_INSN_MULSW_L, "mulsw_l", "muls", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* mulu W,#$lit8 */ + { + IP2K_INSN_MULUW_L, "muluw_l", "mulu", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* loadl #$lit8 */ + { + IP2K_INSN_LOADL_L, "loadl_l", "loadl", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* loadh #$lit8 */ + { + IP2K_INSN_LOADH_L, "loadh_l", "loadh", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* loadl $addr16l */ + { + IP2K_INSN_LOADL_A, "loadl_a", "loadl", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* loadh $addr16h */ + { + IP2K_INSN_LOADH_A, "loadh_a", "loadh", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* addc $fr,W */ + { + IP2K_INSN_ADDCFR_W, "addcfr_w", "addc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* addc W,$fr */ + { + IP2K_INSN_ADDCW_FR, "addcw_fr", "addc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* incsnz $fr */ + { + IP2K_INSN_INCSNZ_FR, "incsnz_fr", "incsnz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* incsnz W,$fr */ + { + IP2K_INSN_INCSNZW_FR, "incsnzw_fr", "incsnz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* muls W,$fr */ + { + IP2K_INSN_MULSW_FR, "mulsw_fr", "muls", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* mulu W,$fr */ + { + IP2K_INSN_MULUW_FR, "muluw_fr", "mulu", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* decsnz $fr */ + { + IP2K_INSN_DECSNZ_FR, "decsnz_fr", "decsnz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* decsnz W,$fr */ + { + IP2K_INSN_DECSNZW_FR, "decsnzw_fr", "decsnz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* subc W,$fr */ + { + IP2K_INSN_SUBCW_FR, "subcw_fr", "subc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* subc $fr,W */ + { + IP2K_INSN_SUBCFR_W, "subcfr_w", "subc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* pop $fr */ + { + IP2K_INSN_POP_FR, "pop_fr", "pop", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* push $fr */ + { + IP2K_INSN_PUSH_FR, "push_fr", "push", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* cse W,$fr */ + { + IP2K_INSN_CSEW_FR, "csew_fr", "cse", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* csne W,$fr */ + { + IP2K_INSN_CSNEW_FR, "csnew_fr", "csne", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* incsz $fr */ + { + IP2K_INSN_INCSZ_FR, "incsz_fr", "incsz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* incsz W,$fr */ + { + IP2K_INSN_INCSZW_FR, "incszw_fr", "incsz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* swap $fr */ + { + IP2K_INSN_SWAP_FR, "swap_fr", "swap", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* swap W,$fr */ + { + IP2K_INSN_SWAPW_FR, "swapw_fr", "swap", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* rl $fr */ + { + IP2K_INSN_RL_FR, "rl_fr", "rl", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* rl W,$fr */ + { + IP2K_INSN_RLW_FR, "rlw_fr", "rl", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* rr $fr */ + { + IP2K_INSN_RR_FR, "rr_fr", "rr", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* rr W,$fr */ + { + IP2K_INSN_RRW_FR, "rrw_fr", "rr", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* decsz $fr */ + { + IP2K_INSN_DECSZ_FR, "decsz_fr", "decsz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* decsz W,$fr */ + { + IP2K_INSN_DECSZW_FR, "decszw_fr", "decsz", 16, + { 0|A(SKIP_CTI), { (1<<MACH_BASE) } } + }, +/* inc $fr */ + { + IP2K_INSN_INC_FR, "inc_fr", "inc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* inc W,$fr */ + { + IP2K_INSN_INCW_FR, "incw_fr", "inc", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* not $fr */ + { + IP2K_INSN_NOT_FR, "not_fr", "not", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* not W,$fr */ + { + IP2K_INSN_NOTW_FR, "notw_fr", "not", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* test $fr */ + { + IP2K_INSN_TEST_FR, "test_fr", "test", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* mov W,#$lit8 */ + { + IP2K_INSN_MOVW_L, "movw_l", "mov", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* mov $fr,W */ + { + IP2K_INSN_MOVFR_W, "movfr_w", "mov", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* mov W,$fr */ + { + IP2K_INSN_MOVW_FR, "movw_fr", "mov", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* add $fr,W */ + { + IP2K_INSN_ADDFR_W, "addfr_w", "add", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* add W,$fr */ + { + IP2K_INSN_ADDW_FR, "addw_fr", "add", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* xor $fr,W */ + { + IP2K_INSN_XORFR_W, "xorfr_w", "xor", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* xor W,$fr */ + { + IP2K_INSN_XORW_FR, "xorw_fr", "xor", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* and $fr,W */ + { + IP2K_INSN_ANDFR_W, "andfr_w", "and", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* and W,$fr */ + { + IP2K_INSN_ANDW_FR, "andw_fr", "and", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* or $fr,W */ + { + IP2K_INSN_ORFR_W, "orfr_w", "or", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* or W,$fr */ + { + IP2K_INSN_ORW_FR, "orw_fr", "or", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* dec $fr */ + { + IP2K_INSN_DEC_FR, "dec_fr", "dec", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* dec W,$fr */ + { + IP2K_INSN_DECW_FR, "decw_fr", "dec", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* sub $fr,W */ + { + IP2K_INSN_SUBFR_W, "subfr_w", "sub", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* sub W,$fr */ + { + IP2K_INSN_SUBW_FR, "subw_fr", "sub", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* clr $fr */ + { + IP2K_INSN_CLR_FR, "clr_fr", "clr", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* cmp W,$fr */ + { + IP2K_INSN_CMPW_FR, "cmpw_fr", "cmp", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* speed #$lit8 */ + { + IP2K_INSN_SPEED, "speed", "speed", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* ireadi */ + { + IP2K_INSN_IREADI, "ireadi", "ireadi", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* iwritei */ + { + IP2K_INSN_IWRITEI, "iwritei", "iwritei", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* fread */ + { + IP2K_INSN_FREAD, "fread", "fread", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* fwrite */ + { + IP2K_INSN_FWRITE, "fwrite", "fwrite", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* iread */ + { + IP2K_INSN_IREAD, "iread", "iread", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* iwrite */ + { + IP2K_INSN_IWRITE, "iwrite", "iwrite", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* page $addr16p */ + { + IP2K_INSN_PAGE, "page", "page", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* system */ + { + IP2K_INSN_SYSTEM, "system", "system", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* reti #$reti3 */ + { + IP2K_INSN_RETI, "reti", "reti", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* ret */ + { + IP2K_INSN_RET, "ret", "ret", 16, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + }, +/* int */ + { + IP2K_INSN_INT, "int", "int", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* breakx */ + { + IP2K_INSN_BREAKX, "breakx", "breakx", 16, + { 0|A(EXT_SKIP_INSN), { (1<<MACH_BASE) } } + }, +/* cwdt */ + { + IP2K_INSN_CWDT, "cwdt", "cwdt", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* ferase */ + { + IP2K_INSN_FERASE, "ferase", "ferase", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* retnp */ + { + IP2K_INSN_RETNP, "retnp", "retnp", 16, + { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } } + }, +/* break */ + { + IP2K_INSN_BREAK, "break", "break", 16, + { 0, { (1<<MACH_BASE) } } + }, +/* nop */ + { + IP2K_INSN_NOP, "nop", "nop", 16, + { 0, { (1<<MACH_BASE) } } + }, +}; + +#undef OP +#undef A + +/* Initialize anything needed to be done once, before any cpu_open call. */ +static void init_tables PARAMS ((void)); + +static void +init_tables () +{ +} + +static const CGEN_MACH * lookup_mach_via_bfd_name + PARAMS ((const CGEN_MACH *, const char *)); +static void build_hw_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_operand_table PARAMS ((CGEN_CPU_TABLE *)); +static void build_insn_table PARAMS ((CGEN_CPU_TABLE *)); +static void ip2k_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *)); + +/* Subroutine of ip2k_cgen_cpu_open to look up a mach via its bfd name. */ + +static const CGEN_MACH * +lookup_mach_via_bfd_name (table, name) + const CGEN_MACH *table; + const char *name; +{ + while (table->name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & ip2k_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & ip2k_cgen_ifld_table[0]; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & ip2k_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of ip2k_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & ip2k_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of ip2k_cgen_cpu_open to rebuild the tables. */ + +static void +ip2k_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & ip2k_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & ip2k_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "ip2k_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +ip2k_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (ip2k_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "ip2k_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "ip2k_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = ip2k_cgen_rebuild_tables; + ip2k_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to ip2k_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +ip2k_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return ip2k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +ip2k_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/ip2k-desc.h b/opcodes/ip2k-desc.h new file mode 100644 index 0000000..74819ac --- /dev/null +++ b/opcodes/ip2k-desc.h @@ -0,0 +1,251 @@ +/* CPU data header for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IP2K_CPU_H +#define IP2K_CPU_H + +#define CGEN_ARCH ip2k + +/* Given symbol S, return ip2k_cgen_<S>. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) ip2k##_cgen_##s +#else +#define CGEN_SYM(s) ip2k/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_IP2KBF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 2 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 2 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 12 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 3 + +/* Enums. */ + +/* Enum declaration for op6 enums. */ +typedef enum insn_op6 { + OP6_OTHER1, OP6_OTHER2, OP6_SUB, OP6_DEC + , OP6_OR, OP6_AND, OP6_XOR, OP6_ADD + , OP6_TEST, OP6_NOT, OP6_INC, OP6_DECSZ + , OP6_RR, OP6_RL, OP6_SWAP, OP6_INCSZ + , OP6_CSE, OP6_POP, OP6_SUBC, OP6_DECSNZ + , OP6_MULU, OP6_MULS, OP6_INCSNZ, OP6_ADDC +} INSN_OP6; + +/* Enum declaration for dir enums. */ +typedef enum insn_dir { + DIR_TO_W, DIR_NOTTO_W +} INSN_DIR; + +/* Enum declaration for op4 enums. */ +typedef enum insn_op4 { + OP4_LITERAL = 7, OP4_CLRB = 8, OP4_SETB = 9, OP4_SNB = 10 + , OP4_SB = 11 +} INSN_OP4; + +/* Enum declaration for op4mid enums. */ +typedef enum insn_op4mid { + OP4MID_LOADH_L = 0, OP4MID_LOADL_L = 1, OP4MID_MULU_L = 2, OP4MID_MULS_L = 3 + , OP4MID_PUSH_L = 4, OP4MID_CSNE_L = 6, OP4MID_CSE_L = 7, OP4MID_RETW_L = 8 + , OP4MID_CMP_L = 9, OP4MID_SUB_L = 10, OP4MID_ADD_L = 11, OP4MID_MOV_L = 12 + , OP4MID_OR_L = 13, OP4MID_AND_L = 14, OP4MID_XOR_L = 15 +} INSN_OP4MID; + +/* Enum declaration for op3 enums. */ +typedef enum insn_op3 { + OP3_CALL = 6, OP3_JMP = 7 +} INSN_OP3; + +/* Enum declaration for . */ +typedef enum register_names { + H_REGISTERS_ADDRSEL = 2, H_REGISTERS_ADDRX = 3, H_REGISTERS_IPH = 4, H_REGISTERS_IPL = 5 + , H_REGISTERS_SPH = 6, H_REGISTERS_SPL = 7, H_REGISTERS_PCH = 8, H_REGISTERS_PCL = 9 + , H_REGISTERS_WREG = 10, H_REGISTERS_STATUS = 11, H_REGISTERS_DPH = 12, H_REGISTERS_DPL = 13 + , H_REGISTERS_SPDREG = 14, H_REGISTERS_MULH = 15, H_REGISTERS_ADDRH = 16, H_REGISTERS_ADDRL = 17 + , H_REGISTERS_DATAH = 18, H_REGISTERS_DATAL = 19, H_REGISTERS_INTVECH = 20, H_REGISTERS_INTVECL = 21 + , H_REGISTERS_INTSPD = 22, H_REGISTERS_INTF = 23, H_REGISTERS_INTE = 24, H_REGISTERS_INTED = 25 + , H_REGISTERS_FCFG = 26, H_REGISTERS_TCTRL = 27, H_REGISTERS_XCFG = 28, H_REGISTERS_EMCFG = 29 + , H_REGISTERS_IPCH = 30, H_REGISTERS_IPCL = 31, H_REGISTERS_RAIN = 32, H_REGISTERS_RAOUT = 33 + , H_REGISTERS_RADIR = 34, H_REGISTERS_LFSRH = 35, H_REGISTERS_RBIN = 36, H_REGISTERS_RBOUT = 37 + , H_REGISTERS_RBDIR = 38, H_REGISTERS_LFSRL = 39, H_REGISTERS_RCIN = 40, H_REGISTERS_RCOUT = 41 + , H_REGISTERS_RCDIR = 42, H_REGISTERS_LFSRA = 43, H_REGISTERS_RDIN = 44, H_REGISTERS_RDOUT = 45 + , H_REGISTERS_RDDIR = 46, H_REGISTERS_REIN = 48, H_REGISTERS_REOUT = 49, H_REGISTERS_REDIR = 50 + , H_REGISTERS_RFIN = 52, H_REGISTERS_RFOUT = 53, H_REGISTERS_RFDIR = 54, H_REGISTERS_RGOUT = 57 + , H_REGISTERS_RGDIR = 58, H_REGISTERS_RTTMR = 64, H_REGISTERS_RTCFG = 65, H_REGISTERS_T0TMR = 66 + , H_REGISTERS_T0CFG = 67, H_REGISTERS_T1CNTH = 68, H_REGISTERS_T1CNTL = 69, H_REGISTERS_T1CAP1H = 70 + , H_REGISTERS_T1CAP1L = 71, H_REGISTERS_T1CAP2H = 72, H_REGISTERS_T1CMP2H = 72, H_REGISTERS_T1CAP2L = 73 + , H_REGISTERS_T1CMP2L = 73, H_REGISTERS_T1CMP1H = 74, H_REGISTERS_T1CMP1L = 75, H_REGISTERS_T1CFG1H = 76 + , H_REGISTERS_T1CFG1L = 77, H_REGISTERS_T1CFG2H = 78, H_REGISTERS_T1CFG2L = 79, H_REGISTERS_ADCH = 80 + , H_REGISTERS_ADCL = 81, H_REGISTERS_ADCCFG = 82, H_REGISTERS_ADCTMR = 83, H_REGISTERS_T2CNTH = 84 + , H_REGISTERS_T2CNTL = 85, H_REGISTERS_T2CAP1H = 86, H_REGISTERS_T2CAP1L = 87, H_REGISTERS_T2CAP2H = 88 + , H_REGISTERS_T2CMP2H = 88, H_REGISTERS_T2CAP2L = 89, H_REGISTERS_T2CMP2L = 89, H_REGISTERS_T2CMP1H = 90 + , H_REGISTERS_T2CMP1L = 91, H_REGISTERS_T2CFG1H = 92, H_REGISTERS_T2CFG1L = 93, H_REGISTERS_T2CFG2H = 94 + , H_REGISTERS_T2CFG2L = 95, H_REGISTERS_S1TMRH = 96, H_REGISTERS_S1TMRL = 97, H_REGISTERS_S1TBUFH = 98 + , H_REGISTERS_S1TBUFL = 99, H_REGISTERS_S1TCFG = 100, H_REGISTERS_S1RCNT = 101, H_REGISTERS_S1RBUFH = 102 + , H_REGISTERS_S1RBUFL = 103, H_REGISTERS_S1RCFG = 104, H_REGISTERS_S1RSYNC = 105, H_REGISTERS_S1INTF = 106 + , H_REGISTERS_S1INTE = 107, H_REGISTERS_S1MODE = 108, H_REGISTERS_S1SMASK = 109, H_REGISTERS_PSPCFG = 110 + , H_REGISTERS_CMPCFG = 111, H_REGISTERS_S2TMRH = 112, H_REGISTERS_S2TMRL = 113, H_REGISTERS_S2TBUFH = 114 + , H_REGISTERS_S2TBUFL = 115, H_REGISTERS_S2TCFG = 116, H_REGISTERS_S2RCNT = 117, H_REGISTERS_S2RBUFH = 118 + , H_REGISTERS_S2RBUFL = 119, H_REGISTERS_S2RCFG = 120, H_REGISTERS_S2RSYNC = 121, H_REGISTERS_S2INTF = 122 + , H_REGISTERS_S2INTE = 123, H_REGISTERS_S2MODE = 124, H_REGISTERS_S2SMASK = 125, H_REGISTERS_CALLH = 126 + , H_REGISTERS_CALLL = 127 +} REGISTER_NAMES; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_IP2K, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld ip2k_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for ip2k ifield types. */ +typedef enum ifield_type { + IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8, IP2K_F_REG + , IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO, IP2K_F_OP3 + , IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6, IP2K_F_OP8 + , IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3, IP2K_F_SKIPB + , IP2K_F_PAGE3, IP2K_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) IP2K_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for ip2k hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_SPR, HW_H_REGISTERS, HW_H_STACK + , HW_H_PABITS, HW_H_ZBIT, HW_H_CBIT, HW_H_DCBIT + , HW_H_PC, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for ip2k operand types. */ +typedef enum cgen_operand_type { + IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR, IP2K_OPERAND_LIT8 + , IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H, IP2K_OPERAND_ADDR16L + , IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT, IP2K_OPERAND_CBIT + , IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 13 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN, CGEN_INSN_SKIPA + , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE ip2k_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE ip2k_cgen_insn_attr_table[]; + +/* Hardware decls. */ + + + + + +#endif /* IP2K_CPU_H */ diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c new file mode 100644 index 0000000..91aaa61 --- /dev/null +++ b/opcodes/ip2k-dis.c @@ -0,0 +1,743 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + +/* -- dis.c */ + +static void +print_fr (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + extern CGEN_KEYWORD ip2k_cgen_opval_register_names; + long offsettest; + long offsetvalue; + + if ( value == 0 ) /* This is (IP) */ + { + (*info->fprintf_func) (info->stream, "%s", "(IP)"); + return; + } + + offsettest = value >> 7; + offsetvalue = value & 0x7F; + + /* Check to see if first two bits are 10 -> (DP) */ + if ( offsettest == 2 ) + { + if ( offsetvalue == 0 ) + (*info->fprintf_func) (info->stream, "%s","(DP)"); + else + (*info->fprintf_func) (info->stream, "$%x%s",offsetvalue, "(DP)"); + return; + } + + /* Check to see if first two bits are 11 -> (SP) */ + if ( offsettest == 3 ) + { + if ( offsetvalue == 0 ) + (*info->fprintf_func) (info->stream, "%s", "(SP)"); + else + (*info->fprintf_func) (info->stream, "$%x%s", offsetvalue,"(SP)"); + return; + } + + /* Attempt to print as a register keyword. */ + ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value); + if (ke != NULL) + { + (*info->fprintf_func) (info->stream, "%s", ke->name); + return; + } + + /* Print as an address literal. */ + (*info->fprintf_func) (info->stream, "$%02x", value); +} + +static void +print_dollarhex (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%x", value); +} + +static void +print_dollarhex8 (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%02x", value); +} + +static void +print_dollarhex16 (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%04x", value); +} + +static void +print_dollarhex_addr16h (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + /* This is a loadh instruction. Shift the value to the left */ + /* by 8 bits so that disassembled code will reassemble properly. */ + value = ((value << 8) & 0xFF00); + + (*info->fprintf_func) (info->stream, "$%04x", value); +} + +static void +print_dollarhex_addr16l (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "$%04x", value); +} + +static void +print_dollarhex_p (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + value = ((value << 14) & 0x1C000); + ;value = (value & 0x1FFFF); + (*info->fprintf_func) (info->stream, "$%05x", value); +} + +static void +print_dollarhex_cj (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + value = ((value << 1) & 0x1FFFF); + (*info->fprintf_func) (info->stream, "$%05x", value); +} + + +static void +print_decimal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) dis_info; + + (*info->fprintf_func) (info->stream, "%d", value); +} + + + +/* -- */ + +void ip2k_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +ip2k_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + print_dollarhex_cj (cd, info, fields->f_addr16cjp, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); + break; + case IP2K_OPERAND_ADDR16H : + print_dollarhex_addr16h (cd, info, fields->f_imm8, 0, pc, length); + break; + case IP2K_OPERAND_ADDR16L : + print_dollarhex_addr16l (cd, info, fields->f_imm8, 0, pc, length); + break; + case IP2K_OPERAND_ADDR16P : + print_dollarhex_p (cd, info, fields->f_page3, 0, pc, length); + break; + case IP2K_OPERAND_BITNO : + print_decimal (cd, info, fields->f_bitno, 0, pc, length); + break; + case IP2K_OPERAND_CBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case IP2K_OPERAND_DCBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + case IP2K_OPERAND_FR : + print_fr (cd, info, fields->f_reg, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); + break; + case IP2K_OPERAND_LIT8 : + print_dollarhex8 (cd, info, fields->f_imm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); + break; + case IP2K_OPERAND_PABITS : + print_normal (cd, info, 0, 0, pc, length); + break; + case IP2K_OPERAND_RETI3 : + print_dollarhex (cd, info, fields->f_reti3, 0, pc, length); + break; + case IP2K_OPERAND_ZBIT : + print_normal (cd, info, 0, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const ip2k_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +ip2k_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + ip2k_cgen_init_opcode_table (cd); + ip2k_cgen_init_ibld_table (cd); + cd->print_handlers = & ip2k_cgen_print_handlers[0]; + cd->print_operand = ip2k_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + ip2k_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! ip2k_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_ip2k (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_ip2k +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + ip2k_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/ip2k-ibld.c b/opcodes/ip2k-ibld.c new file mode 100644 index 0000000..22e2d8d --- /dev/null +++ b/opcodes/ip2k-ibld.c @@ -0,0 +1,952 @@ +/* Instruction building/extraction support for ip2k. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include <stdio.h> +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * ip2k_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +ip2k_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + errmsg = insert_normal (cd, fields->f_addr16cjp, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 12, 13, 16, total_length, buffer); + break; + case IP2K_OPERAND_ADDR16H : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_ADDR16L : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_ADDR16P : + errmsg = insert_normal (cd, fields->f_page3, 0, 0, 2, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_BITNO : + errmsg = insert_normal (cd, fields->f_bitno, 0, 0, 11, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + errmsg = insert_normal (cd, fields->f_reg, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 9, 16, total_length, buffer); + break; + case IP2K_OPERAND_LIT8 : + errmsg = insert_normal (cd, fields->f_imm8, 0, 0, 7, 8, 16, total_length, buffer); + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + errmsg = insert_normal (cd, fields->f_reti3, 0, 0, 2, 3, 16, total_length, buffer); + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int ip2k_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +ip2k_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 12, 13, 16, total_length, pc, & fields->f_addr16cjp); + break; + case IP2K_OPERAND_ADDR16H : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16L : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_ADDR16P : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_page3); + break; + case IP2K_OPERAND_BITNO : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 3, 16, total_length, pc, & fields->f_bitno); + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 9, 16, total_length, pc, & fields->f_reg); + break; + case IP2K_OPERAND_LIT8 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 16, total_length, pc, & fields->f_imm8); + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 16, total_length, pc, & fields->f_reti3); + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const ip2k_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const ip2k_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int ip2k_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma ip2k_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +ip2k_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + value = fields->f_addr16cjp; + break; + case IP2K_OPERAND_ADDR16H : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16L : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16P : + value = fields->f_page3; + break; + case IP2K_OPERAND_BITNO : + value = fields->f_bitno; + break; + case IP2K_OPERAND_CBIT : + value = 0; + break; + case IP2K_OPERAND_DCBIT : + value = 0; + break; + case IP2K_OPERAND_FR : + value = fields->f_reg; + break; + case IP2K_OPERAND_LIT8 : + value = fields->f_imm8; + break; + case IP2K_OPERAND_PABITS : + value = 0; + break; + case IP2K_OPERAND_RETI3 : + value = fields->f_reti3; + break; + case IP2K_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +ip2k_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + value = fields->f_addr16cjp; + break; + case IP2K_OPERAND_ADDR16H : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16L : + value = fields->f_imm8; + break; + case IP2K_OPERAND_ADDR16P : + value = fields->f_page3; + break; + case IP2K_OPERAND_BITNO : + value = fields->f_bitno; + break; + case IP2K_OPERAND_CBIT : + value = 0; + break; + case IP2K_OPERAND_DCBIT : + value = 0; + break; + case IP2K_OPERAND_FR : + value = fields->f_reg; + break; + case IP2K_OPERAND_LIT8 : + value = fields->f_imm8; + break; + case IP2K_OPERAND_PABITS : + value = 0; + break; + case IP2K_OPERAND_RETI3 : + value = fields->f_reti3; + break; + case IP2K_OPERAND_ZBIT : + value = 0; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void ip2k_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void ip2k_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +ip2k_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + fields->f_addr16cjp = value; + break; + case IP2K_OPERAND_ADDR16H : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16L : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16P : + fields->f_page3 = value; + break; + case IP2K_OPERAND_BITNO : + fields->f_bitno = value; + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + fields->f_reg = value; + break; + case IP2K_OPERAND_LIT8 : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + fields->f_reti3 = value; + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +ip2k_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case IP2K_OPERAND_ADDR16CJP : + fields->f_addr16cjp = value; + break; + case IP2K_OPERAND_ADDR16H : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16L : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_ADDR16P : + fields->f_page3 = value; + break; + case IP2K_OPERAND_BITNO : + fields->f_bitno = value; + break; + case IP2K_OPERAND_CBIT : + break; + case IP2K_OPERAND_DCBIT : + break; + case IP2K_OPERAND_FR : + fields->f_reg = value; + break; + case IP2K_OPERAND_LIT8 : + fields->f_imm8 = value; + break; + case IP2K_OPERAND_PABITS : + break; + case IP2K_OPERAND_RETI3 : + fields->f_reti3 = value; + break; + case IP2K_OPERAND_ZBIT : + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +ip2k_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & ip2k_cgen_insert_handlers[0]; + cd->extract_handlers = & ip2k_cgen_extract_handlers[0]; + + cd->insert_operand = ip2k_cgen_insert_operand; + cd->extract_operand = ip2k_cgen_extract_operand; + + cd->get_int_operand = ip2k_cgen_get_int_operand; + cd->set_int_operand = ip2k_cgen_set_int_operand; + cd->get_vma_operand = ip2k_cgen_get_vma_operand; + cd->set_vma_operand = ip2k_cgen_set_vma_operand; +} diff --git a/opcodes/ip2k-opc.c b/opcodes/ip2k-opc.c new file mode 100644 index 0000000..311a0f7 --- /dev/null +++ b/opcodes/ip2k-opc.c @@ -0,0 +1,914 @@ +/* Instruction opcode table for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "ip2k-desc.h" +#include "ip2k-opc.h" +#include "libiberty.h" + +/* -- opc.c */ + +/* A better hash function for instruction mnemonics. */ +unsigned int +ip2k_asm_hash (insn) + const char* insn; +{ + unsigned int hash; + const char* m = insn; + + for (hash = 0; *m && !isspace(*m); m++) + hash = (hash * 23) ^ (0x1F & tolower(*m)); + + /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ + + return hash % CGEN_ASM_HASH_SIZE; +} + + + + +/* -- asm.c */ +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & ip2k_cgen_ifld_table[IP2K_##f] +#else +#define F(f) & ip2k_cgen_ifld_table[IP2K_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_jmp = { + 16, 16, 0xe000, { { F (F_OP3) }, { F (F_ADDR16CJP) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb = { + 16, 16, 0xf000, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_xorw_l = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loadl_a = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_loadh_a = { + 16, 16, 0xff00, { { F (F_OP4) }, { F (F_OP4MID) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addcfr_w = { + 16, 16, 0xfe00, { { F (F_OP6) }, { F (F_DIR) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_speed = { + 16, 16, 0xff00, { { F (F_OP8) }, { F (F_IMM8) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ireadi = { + 16, 16, 0xffff, { { F (F_OP6) }, { F (F_OP6_10LOW) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_page = { + 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_PAGE3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_reti = { + 16, 16, 0xfff8, { { F (F_OP6) }, { F (F_OP6_7LOW) }, { F (F_RETI3) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IP2K_OPERAND_##op +#else +#define OPERAND(op) IP2K_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE ip2k_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* jmp $addr16cjp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16CJP), 0 } }, + & ifmt_jmp, { 0xe000 } + }, +/* call $addr16cjp */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16CJP), 0 } }, + & ifmt_jmp, { 0xc000 } + }, +/* sb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0xb000 } + }, +/* snb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0xa000 } + }, +/* setb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0x9000 } + }, +/* clrb $fr,$bitno */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', OP (BITNO), 0 } }, + & ifmt_sb, { 0x8000 } + }, +/* xor W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7f00 } + }, +/* and W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7e00 } + }, +/* or W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7d00 } + }, +/* add W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7b00 } + }, +/* sub W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7a00 } + }, +/* cmp W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7900 } + }, +/* retw #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7800 } + }, +/* cse W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7700 } + }, +/* csne W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7600 } + }, +/* push #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7400 } + }, +/* muls W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7300 } + }, +/* mulu W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7200 } + }, +/* loadl #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7100 } + }, +/* loadh #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7000 } + }, +/* loadl $addr16l */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16L), 0 } }, + & ifmt_loadl_a, { 0x7100 } + }, +/* loadh $addr16h */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16H), 0 } }, + & ifmt_loadh_a, { 0x7000 } + }, +/* addc $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x5e00 } + }, +/* addc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5c00 } + }, +/* incsnz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5a00 } + }, +/* incsnz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5800 } + }, +/* muls W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5400 } + }, +/* mulu W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x5000 } + }, +/* decsnz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4e00 } + }, +/* decsnz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4c00 } + }, +/* subc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4800 } + }, +/* subc $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x4a00 } + }, +/* pop $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4600 } + }, +/* push $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4400 } + }, +/* cse W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4200 } + }, +/* csne W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x4000 } + }, +/* incsz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3e00 } + }, +/* incsz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3c00 } + }, +/* swap $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3a00 } + }, +/* swap W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3800 } + }, +/* rl $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3600 } + }, +/* rl W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3400 } + }, +/* rr $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3200 } + }, +/* rr W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x3000 } + }, +/* decsz $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2e00 } + }, +/* decsz W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2c00 } + }, +/* inc $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2a00 } + }, +/* inc W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2800 } + }, +/* not $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2600 } + }, +/* not W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2400 } + }, +/* test $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2200 } + }, +/* mov W,#$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', '#', OP (LIT8), 0 } }, + & ifmt_xorw_l, { 0x7c00 } + }, +/* mov $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x200 } + }, +/* mov W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x2000 } + }, +/* add $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1e00 } + }, +/* add W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1c00 } + }, +/* xor $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1a00 } + }, +/* xor W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1800 } + }, +/* and $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1600 } + }, +/* and W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1400 } + }, +/* or $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0x1200 } + }, +/* or W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x1000 } + }, +/* dec $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0xe00 } + }, +/* dec W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0xc00 } + }, +/* sub $fr,W */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), ',', 'W', 0 } }, + & ifmt_addcfr_w, { 0xa00 } + }, +/* sub W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x800 } + }, +/* clr $fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x600 } + }, +/* cmp W,$fr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', 'W', ',', OP (FR), 0 } }, + & ifmt_addcfr_w, { 0x400 } + }, +/* speed #$lit8 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (LIT8), 0 } }, + & ifmt_speed, { 0x100 } + }, +/* ireadi */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1d } + }, +/* iwritei */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1c } + }, +/* fread */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1b } + }, +/* fwrite */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1a } + }, +/* iread */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x19 } + }, +/* iwrite */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x18 } + }, +/* page $addr16p */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (ADDR16P), 0 } }, + & ifmt_page, { 0x10 } + }, +/* system */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0xff } + }, +/* reti #$reti3 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', '#', OP (RETI3), 0 } }, + & ifmt_reti, { 0x8 } + }, +/* ret */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x7 } + }, +/* int */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x6 } + }, +/* breakx */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x5 } + }, +/* cwdt */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x4 } + }, +/* ferase */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x3 } + }, +/* retnp */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x2 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x1 } + }, +/* nop */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_ireadi, { 0x0 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & ip2k_cgen_ifld_table[IP2K_##f] +#else +#define F(f) & ip2k_cgen_ifld_table[IP2K_/**/f] +#endif +static const CGEN_IFMT ifmt_sc = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_snc = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sz = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_snz = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_skip = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_skipb = { + 16, 16, 0xffff, { { F (F_OP4) }, { F (F_BITNO) }, { F (F_REG) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IP2K_OPERAND_##op +#else +#define OPERAND(op) IP2K_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE ip2k_cgen_macro_insn_table[] = +{ +/* sc */ + { + -1, "sc", "sc", 16, + { 0|A(ALIAS), { (1<<MACH_BASE) } } + }, +/* snc */ + { + -1, "snc", "snc", 16, + { 0|A(ALIAS), { (1<<MACH_BASE) } } + }, +/* sz */ + { + -1, "sz", "sz", 16, + { 0|A(ALIAS), { (1<<MACH_BASE) } } + }, +/* snz */ + { + -1, "snz", "snz", 16, + { 0|A(ALIAS), { (1<<MACH_BASE) } } + }, +/* skip */ + { + -1, "skip", "skip", 16, + { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } } + }, +/* skip */ + { + -1, "skipb", "skip", 16, + { 0|A(SKIPA)|A(ALIAS), { (1<<MACH_BASE) } } + }, +}; + +/* The macro instruction opcode table. */ + +static const CGEN_OPCODE ip2k_cgen_macro_insn_opcode_table[] = +{ +/* sc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_sc, { 0xb00b } + }, +/* snc */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_snc, { 0xa00b } + }, +/* sz */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_sz, { 0xb40b } + }, +/* snz */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_snz, { 0xa40b } + }, +/* skip */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_skip, { 0xa009 } + }, +/* skip */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_skipb, { 0xb009 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +#ifndef CGEN_ASM_HASH_P +#define CGEN_ASM_HASH_P(insn) 1 +#endif + +#ifndef CGEN_DIS_HASH_P +#define CGEN_DIS_HASH_P(insn) 1 +#endif + +/* Return non-zero if INSN is to be added to the hash table. + Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ + +static int +asm_hash_insn_p (insn) + const CGEN_INSN *insn ATTRIBUTE_UNUSED; +{ + return CGEN_ASM_HASH_P (insn); +} + +static int +dis_hash_insn_p (insn) + const CGEN_INSN *insn; +{ + /* If building the hash table and the NO-DIS attribute is present, + ignore. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) + return 0; + return CGEN_DIS_HASH_P (insn); +} + +#ifndef CGEN_ASM_HASH +#define CGEN_ASM_HASH_SIZE 127 +#ifdef CGEN_MNEMONIC_OPERANDS +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) +#else +#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ +#endif +#endif + +/* It doesn't make much sense to provide a default here, + but while this is under development we do. + BUFFER is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +#ifndef CGEN_DIS_HASH +#define CGEN_DIS_HASH_SIZE 256 +#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) +#endif + +/* The result is the hash value of the insn. + Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ + +static unsigned int +asm_hash_insn (mnem) + const char * mnem; +{ + return CGEN_ASM_HASH (mnem); +} + +/* BUF is a pointer to the bytes of the insn, target order. + VALUE is the first base_insn_bitsize bits as an int in host order. */ + +static unsigned int +dis_hash_insn (buf, value) + const char * buf ATTRIBUTE_UNUSED; + CGEN_INSN_INT value ATTRIBUTE_UNUSED; +{ + return CGEN_DIS_HASH (buf, value); +} + +static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int)); + +/* Set the recorded length of the insn in the CGEN_FIELDS struct. */ + +static void +set_fields_bitsize (fields, size) + CGEN_FIELDS *fields; + int size; +{ + CGEN_FIELDS_BITSIZE (fields) = size; +} + +/* Function to call before using the operand instance table. + This plugs the opcode entries and macro instructions into the cpu table. */ + +void +ip2k_cgen_init_opcode_table (cd) + CGEN_CPU_DESC cd; +{ + int i; + int num_macros = (sizeof (ip2k_cgen_macro_insn_table) / + sizeof (ip2k_cgen_macro_insn_table[0])); + const CGEN_IBASE *ib = & ip2k_cgen_macro_insn_table[0]; + const CGEN_OPCODE *oc = & ip2k_cgen_macro_insn_opcode_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN)); + memset (insns, 0, num_macros * sizeof (CGEN_INSN)); + for (i = 0; i < num_macros; ++i) + { + insns[i].base = &ib[i]; + insns[i].opcode = &oc[i]; + ip2k_cgen_build_insn_regex (& insns[i]); + } + cd->macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & ip2k_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + ip2k_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/ip2k-opc.h b/opcodes/ip2k-opc.h new file mode 100644 index 0000000..0f8df98 --- /dev/null +++ b/opcodes/ip2k-opc.h @@ -0,0 +1,133 @@ +/* Instruction opcode header for ip2k. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IP2K_OPC_H +#define IP2K_OPC_H + +/* -- opc.h */ + +/* Check applicability of instructions against machines. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) + +#define CGEN_ASM_HASH_SIZE 127 +#define CGEN_ASM_HASH(insn) ip2k_asm_hash(insn) + +extern unsigned int ip2k_asm_hash (const char *insn); + + +/* Special check to ensure that instruction exists for given machine. */ +static int +ip2k_cgen_insn_supported (cd, insn) + CGEN_CPU_DESC cd; + CGEN_INSN *insn; +{ + int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); + + /* No mach attribute? Assume it's supported for all machs. */ + if (machs == 0) + return 1; + + return ((machs & cd->machs) != 0); +} + + +/* -- opc.c */ +/* Enum declaration for ip2k instruction types. */ +typedef enum cgen_insn_type { + IP2K_INSN_INVALID, IP2K_INSN_JMP, IP2K_INSN_CALL, IP2K_INSN_SB + , IP2K_INSN_SNB, IP2K_INSN_SETB, IP2K_INSN_CLRB, IP2K_INSN_XORW_L + , IP2K_INSN_ANDW_L, IP2K_INSN_ORW_L, IP2K_INSN_ADDW_L, IP2K_INSN_SUBW_L + , IP2K_INSN_CMPW_L, IP2K_INSN_RETW_L, IP2K_INSN_CSEW_L, IP2K_INSN_CSNEW_L + , IP2K_INSN_PUSH_L, IP2K_INSN_MULSW_L, IP2K_INSN_MULUW_L, IP2K_INSN_LOADL_L + , IP2K_INSN_LOADH_L, IP2K_INSN_LOADL_A, IP2K_INSN_LOADH_A, IP2K_INSN_ADDCFR_W + , IP2K_INSN_ADDCW_FR, IP2K_INSN_INCSNZ_FR, IP2K_INSN_INCSNZW_FR, IP2K_INSN_MULSW_FR + , IP2K_INSN_MULUW_FR, IP2K_INSN_DECSNZ_FR, IP2K_INSN_DECSNZW_FR, IP2K_INSN_SUBCW_FR + , IP2K_INSN_SUBCFR_W, IP2K_INSN_POP_FR, IP2K_INSN_PUSH_FR, IP2K_INSN_CSEW_FR + , IP2K_INSN_CSNEW_FR, IP2K_INSN_INCSZ_FR, IP2K_INSN_INCSZW_FR, IP2K_INSN_SWAP_FR + , IP2K_INSN_SWAPW_FR, IP2K_INSN_RL_FR, IP2K_INSN_RLW_FR, IP2K_INSN_RR_FR + , IP2K_INSN_RRW_FR, IP2K_INSN_DECSZ_FR, IP2K_INSN_DECSZW_FR, IP2K_INSN_INC_FR + , IP2K_INSN_INCW_FR, IP2K_INSN_NOT_FR, IP2K_INSN_NOTW_FR, IP2K_INSN_TEST_FR + , IP2K_INSN_MOVW_L, IP2K_INSN_MOVFR_W, IP2K_INSN_MOVW_FR, IP2K_INSN_ADDFR_W + , IP2K_INSN_ADDW_FR, IP2K_INSN_XORFR_W, IP2K_INSN_XORW_FR, IP2K_INSN_ANDFR_W + , IP2K_INSN_ANDW_FR, IP2K_INSN_ORFR_W, IP2K_INSN_ORW_FR, IP2K_INSN_DEC_FR + , IP2K_INSN_DECW_FR, IP2K_INSN_SUBFR_W, IP2K_INSN_SUBW_FR, IP2K_INSN_CLR_FR + , IP2K_INSN_CMPW_FR, IP2K_INSN_SPEED, IP2K_INSN_IREADI, IP2K_INSN_IWRITEI + , IP2K_INSN_FREAD, IP2K_INSN_FWRITE, IP2K_INSN_IREAD, IP2K_INSN_IWRITE + , IP2K_INSN_PAGE, IP2K_INSN_SYSTEM, IP2K_INSN_RETI, IP2K_INSN_RET + , IP2K_INSN_INT, IP2K_INSN_BREAKX, IP2K_INSN_CWDT, IP2K_INSN_FERASE + , IP2K_INSN_RETNP, IP2K_INSN_BREAK, IP2K_INSN_NOP +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID IP2K_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) IP2K_INSN_NOP + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_imm8; + long f_reg; + long f_addr16cjp; + long f_dir; + long f_bitno; + long f_op3; + long f_op4; + long f_op4mid; + long f_op6; + long f_op8; + long f_op6_10low; + long f_op6_7low; + long f_reti3; + long f_skipb; + long f_page3; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* IP2K_OPC_H */ diff --git a/opcodes/m68hc11-dis.c b/opcodes/m68hc11-dis.c index bb0cc20..c721d16 100644 --- a/opcodes/m68hc11-dis.c +++ b/opcodes/m68hc11-dis.c @@ -1,6 +1,6 @@ /* m68hc11-dis.c -- Motorola 68HC11 & 68HC12 disassembly - Copyright 1999, 2000, 2001 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -40,7 +40,7 @@ static const char *const reg_dst_table[] = { static int read_memory PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); static int print_indexed_operand - PARAMS ((bfd_vma, struct disassemble_info *, int)); + PARAMS ((bfd_vma, struct disassemble_info *, int*, int)); static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, int)); @@ -68,9 +68,10 @@ read_memory (memaddr, buffer, size, info) /* Read the 68HC12 indexed operand byte and print the corresponding mode. Returns the number of bytes read or -1 if failure. */ static int -print_indexed_operand (memaddr, info, mov_insn) +print_indexed_operand (memaddr, info, indirect, mov_insn) bfd_vma memaddr; struct disassemble_info *info; + int *indirect; int mov_insn; { bfd_byte buffer[4]; @@ -79,6 +80,9 @@ print_indexed_operand (memaddr, info, mov_insn) short sval; int pos = 1; + if (indirect) + *indirect = 0; + status = read_memory (memaddr, &buffer[0], 1, info); if (status != 0) { @@ -140,6 +144,8 @@ print_indexed_operand (memaddr, info, mov_insn) sval = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); (*info->fprintf_func) (info->stream, "[%u,%s]", sval & 0x0ffff, reg_name[reg]); + if (indirect) + *indirect = 1; } else if ((buffer[0] & 0x4) == 0) { @@ -189,6 +195,8 @@ print_indexed_operand (memaddr, info, mov_insn) case 3: default: (*info->fprintf_func) (info->stream, "[D,%s]", reg_name[reg]); + if (indirect) + *indirect = 1; break; } } @@ -440,12 +448,19 @@ print_insn (memaddr, info, arch) /* Analyze the 68HC12 indexed byte. */ if (format & M6812_INDEXED_FLAGS) { - status = print_indexed_operand (memaddr + pos, info, 0); + int indirect; + + status = print_indexed_operand (memaddr + pos, info, &indirect, 0); if (status < 0) { return status; } pos += status; + + /* The indirect addressing mode of the call instruction does + not need the page code. */ + if ((format & M6812_OP_PAGE) && indirect) + format &= ~M6812_OP_PAGE; } /* 68HC12 dbcc/ibcc/tbcc operands. */ @@ -532,6 +547,8 @@ print_insn (memaddr, info, arch) if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) { int val; + bfd_vma addr; + unsigned page = 0; status = read_memory (memaddr + pos + offset, &buffer[0], 2, info); if (status != 0) @@ -546,6 +563,38 @@ print_insn (memaddr, info, arch) val = ((buffer[0] << 8) | (buffer[1] & 0x0FF)); val &= 0x0FFFF; + addr = val; + if (format & M6812_OP_PAGE) + { + status = read_memory (memaddr + pos + offset, buffer, 1, info); + if (status != 0) + return status; + + page = (unsigned) buffer[0]; + if (addr >= M68HC12_BANK_BASE && addr < 0x0c000) + addr = ((val - M68HC12_BANK_BASE) + | (page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + } + else if ((arch & cpu6812) + && addr >= M68HC12_BANK_BASE && addr < 0x0c000) + { + int cur_page; + bfd_vma vaddr; + + if (memaddr >= M68HC12_BANK_VIRT) + cur_page = ((memaddr - M68HC12_BANK_VIRT) + >> M68HC12_BANK_SHIFT); + else + cur_page = 0; + + vaddr = ((addr - M68HC12_BANK_BASE) + + (cur_page << M68HC12_BANK_SHIFT)) + + M68HC12_BANK_VIRT; + if (!info->symbol_at_address_func (addr, info) + && info->symbol_at_address_func (vaddr, info)) + addr = vaddr; + } if (format & M6811_OP_IMM16) { format &= ~M6811_OP_IMM16; @@ -554,13 +603,21 @@ print_insn (memaddr, info, arch) else format &= ~M6811_OP_IND16; - (*info->print_address_func) (val, info); + (*info->print_address_func) (addr, info); + if (format & M6812_OP_PAGE) + { + (* info->fprintf_func) (info->stream, " {"); + (* info->print_address_func) (val, info); + (* info->fprintf_func) (info->stream, ", %d}", page); + format &= ~M6812_OP_PAGE; + pos += 1; + } } if (format & M6812_OP_IDX_P2) { (*info->fprintf_func) (info->stream, ", "); - status = print_indexed_operand (memaddr + pos + offset, info, 1); + status = print_indexed_operand (memaddr + pos + offset, info, 0, 1); if (status < 0) return status; pos += status; @@ -584,6 +641,21 @@ print_insn (memaddr, info, arch) (*info->print_address_func) (val, info); } + if (format & M6812_OP_PAGE) + { + int val; + + status = read_memory (memaddr + pos + offset, &buffer[0], 1, info); + if (status != 0) + { + return status; + } + pos += 1; + + val = buffer[0] & 0x0ff; + (*info->fprintf_func) (info->stream, ", %d", val); + } + #ifdef DEBUG /* Consistency check. 'format' must be 0, so that we have handled all formats; and the computed size of the insn must match the diff --git a/opcodes/m68hc11-opc.c b/opcodes/m68hc11-opc.c index 1e37971..53cb358 100644 --- a/opcodes/m68hc11-opc.c +++ b/opcodes/m68hc11-opc.c @@ -1,6 +1,6 @@ /* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list - Copyright 1999, 2000 Free Software Foundation, Inc. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright 1999, 2000, 2002 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GDB, GAS, and the GNU binutils. @@ -76,6 +76,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. #define OP_IX M6811_OP_IX #define OP_IY M6811_OP_IY #define OP_IND16 M6811_OP_IND16 +#define OP_PAGE M6812_OP_PAGE #define OP_IDX M6812_OP_IDX #define OP_IDX_1 M6812_OP_IDX_1 #define OP_IDX_2 M6812_OP_IDX_2 @@ -83,8 +84,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. #define OP_D_IDX_2 M6812_OP_D_IDX_2 #define OP_DIRECT M6811_OP_DIRECT #define OP_BITMASK M6811_OP_BITMASK -#define OP_JUMP_REL M6811_OP_JUMP_REL -#define OP_JUMP_REL16 M6812_OP_JUMP_REL16 +#define OP_BRANCH M6811_OP_BRANCH +#define OP_JUMP_REL (M6811_OP_JUMP_REL|OP_BRANCH) +#define OP_JUMP_REL16 (M6812_OP_JUMP_REL16|OP_BRANCH) #define OP_REG M6812_OP_REG #define OP_REG_1 M6812_OP_REG #define OP_REG_2 M6812_OP_REG_2 @@ -325,12 +327,18 @@ const struct m68hc11_opcode m68hc11_opcodes[] = { { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 | cpu6812 }, - { "call", OP_IND16, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, - { "call", OP_IDX, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, - { "call", OP_IDX_1, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, - { "call", OP_IDX_2, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, - { "call", OP_D_IDX, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, - { "call", OP_D_IDX_2, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_IND16 | OP_PAGE + | OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX | OP_PAGE + | OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_1 | OP_PAGE + | OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 }, + { "call", OP_IDX_2 | OP_PAGE + | OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX + | OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 }, + { "call", OP_D_IDX_2 + | OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 }, { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 }, { "cba", OP_NONE | OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 }, @@ -564,22 +572,22 @@ const struct m68hc11_opcode m68hc11_opcodes[] = { { "iny", OP_NONE |OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 }, { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 }, - { "jmp", OP_IND16, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 }, { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 }, { "jmp", OP_IY | OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 }, - { "jmp", OP_IND16, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, + { "jmp", OP_IND16 | OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 }, { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 }, { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 }, { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 }, { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 }, { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 }, - { "jsr", OP_DIRECT, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, - { "jsr", OP_IND16, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 }, { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 }, { "jsr", OP_IY | OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 }, - { "jsr", OP_DIRECT, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, - { "jsr", OP_IND16, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, + { "jsr", OP_DIRECT | OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 }, + { "jsr", OP_IND16 | OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 }, { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 }, { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 }, { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 }, diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c index d575088..12c0b94 100644 --- a/opcodes/m68k-dis.c +++ b/opcodes/m68k-dis.c @@ -46,7 +46,7 @@ static int print_insn_arg PARAMS ((const char *, unsigned char *, unsigned char *, bfd_vma, disassemble_info *)); -CONST char * CONST fpcr_names[] = { +const char * const fpcr_names[] = { "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" }; @@ -478,7 +478,7 @@ print_insn_arg (d, buffer, p0, addr, info) register int place = d[1]; register unsigned char *p = p0; int regno; - register CONST char *regname; + register const char *regname; register unsigned char *p1; double flval; int flt_p; diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 661c179..9b35a47 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -284,6 +284,53 @@ print_insn_arg (d, l, pc, info) (l >> OP_SH_SEL) & OP_MASK_SEL); break; + case 'O': + (*info->fprintf_func) (info->stream, "%d", + (l >> OP_SH_ALN) & OP_MASK_ALN); + break; + + case 'Q': + { + unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; + if ((vsel & 0x10) == 0) + { + int fmt; + vsel &= 0x0f; + for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) + if ((vsel & 1) == 0) + break; + (*info->fprintf_func) (info->stream, "$v%d[%d]", + (l >> OP_SH_FT) & OP_MASK_FT, + vsel >> 1); + } + else if ((vsel & 0x08) == 0) + { + (*info->fprintf_func) (info->stream, "$v%d", + (l >> OP_SH_FT) & OP_MASK_FT); + } + else + { + (*info->fprintf_func) (info->stream, "0x%x", + (l >> OP_SH_FT) & OP_MASK_FT); + } + } + break; + + case 'X': + (*info->fprintf_func) (info->stream, "$v%d", + (l >> OP_SH_FD) & OP_MASK_FD); + break; + + case 'Y': + (*info->fprintf_func) (info->stream, "$v%d", + (l >> OP_SH_FS) & OP_MASK_FS); + break; + + case 'Z': + (*info->fprintf_func) (info->stream, "$v%d", + (l >> OP_SH_FT) & OP_MASK_FT); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, @@ -365,7 +412,7 @@ mips_isa_type (mach, isa, cputype) break; case bfd_mach_mips16: *cputype = CPU_MIPS16; - *isa = ISA_MIPS3; + *isa = ISA_MIPS3 | INSN_MIPS16; break; case bfd_mach_mips5: *cputype = CPU_MIPS5; @@ -378,16 +425,16 @@ mips_isa_type (mach, isa, cputype) case bfd_mach_mipsisa32: *cputype = CPU_MIPS32; /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. - Note that MIPS-3D is not applicable to MIPS32. (See _MIPS32 - Architecture For Programmers Volume I: Introduction to the + Note that MIPS-3D and MDMX are not applicable to MIPS32. (See + _MIPS32 Architecture For Programmers Volume I: Introduction to the MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), page 1. */ - *isa = ISA_MIPS32; + *isa = ISA_MIPS32 | INSN_MIPS16; break; case bfd_mach_mipsisa64: *cputype = CPU_MIPS64; /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ - *isa = ISA_MIPS64 | INSN_MIPS3D; + *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX; break; default: diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 4b8cbc7..6e8adc5 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -4,7 +4,7 @@ Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc. - MIPS-3D support added by Broadcom Corporation (SiByte). + MIPS-3D and MDMX support added by Broadcom Corporation (SiByte). This file is part of GDB, GAS, and the GNU binutils. @@ -75,6 +75,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define IS_M INSN_MULT +#define WR_MACC INSN_WRITE_MDMX_ACC +#define RD_MACC INSN_READ_MDMX_ACC + #define I1 INSN_ISA1 #define I2 INSN_ISA2 #define I3 INSN_ISA3 @@ -84,8 +87,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define I64 INSN_ISA64 /* MIPS64 MIPS-3D ASE support. */ +#define I16 INSN_MIPS16 + +/* MIPS64 MIPS-3D ASE support. */ #define M3D INSN_MIPS3D +/* MIPS64 MDMX ASE support. */ +#define MX INSN_MDMX + #define P3 INSN_4650 #define L1 INSN_4010 #define V1 INSN_4100 @@ -144,15 +153,27 @@ const struct mips_opcode mips_builtin_opcodes[] = {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 }, {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 }, {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, +{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 }, +{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX }, {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 }, +{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX }, {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 }, +{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 }, /* b is at the top of the table. */ /* bal is at the top of the table. */ @@ -256,8 +277,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, @@ -316,8 +339,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, @@ -328,8 +353,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, +{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 }, {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, +{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX }, {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, @@ -453,7 +480,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 }, {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 }, -{"dla", "t,o(b)", 0x64000000, 0xfc000000, WR_t|RD_s, I3 }, /* daddiu */ {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 }, {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */ {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */ @@ -544,10 +570,7 @@ const struct mips_opcode mips_builtin_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 }, - /* jalx really should only be avaliable if mips16 is available, - but for now make it I1. */ -{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 }, -{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */ +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 }, {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 }, {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 }, {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 }, @@ -626,6 +649,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 }, +{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, @@ -638,28 +663,39 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 }, +{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 }, {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 }, {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 }, {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32}, {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, +{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, +{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 }, {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, +{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, +{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 }, {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 }, +{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, +{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 }, {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 }, {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 }, {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 }, {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 }, {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 }, +{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, +{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 }, {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 }, {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 }, /* move is at the top of the table. */ +{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 }, {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 }, {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 }, @@ -681,15 +717,25 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 }, {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3 }, {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 }, {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 }, +{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, +{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 }, {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 }, {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 }, {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 }, {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, +{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, +{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 }, @@ -708,19 +754,32 @@ const struct mips_opcode mips_builtin_opcodes[] = /* nop is at the start of the table. */ {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 }, +{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/ {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 }, +{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 }, - +{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 }, +{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1 }, +{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 }, +{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, - /* pref and prefx are at the start of the table. */ - {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, - +{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, +{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, +{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, +{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, +{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 }, +{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX }, {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, @@ -737,6 +796,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 }, {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 }, {"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 }, +{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, +{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, +{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, +{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, +{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, +{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 }, {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 }, @@ -754,6 +819,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D }, {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D }, +{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, +{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 }, +{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, @@ -798,6 +866,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 }, {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 }, +{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 }, {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 }, {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 }, @@ -805,6 +883,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */ {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 }, +{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 }, {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 }, @@ -819,16 +899,25 @@ const struct mips_opcode mips_builtin_opcodes[] = {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, +{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */ {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 }, +{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, /* ssnop is at the start of the table. */ {"standby", "", 0x42000021, 0xffffffff, 0, V1 }, {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, +{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, +{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 }, {"suspend", "", 0x42000022, 0xffffffff, 0, V1 }, @@ -917,13 +1006,20 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 }, {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 }, {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 }, -{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, -{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, -{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, +{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 }, +{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX }, +{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 }, +{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX }, {"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 }, {"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32 }, {"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 }, {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 }, +{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, +{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 }, +{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 }, +{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX }, +{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the diff --git a/opcodes/or32-dis.c b/opcodes/or32-dis.c index 8876a30..d5f4679 100644 --- a/opcodes/or32-dis.c +++ b/opcodes/or32-dis.c @@ -261,7 +261,7 @@ print_insn (memaddr, info) /* The four bytes of the instruction. */ unsigned long insn; find_byte_func_type find_byte_func = (find_byte_func_type)info->private_data; - struct or32_opcode CONST * opcode; + struct or32_opcode const * opcode; { int status = diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index 0cb531b..1f85d72 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -18,6 +18,7 @@ d30v-dis.c d30v-opc.c dis-buf.c disassemble.c +dlx-dis.c fr30-asm.c fr30-desc.c fr30-desc.h @@ -25,6 +26,13 @@ fr30-dis.c fr30-ibld.c fr30-opc.c fr30-opc.h +frv-asm.c +frv-desc.c +frv-desc.h +frv-dis.c +frv-ibld.c +frv-opc.c +frv-opc.h h8300-dis.c h8500-dis.c h8500-opc.h @@ -46,6 +54,13 @@ ia64-opc-i.c ia64-opc-m.c ia64-opc.c ia64-opc.h +ip2k-asm.c +ip2k-desc.c +ip2k-desc.h +ip2k-dis.c +ip2k-ibld.c +ip2k-opc.c +ip2k-opc.h m10200-dis.c m10200-opc.c m10300-dis.c diff --git a/opcodes/po/es.po b/opcodes/po/es.po index a423506..4ee0c99 100644 --- a/opcodes/po/es.po +++ b/opcodes/po/es.po @@ -1,12 +1,12 @@ -# Mensajes en español para opcodes-2.12-pre020121 +# Mensajes en español para opcodes-2.12.91 # Copyright (C) 2002 Free Software Foundation, Inc. # Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002. # msgid "" msgstr "" -"Project-Id-Version: opcodes 2.12-pre020121\n" -"POT-Creation-Date: 2002-01-17 13:58+0000\n" -"PO-Revision-Date: 2002-01-24 08:55-0600\n" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-07-24 02:03-0500\n" "Last-Translator: Cristian Othón Martínez Vera <cfuga@itam.mx>\n" "Language-Team: Spanish <es@li.org>\n" "MIME-Version: 1.0\n" @@ -25,21 +25,21 @@ msgstr "pista de salto sin alinear" msgid "Illegal limm reference in last instruction!\n" msgstr "¡Referencia limm ilegal en la última instrucción!\n" -#: arm-dis.c:509 +#: arm-dis.c:507 msgid "<illegal precision>" msgstr "<precisión ilegal>" -#: arm-dis.c:1019 +#: arm-dis.c:1010 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Conjunto de nombres de registro no reconocido: %s\n" -#: arm-dis.c:1026 +#: arm-dis.c:1017 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Opción de desensamblador no reconocida: %s\n" -#: arm-dis.c:1198 +#: arm-dis.c:1191 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -62,7 +62,8 @@ msgstr "Error interno del desensamblador" msgid "unknown constraint `%c'" msgstr "restricción `%c' desconocida" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "operando fuera de rango (%ld no está entre %ld y %ld)" @@ -88,106 +89,126 @@ msgstr "Error desconocido %d\n" msgid "Address 0x%x is out of bounds.\n" msgstr "La dirección 0x%x está fuera de los límites.\n" -#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "No se reconoció el campo %d durante la decodificación.\n" -#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 msgid "missing mnemonic in syntax string" msgstr "falta el mnemónico en la cadena sintáctica" #. We couldn't parse it. -#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 -#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 -#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 msgid "unrecognized instruction" msgstr "instrucción no reconocida" -#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "error sintáctico (se esperaba el carácter `%c', se encontró `%c')" -#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "error sintáctico (se esperaba el carácter `%c', se encontró el final de la instrucción)" -#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 msgid "junk at end of line" msgstr "basura al final de la línea" -#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 msgid "unrecognized form of instruction" msgstr "forma de instrucción no reconocida" -#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 #, c-format msgid "bad instruction `%.50s...'" msgstr "instrucción errónea `%.50s...'" -#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 #, c-format msgid "bad instruction `%.50s'" msgstr "instrucción errónea `%.50s'" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 msgid "*unknown*" msgstr "*desconocida*" -#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "No se reconoció el campo %d al mostrar insn.\n" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "operando fuera de rango (%ld no está entre %ld y %lu)" -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "operando fuera de rango (%lu no está entre 0 y %lu)" -#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "No se reconoció el campo %d al construir insn.\n" -#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "No se reconoció el campo %d al decodificar insn.\n" -#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "No se reconoció el campo %d al obtener el operando int.\n" -#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "No se reconoció el campo %d al obtener el operando vma.\n" -#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "No se reconoció el campo %d al establecer el operando int.\n" -#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "No se reconoció el campo %d al establecer el operando vma.\n" -#: h8300-dis.c:384 +#: h8300-dis.c:385 #, c-format msgid "Hmmmm %x" msgstr "Hmmmm %x" -#: h8300-dis.c:395 +#: h8300-dis.c:396 #, c-format msgid "Don't understand %x \n" msgstr "No se entiende %x \n" @@ -237,12 +258,12 @@ msgstr "<código de función %d>" msgid "# <dis error: %08x>" msgstr "# <error de desensamblador: %08x>" -#: mips-dis.c:290 +#: mips-dis.c:337 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "# error interno, modificador(%c) sin definir" -#: mips-dis.c:1154 +#: mips-dis.c:1209 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "# error interno del desensamblador, modificador (%c) no reconocido" @@ -276,62 +297,62 @@ msgstr "*tipo de operandos operandos desconocido: %d*" msgid "$<undefined>" msgstr "$<sin definir>" -#: ppc-opc.c:765 ppc-opc.c:798 +#: ppc-opc.c:777 ppc-opc.c:810 msgid "invalid conditional option" msgstr "opción condicional inválida" -#: ppc-opc.c:800 +#: ppc-opc.c:812 msgid "attempt to set y bit when using + or - modifier" msgstr "intento de establecer el bit y cuando se usaba el modificador + ó -" -#: ppc-opc.c:832 ppc-opc.c:884 +#: ppc-opc.c:844 ppc-opc.c:896 msgid "offset not a multiple of 4" msgstr "el desplazamiento no es un múltiplo de 4" -#: ppc-opc.c:857 +#: ppc-opc.c:869 msgid "offset not between -2048 and 2047" msgstr "el desplazamiento no está entre -2048 y 2047" -#: ppc-opc.c:882 +#: ppc-opc.c:894 msgid "offset not between -8192 and 8191" msgstr "el desplazamiento no está entre -8192 y 8191" -#: ppc-opc.c:910 +#: ppc-opc.c:922 msgid "ignoring least significant bits in branch offset" msgstr "ignorando los bits menos significativos en el desplazamiento de la rama" -#: ppc-opc.c:944 ppc-opc.c:981 +#: ppc-opc.c:956 ppc-opc.c:993 msgid "illegal bitmask" msgstr "máscara de bits ilegal" -#: ppc-opc.c:1054 +#: ppc-opc.c:1066 msgid "value out of range" msgstr "valor fuera de rango" -#: ppc-opc.c:1130 +#: ppc-opc.c:1142 msgid "index register in load range" msgstr "registro índice en el rango de carga" -#: ppc-opc.c:1146 +#: ppc-opc.c:1158 msgid "invalid register operand when updating" msgstr "operando de registro inválido mientras se actualizaba" #. Mark as non-valid instruction -#: sparc-dis.c:749 +#: sparc-dis.c:750 msgid "unknown" msgstr "desconocida" -#: sparc-dis.c:824 +#: sparc-dis.c:825 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:835 +#: sparc-dis.c:836 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Error interno: sparc-opcode.h erróneo: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:884 +#: sparc-dis.c:885 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "Error interno: sparc-opcode.h erróneo: \"%s\" == \"%s\"\n" @@ -395,5 +416,33 @@ msgstr "el valor inmediato no está en rango y no es par" msgid "immediate value must be even" msgstr "el valor inmediato debe ser par" +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "Registro erróneo en el preincremento" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Registro erróneo en el postincremento" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Nombre de registro erróneo" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "La etiqueta tiene conflictos con el nombre de registro" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "La etiqueta tiene conflictos con `Rx'" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Expresión inmediata errónea" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "El operando small no era un número inmediato" + #~ msgid "unrecognized keyword/register name" #~ msgstr "nombre clave/de registro no reconocido" diff --git a/opcodes/po/fr.po b/opcodes/po/fr.po index e1806b0..b0ff20e 100644 --- a/opcodes/po/fr.po +++ b/opcodes/po/fr.po @@ -1,12 +1,12 @@ # Messages français pour opcodes. -# Copyright (C) 1996 Free Software Foundation, Inc. -# Michel Robitaille <robitail@IRO.UMontreal.CA>, 1996. +# Copyright © 1996 Free Software Foundation, Inc. +# Michel Robitaille <robitail@IRO.UMontreal.CA>, traducteur depuis/since 1996. # msgid "" msgstr "" -"Project-Id-Version: opcodes 2.12-pre020121\n" -"POT-Creation-Date: 2002-01-17 13:58+0000\n" -"PO-Revision-Date: 2002-03-17 20:00-0500\n" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-07-24 08:00-0500\n" "Last-Translator: Michel Robitaille <robitail@IRO.UMontreal.CA>\n" "Language-Team: French <traduc@traduc.org>\n" "MIME-Version: 1.0\n" @@ -25,21 +25,21 @@ msgstr "saut indicé non aligné" msgid "Illegal limm reference in last instruction!\n" msgstr "Référence limite illégale dans la dernière instruction!\n" -#: arm-dis.c:509 +#: arm-dis.c:507 msgid "<illegal precision>" msgstr "<précision illégale>" -#: arm-dis.c:1019 +#: arm-dis.c:1010 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Nom de jeu de registres inconnu: %s\n" -#: arm-dis.c:1026 +#: arm-dis.c:1017 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Option du désassembleur non reconnue: %s\n" -#: arm-dis.c:1198 +#: arm-dis.c:1191 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -62,7 +62,8 @@ msgstr "Erreur interne du désassembleur" msgid "unknown constraint `%c'" msgstr "contrainte inconnue « %c »" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "opérande hors gamme (%ld n'est pas entre %ld et %ld)" @@ -88,105 +89,127 @@ msgstr "Erreur inconnue %d\n" msgid "Address 0x%x is out of bounds.\n" msgstr "Adresse 0x%x est hors gamme.\n" -#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "Champ non reconnu %d lors de l'analyse.\n" -#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 msgid "missing mnemonic in syntax string" msgstr "mnémonique manquante dans la syntaxe de la chaîne" #. We couldn't parse it. -#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 msgid "unrecognized instruction" msgstr "instruction non reconnue" -#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "erreur de syntaxe (caractère « %c » attendu, « %c » obtenu)" -#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "erreur de syntaxe (caractère « %c » attendu, fin de l'instruction obtenue)" -#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 msgid "junk at end of line" msgstr "rebut à la fin de la ligne" -#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 msgid "unrecognized form of instruction" msgstr "forme d'instruction non reconnue" -#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 #, c-format msgid "bad instruction `%.50s...'" msgstr "instruction erronée « %.50s... »" -#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 #, c-format msgid "bad instruction `%.50s'" msgstr "instruction erronée « %.50s »" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 msgid "*unknown*" msgstr "*inconnu*" -#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "Champ non reconnu %d lors de l'impression insn.\n" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "opérande hors gamme (%ld n'est pas entre %ld et %lu)" -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "opérande hors gamme (%lu n'est pas entre 0 et %lu)" -#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "Champ non reconnu %d lors de la construction de insn.\n" -#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "Champ non reconnu %d lors du décodage de insn.\n" -#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "Champ non reconnu %d lors de la prise d'une opérande int.\n" -#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "Champ non reconnu %d lors de la prise d'une opérande vma.\n" -#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande int.\n" -#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "Champ non reconnu %d lors de l'initialisation d'une opérande vma.\n" # h8300-dis.c:380Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" -#: h8300-dis.c:384 +#: h8300-dis.c:385 #, c-format msgid "Hmmmm %x" msgstr "Hummm %x" -#: h8300-dis.c:395 +#: h8300-dis.c:396 #, c-format msgid "Don't understand %x \n" msgstr "Ne comprend pas %x \n" @@ -236,12 +259,12 @@ msgstr "<code de fonction %d>" msgid "# <dis error: %08x>" msgstr "# <erreur du désassembleur: %08x>" -#: mips-dis.c:290 +#: mips-dis.c:337 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "# erreur interne, modificateur non défini(%c)" -#: mips-dis.c:1154 +#: mips-dis.c:1209 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "# erreur interne du déssassembleur, modificateur non reconnu(%c)" @@ -275,62 +298,62 @@ msgstr "*type d'opérande inconnue: %d*" msgid "$<undefined>" msgstr "$<non défini>" -#: ppc-opc.c:765 ppc-opc.c:798 +#: ppc-opc.c:777 ppc-opc.c:810 msgid "invalid conditional option" msgstr "option conditionnelle invalide" -#: ppc-opc.c:800 +#: ppc-opc.c:812 msgid "attempt to set y bit when using + or - modifier" msgstr "tentative d'initialisation du bit y lorsque le modificateur + ou - a été utilisé" -#: ppc-opc.c:832 ppc-opc.c:884 +#: ppc-opc.c:844 ppc-opc.c:896 msgid "offset not a multiple of 4" msgstr "décalage n'est pas un multiple de 4" -#: ppc-opc.c:857 +#: ppc-opc.c:869 msgid "offset not between -2048 and 2047" msgstr "décalage n'est pas entre -2048 et 2047" -#: ppc-opc.c:882 +#: ppc-opc.c:894 msgid "offset not between -8192 and 8191" msgstr "décalage n'est pas entre -8192 et 8191" -#: ppc-opc.c:910 +#: ppc-opc.c:922 msgid "ignoring least significant bits in branch offset" msgstr "Les derniers bits les moins significatifs sont ignorés dans le décalage de branchement" -#: ppc-opc.c:944 ppc-opc.c:981 +#: ppc-opc.c:956 ppc-opc.c:993 msgid "illegal bitmask" msgstr "masque de bits illégal" -#: ppc-opc.c:1054 +#: ppc-opc.c:1066 msgid "value out of range" msgstr "valeur hors gamme" -#: ppc-opc.c:1130 +#: ppc-opc.c:1142 msgid "index register in load range" msgstr "registre index n'est pas dans la plage de chargement" -#: ppc-opc.c:1146 +#: ppc-opc.c:1158 msgid "invalid register operand when updating" msgstr "opérande registre invalide lors de la mise à jour" #. Mark as non-valid instruction -#: sparc-dis.c:749 +#: sparc-dis.c:750 msgid "unknown" msgstr "inconnu" -#: sparc-dis.c:824 +#: sparc-dis.c:825 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Erreur interne: sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n" -#: sparc-dis.c:835 +#: sparc-dis.c:836 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Erreur interne: sparc-opcode.h erroné: « %s », %#.8lx, %#.8lx\n" -#: sparc-dis.c:884 +#: sparc-dis.c:885 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "Erreur interne: sparc-opcode.h erroné: « %s » == « %s »\n" @@ -356,31 +379,31 @@ msgstr "La valeur de déplacement est hors gamme et n'est pas alignée." #: v850-opc.c:69 msgid "displacement value is out of range" -msgstr "La valeur de déplacement est hors gamme." +msgstr "valeur de déplacement est hors gamme" #: v850-opc.c:70 msgid "displacement value is not aligned" -msgstr "La valeur de déplacement n'est pas alignée." +msgstr "valeur de déplacement n'est pas alignée" #: v850-opc.c:72 msgid "immediate value is out of range" -msgstr "La valeur immédiate est hors gamme." +msgstr "valeur immédiate est hors gamme" #: v850-opc.c:83 msgid "branch value not in range and to odd offset" -msgstr "Valeur de branchement est hors gamme et a un décalage impair." +msgstr "valeur de branchement est hors gamme et a un décalage impair" #: v850-opc.c:85 v850-opc.c:117 msgid "branch value out of range" -msgstr "Valeur de branchement hors gamme." +msgstr "valeur de branchement hors gamme" #: v850-opc.c:88 v850-opc.c:120 msgid "branch to odd offset" -msgstr "Branchement avec un décalage impair." +msgstr "Branchement avec un décalage impair" #: v850-opc.c:115 msgid "branch value not in range and to an odd offset" -msgstr "Valeur de branchement est hors gamme et a un décalage impair" +msgstr "valeur de branchement est hors gamme et a un décalage impair" #: v850-opc.c:346 msgid "invalid register for stack adjustment" @@ -388,11 +411,39 @@ msgstr "registre invalide pour un ajustement de la pile" #: v850-opc.c:370 msgid "immediate value not in range and not even" -msgstr "La valeur immédiate est hors gamme et est impaire." +msgstr "valeur immédiate est hors gamme et est impaire" #: v850-opc.c:375 msgid "immediate value must be even" -msgstr "La valeur immédiate doit être paire." +msgstr "valeur immédiate doit être paire" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "Registre erroné dans un préincrément" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Registre erroné dans un postincrément" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Nom erroné de registre" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "Conflits d'étiquette avec le nom de registre" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "Conflit d'étiquette avec « Rx »" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Expression immédiate erronée" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "Petite opérande n'était pas un nombre immédiat" #~ msgid "unrecognized keyword/register name" #~ msgstr "nom de mot clé ou de registre non reconnu" diff --git a/opcodes/po/id.po b/opcodes/po/id.po index 3c69b4b..3edf294 100644 --- a/opcodes/po/id.po +++ b/opcodes/po/id.po @@ -1,12 +1,12 @@ -# opcodes 2.12-pre020121 (Indonesian) +# opcodes 2.12.1 (Indonesian) # Copyright (C) 2002 Free Software Foundation, Inc. # Tedi Heriyanto <tedi_h@gmx.net>, 2002. # msgid "" msgstr "" -"Project-Id-Version: opcodes 2.12-pre020121\n" -"POT-Creation-Date: 2002-01-17 13:58+0000\n" -"PO-Revision-Date: 2002-04-02 08:20GMT+0700\n" +"Project-Id-Version: opcodes 2.12.1\n" +"POT-Creation-Date: 2002-02-08 03:24-0200\n" +"PO-Revision-Date: 2002-07-23 12:35GMT+0700\n" "Last-Translator: Tedi Heriyanto <tedi_h@gmx.net>\n" "Language-Team: Indonesian <translation-team-id@lists.sourceforge.net>\n" "MIME-Version: 1.0\n" @@ -26,21 +26,21 @@ msgstr "petunjuk lompat tidak rata" msgid "Illegal limm reference in last instruction!\n" msgstr "referensi limm ilegal dalam instruksi terakhir!\n" -#: arm-dis.c:509 +#: arm-dis.c:502 msgid "<illegal precision>" msgstr "<presisi ilegal>" -#: arm-dis.c:1019 +#: arm-dis.c:1012 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Set nama register tidak dikenal: %s\n" -#: arm-dis.c:1026 +#: arm-dis.c:1019 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Option disasembler tidak dikenal: %s\n" -#: arm-dis.c:1198 +#: arm-dis.c:1191 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -63,7 +63,7 @@ msgstr "Kesalahan disasembler internal" msgid "unknown constraint `%c'" msgstr "konstrain tidak dikenal `%c'" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "operand keluar batas (%ld tidak antara %ld dan %ld)" @@ -89,94 +89,94 @@ msgstr "Kesalahan tidak dikenal %d\n" msgid "Address 0x%x is out of bounds.\n" msgstr "Alamat 0x%x di luar batas.\n" -#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "Field tidak dikenal %d saat parsing.\n" -#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281 msgid "missing mnemonic in syntax string" msgstr "mnemonik hilang dalam string sintaks" #. We couldn't parse it. -#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 msgid "unrecognized instruction" msgstr "instruksti tidak dikenal" -#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan `%c')" -#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "kesalahan sintaks (diharapkan karakter `%c', ditemukan akhir instruksi)" -#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502 msgid "junk at end of line" msgstr "sampah di akhir baris" -#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609 msgid "unrecognized form of instruction" msgstr "bentuk instruksi tidak dikenal" -#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621 #, c-format msgid "bad instruction `%.50s...'" msgstr "instruksi buruk `%.50s...'" -#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624 #, c-format msgid "bad instruction `%.50s'" msgstr "instruksi buruk `%.50s'" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 xstormy16-dis.c:39 msgid "*unknown*" msgstr "*tidak dikenal*" -#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "Field tidak dikenal %d saat mencetak insn.\n" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "operand di luar batas (%ld tidak antara %ld dan %lu)" -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "operand di luar batas (%lu tidak antara 0 dan %lu)" -#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "Field tidak dikenal %d saat membuild insn.\n" -#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "Field tidak dikenal %d saat mendekode insn.\n" -#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "Field tidak dikenal %d saat memperoleh operand int.\n" -#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "Field tidak dikenal %d saat memperoleh operand vma.\n" -#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "Field tidak dikenal %d saat menset operand int.\n" -#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "Field tidak dikenal %d saat menset operand vma.\n" @@ -316,21 +316,21 @@ msgid "invalid register operand when updating" msgstr "operand register tidak valid saat mengupdate" #. Mark as non-valid instruction -#: sparc-dis.c:749 +#: sparc-dis.c:750 msgid "unknown" msgstr "tidak dikenal" -#: sparc-dis.c:824 +#: sparc-dis.c:825 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:835 +#: sparc-dis.c:836 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:884 +#: sparc-dis.c:885 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "Kesalahan internal: sparc-opcode.h buruk: \"%s\" == \"%s\"\n" @@ -393,3 +393,31 @@ msgstr "nilai langsung tidak dalam jangkauan dan tidak genap" #: v850-opc.c:375 msgid "immediate value must be even" msgstr "nilai langsung harus genap" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "register buruk dalam preinkremen" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Register buruk dalam pascainkremen" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Nama register buruk" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "Label konflik dengan nama register" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "Label konflik dengan `Rx'" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Ekspresi langsung yang buruk" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "Operand kecil bukan sebuah angka immediate" diff --git a/opcodes/po/pt_BR.po b/opcodes/po/pt_BR.po new file mode 100644 index 0000000..c2663d3 --- /dev/null +++ b/opcodes/po/pt_BR.po @@ -0,0 +1,445 @@ +# opcodes: translation to Brazilian Portuguese (pt_BR) +# Copyright (C) 2002 Free Software Foundation, Inc. +# Alexandre Folle de Menezes <afmenez@terra.com.br>, 2002. +# +msgid "" +msgstr "" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-07-24 04:00-0300\n" +"Last-Translator: Alexandre Folle de Menezes <afmenez@terra.com.br>\n" +"Language-Team: Brazilian Portuguese <ldp-br@bazar.conectiva.com.br>\n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=ISO-8859-1\n" +"Content-Transfer-Encoding: 8-bit\n" + +#: alpha-opc.c:335 +msgid "branch operand unaligned" +msgstr "operando de desvio desalinhado" + +#: alpha-opc.c:358 alpha-opc.c:380 +msgid "jump hint unaligned" +msgstr "dica de salto desalinhada" + +#: arc-dis.c:52 +msgid "Illegal limm reference in last instruction!\n" +msgstr "Referência limm ilegal na última instrução!\n" + +#: arm-dis.c:507 +msgid "<illegal precision>" +msgstr "<precisão ilegal>" + +#: arm-dis.c:1010 +#, c-format +msgid "Unrecognised register name set: %s\n" +msgstr "Conjunto de nomes de registrador desconhecido: %s\n" + +#: arm-dis.c:1017 +#, c-format +msgid "Unrecognised disassembler option: %s\n" +msgstr "Opção do desmontador desconhecida: %s\n" + +#: arm-dis.c:1191 +msgid "" +"\n" +"The following ARM specific disassembler options are supported for use with\n" +"the -M switch:\n" +msgstr "" +"\n" +"As opções do desmontador espcíficas para ARM a seguir não são suportadas para\n" +"uso com a opção -M:\n" + +#: avr-dis.c:118 avr-dis.c:128 +msgid "undefined" +msgstr "indefinido" + +#: avr-dis.c:180 +msgid "Internal disassembler error" +msgstr "Erro interno do desmontador" + +#: avr-dis.c:228 +#, c-format +msgid "unknown constraint `%c'" +msgstr "restrição `%c' desconhecida" + +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 +#, c-format +msgid "operand out of range (%ld not between %ld and %ld)" +msgstr "operando fora de faixa (%ld não está entre %ld e %ld)" + +#: cgen-asm.c:367 +#, c-format +msgid "operand out of range (%lu not between %lu and %lu)" +msgstr "operando fora de faixa (%lu não está entre %lu e %lu)" + +#: d30v-dis.c:312 +#, c-format +msgid "<unknown register %d>" +msgstr "<registrador %d desconhecido>" + +#. Can't happen. +#: dis-buf.c:57 +#, c-format +msgid "Unknown error %d\n" +msgstr "Erro %d desconhecido\n" + +#: dis-buf.c:62 +#, c-format +msgid "Address 0x%x is out of bounds.\n" +msgstr "Endereço 0x%x está fora dos limites.\n" + +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 +#, c-format +msgid "Unrecognized field %d while parsing.\n" +msgstr "Campo %d desconhecido durante análise.\n" + +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 +msgid "missing mnemonic in syntax string" +msgstr "mnemônico faltando na string de sintaxe" + +#. We couldn't parse it. +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 +msgid "unrecognized instruction" +msgstr "instrução não reconhecida" + +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 +#, c-format +msgid "syntax error (expected char `%c', found `%c')" +msgstr "erro de sintaxe (esperado char `%c', encontrado `%c')" + +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "erro de sintaxe (esperado char `%c', encontrado fim de instrução)" + +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 +msgid "junk at end of line" +msgstr "lixo no final do arquivo" + +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 +msgid "unrecognized form of instruction" +msgstr "forma de instrução não reconhecida" + +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 +#, c-format +msgid "bad instruction `%.50s...'" +msgstr "instrução `%.50s...' errada" + +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 +#, c-format +msgid "bad instruction `%.50s'" +msgstr "instrução `%.50s' errada" + +#. Default text to print if an instruction isn't recognized. +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 +msgid "*unknown*" +msgstr "*desconecida*" + +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 +#, c-format +msgid "Unrecognized field %d while printing insn.\n" +msgstr "Campo %d não reconhecido durante impressão de insn.\n" + +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "operando fora de faixa (%ld não está entre %ld e %lu)" + +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 +#, c-format +msgid "operand out of range (%lu not between 0 and %lu)" +msgstr "operando fora de faixa (%lu não está entre 0 e %lu)" + +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 +#, c-format +msgid "Unrecognized field %d while building insn.\n" +msgstr "Campo %d não reconhecido durante construção de insn.\n" + +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 +#, c-format +msgid "Unrecognized field %d while decoding insn.\n" +msgstr "Campo %d não reconhecido durante decodificação de insn.\n" + +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 +#, c-format +msgid "Unrecognized field %d while getting int operand.\n" +msgstr "Campo %d não reconhecido ao obter operando int.\n" + +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 +#, c-format +msgid "Unrecognized field %d while getting vma operand.\n" +msgstr "Campo %d não reconhecido ao obter operando vma.\n" + +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 +#, c-format +msgid "Unrecognized field %d while setting int operand.\n" +msgstr "Campo %d não reconhecido ao definir operando int.\n" + +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 +#, c-format +msgid "Unrecognized field %d while setting vma operand.\n" +msgstr "Campo %d não reconhecido ao definir operando vma.\n" + +#: h8300-dis.c:385 +#, c-format +msgid "Hmmmm %x" +msgstr "Hmmmm %x" + +#: h8300-dis.c:396 +#, c-format +msgid "Don't understand %x \n" +msgstr "Não entendo %x \n" + +#: h8500-dis.c:143 +#, c-format +msgid "can't cope with insert %d\n" +msgstr "impossível lidar com insert %d\n" + +#. Couldn't understand anything. +#: h8500-dis.c:350 +#, c-format +msgid "%02x\t\t*unknown*" +msgstr "%02x\t\t*desconhecido*" + +#: i386-dis.c:1649 +msgid "<internal disassembler error>" +msgstr "<erro interno do desmontador>" + +#: m10200-dis.c:199 +#, c-format +msgid "unknown\t0x%02x" +msgstr "desconhecido\t0x%02x" + +#: m10200-dis.c:339 +#, c-format +msgid "unknown\t0x%04lx" +msgstr "desconhecido\t0x%04lx" + +#: m10300-dis.c:685 +#, c-format +msgid "unknown\t0x%04x" +msgstr "desconhecido\t0x%04x" + +#: m68k-dis.c:429 +#, c-format +msgid "<internal error in opcode table: %s %s>\n" +msgstr "<erro interno na tabela de códigos de operação: %s %s>\n" + +#: m68k-dis.c:1007 +#, c-format +msgid "<function code %d>" +msgstr "<código de função %d>" + +#: m88k-dis.c:255 +#, c-format +msgid "# <dis error: %08x>" +msgstr "# <erro de desmontador: %08x>" + +#: mips-dis.c:337 +#, c-format +msgid "# internal error, undefined modifier(%c)" +msgstr "# erro interno, modificador (%c) indefinido" + +#: mips-dis.c:1209 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "# erro interno do desmontador, modificador (%c) não reconhecido" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "Case %d errado (%s) em %s:%d\n" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "Interno: Código não depurado (test-case faltando): %s:%d" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "(desconhecido)" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "*tipo de operandos desconhecidos: %d*" + +#. I and Z are output operands and can`t be immediate +#. * A is an address and we can`t have the address of +#. * an immediate either. We don't know how much to increase +#. * aoffsetp by since whatever generated this is broken +#. * anyway! +#. +#: ns32k-dis.c:628 +msgid "$<undefined>" +msgstr "$<indefinido>" + +#: ppc-opc.c:777 ppc-opc.c:810 +msgid "invalid conditional option" +msgstr "opção condicional inválida" + +#: ppc-opc.c:812 +msgid "attempt to set y bit when using + or - modifier" +msgstr "tentativa de setar bit y ao usar modificador + ou -" + +#: ppc-opc.c:844 ppc-opc.c:896 +msgid "offset not a multiple of 4" +msgstr "deslocamento não é um múltiplo de 4" + +#: ppc-opc.c:869 +msgid "offset not between -2048 and 2047" +msgstr "deslocamento não está entre -2048 and 2047" + +#: ppc-opc.c:894 +msgid "offset not between -8192 and 8191" +msgstr "deslocamento não está entre -8192 and 8191" + +#: ppc-opc.c:922 +msgid "ignoring least significant bits in branch offset" +msgstr "ignorando os bits menos significatiovs no deslocamento do desvio" + +#: ppc-opc.c:956 ppc-opc.c:993 +msgid "illegal bitmask" +msgstr "máscara de bits ilegal" + +#: ppc-opc.c:1066 +msgid "value out of range" +msgstr "valor fora de faixa" + +#: ppc-opc.c:1142 +msgid "index register in load range" +msgstr "registrador de índice na faixa de carregamento" + +#: ppc-opc.c:1158 +msgid "invalid register operand when updating" +msgstr "operando de registro inválido durante atualização" + +#. Mark as non-valid instruction +#: sparc-dis.c:750 +msgid "unknown" +msgstr "desconhecido" + +#: sparc-dis.c:825 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:836 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\", %#.8lx, %#.8lx\n" + +#: sparc-dis.c:885 +#, c-format +msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" +msgstr "Erro interno: sparc-opcode.h errado: \"%s\" == \"%s\"\n" + +#: v850-dis.c:224 +#, c-format +msgid "unknown operand shift: %x\n" +msgstr "deslocamento de operando desconhecido: %x\n" + +#: v850-dis.c:236 +#, c-format +msgid "unknown pop reg: %d\n" +msgstr "registrador pop desconhecido: %d\n" + +#. The functions used to insert and extract complicated operands. +#. Note: There is a conspiracy between these functions and +#. v850_insert_operand() in gas/config/tc-v850.c. Error messages +#. containing the string 'out of range' will be ignored unless a +#. specific command line option is given to GAS. +#: v850-opc.c:68 +msgid "displacement value is not in range and is not aligned" +msgstr "valor do deslocamento está fora da faixa e não está alinhado" + +#: v850-opc.c:69 +msgid "displacement value is out of range" +msgstr "valor do deslocamento está fora da faixa" + +#: v850-opc.c:70 +msgid "displacement value is not aligned" +msgstr "valor do deslocamento não está alinhado" + +#: v850-opc.c:72 +msgid "immediate value is out of range" +msgstr "valor imediato está fora da faixa" + +#: v850-opc.c:83 +msgid "branch value not in range and to odd offset" +msgstr "valor do desvio fora da faixa e para deslocamento ímpar" + +#: v850-opc.c:85 v850-opc.c:117 +msgid "branch value out of range" +msgstr "valor do desvio fora da faixa" + +#: v850-opc.c:88 v850-opc.c:120 +msgid "branch to odd offset" +msgstr "desvio para um deslocamento ímpar" + +#: v850-opc.c:115 +msgid "branch value not in range and to an odd offset" +msgstr "valor do desvio fora da faixa e para um deslocamento ímpar" + +#: v850-opc.c:346 +msgid "invalid register for stack adjustment" +msgstr "registrador inválido para ajuste da pilha" + +#: v850-opc.c:370 +msgid "immediate value not in range and not even" +msgstr "valor imediato fora da faixa e não é par" + +#: v850-opc.c:375 +msgid "immediate value must be even" +msgstr "o valor imediato deve ser par" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "Registrador errado no pré-incremento" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Registrador errado no pós-incremento" + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Nome de registrador errado" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "O rótulo conflita com nome de registrador" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "O rótulo conflita com `Rx'" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Expressão imediata errada" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "O operando pequeno não era um número imediato" diff --git a/opcodes/po/sv.po b/opcodes/po/sv.po index a6eda07..56190f8 100644 --- a/opcodes/po/sv.po +++ b/opcodes/po/sv.po @@ -1,12 +1,12 @@ # Swedish messages for opcodes. -# Copyright (C) 2001 Free Software Foundation, Inc. -# Christian Rose <menthos@menthos.com>, 2001. +# Copyright (C) 2001, 2002 Free Software Foundation, Inc. +# Christian Rose <menthos@menthos.com>, 2001, 2002. # msgid "" msgstr "" -"Project-Id-Version: opcodes 2.11\n" -"POT-Creation-Date: 2002-01-31 17:10+0000\n" -"PO-Revision-Date: 2001-10-23 15:35+0200\n" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-08-03 13:19+0200\n" "Last-Translator: Christian Rose <menthos@menthos.com>\n" "Language-Team: Swedish <sv@li.org>\n" "MIME-Version: 1.0\n" @@ -25,16 +25,16 @@ msgstr "hopptipset ligger inte på jämn gräns" msgid "Illegal limm reference in last instruction!\n" msgstr "Otillåten limm-referens i sista instruktionen!\n" -#: arm-dis.c:502 +#: arm-dis.c:507 msgid "<illegal precision>" msgstr "<otillåten precision>" -#: arm-dis.c:1012 +#: arm-dis.c:1010 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Okänt registernamn är angivet: %s\n" -#: arm-dis.c:1019 +#: arm-dis.c:1017 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Okänt disassembleralternativ: %s\n" @@ -62,8 +62,8 @@ msgstr "Internt fel i disassembleraren" msgid "unknown constraint `%c'" msgstr "okänd begränsning \"%c\"" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 -#: xstormy16-ibld.c:195 +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)" @@ -89,111 +89,126 @@ msgstr "Okänt fel %d\n" msgid "Address 0x%x is out of bounds.\n" msgstr "Adressen 0x%x ligger utanför tillåtna gränser.\n" -#: fr30-asm.c:323 m32r-asm.c:325 openrisc-asm.c:244 xstormy16-asm.c:231 +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "Okänt fält %d vid tolkning.\n" -#: fr30-asm.c:373 m32r-asm.c:375 openrisc-asm.c:294 xstormy16-asm.c:281 +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 msgid "missing mnemonic in syntax string" -msgstr "" +msgstr "instruktion saknas i syntaxsträng" #. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 m32r-asm.c:511 -#: m32r-asm.c:515 m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 -#: openrisc-asm.c:434 openrisc-asm.c:521 openrisc-asm.c:623 -#: xstormy16-asm.c:417 xstormy16-asm.c:421 xstormy16-asm.c:508 -#: xstormy16-asm.c:610 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 msgid "unrecognized instruction" msgstr "okänd instruktion" -#: fr30-asm.c:556 m32r-asm.c:558 openrisc-asm.c:477 xstormy16-asm.c:464 +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")" -#: fr30-asm.c:566 m32r-asm.c:568 openrisc-asm.c:487 xstormy16-asm.c:474 -#, fuzzy, c-format +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 +#, c-format msgid "syntax error (expected char `%c', found end of instruction)" -msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade \"%c\")" +msgstr "syntaxfel (tecknet \"%c\" förväntades, hittade slutet på instruktion)" -#: fr30-asm.c:594 m32r-asm.c:596 openrisc-asm.c:515 xstormy16-asm.c:502 +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 msgid "junk at end of line" msgstr "skräp vid slutet på raden" -#: fr30-asm.c:701 m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:609 -#, fuzzy +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 msgid "unrecognized form of instruction" -msgstr "okänd instruktion" +msgstr "okänd instruktionsform" -#: fr30-asm.c:713 m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:621 +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 #, c-format msgid "bad instruction `%.50s...'" msgstr "felaktig instruktion \"%.50s...\"" -#: fr30-asm.c:716 m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:624 +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 #, c-format msgid "bad instruction `%.50s'" msgstr "felaktig instruktion \"%.50s\"" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 #: xstormy16-dis.c:39 msgid "*unknown*" msgstr "*okänd*" -#: fr30-dis.c:318 m32r-dis.c:249 openrisc-dis.c:136 xstormy16-dis.c:169 +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "Okänt fält %d vid utskrift av instruktion.\n" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 -#, fuzzy, c-format +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 +#, c-format msgid "operand out of range (%ld not between %ld and %lu)" -msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %ld)" +msgstr "operanden är utanför intervallet (%ld är inte mellan %ld och %lu)" -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "operanden utanför intervallet (%lu inte mellan 0 och %lu)" -#: fr30-ibld.c:730 m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "Okänt fält %d vid konstruktion av instruktion.\n" -#: fr30-ibld.c:937 m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "Okänt fält %d vid avkodning av instruktion.\n" -#: fr30-ibld.c:1086 m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "Okänt fält %d vid hämtning av heltalsoperand.\n" -#: fr30-ibld.c:1215 m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "Okänt fält %d vid hämtning av vma-operand.\n" -#: fr30-ibld.c:1349 m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "Okänt fält %d vid inställning av heltalsoperand.\n" -#: fr30-ibld.c:1471 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 #: xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "Okänt fält %d vid inställning av vma-operand.\n" -#: h8300-dis.c:384 +#: h8300-dis.c:385 #, c-format msgid "Hmmmm %x" msgstr "Hmmmm %x" -#: h8300-dis.c:395 +#: h8300-dis.c:396 #, c-format msgid "Don't understand %x \n" msgstr "Förstår inte %x \n" @@ -243,35 +258,34 @@ msgstr "<funktionskod %d>" msgid "# <dis error: %08x>" msgstr "# <disassemblerarfel: %08x>" -#: mips-dis.c:290 +#: mips-dis.c:337 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "# internt fel, okänd modifierare(%c)" -#: mips-dis.c:1154 -#, fuzzy, c-format +#: mips-dis.c:1209 +#, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" -msgstr "# internt fel, okänd modifierare(%c)" +msgstr "# internt disassemblerfel, okänd modifierare (%c)" #: mmix-dis.c:34 #, c-format msgid "Bad case %d (%s) in %s:%d\n" -msgstr "" +msgstr "Felaktigt fall %d (%s) i %s:%d\n" #: mmix-dis.c:44 #, c-format msgid "Internal: Non-debugged code (test-case missing): %s:%d" -msgstr "" +msgstr "Internt: Ej felsökt kod (testfall saknas): %s:%d" #: mmix-dis.c:53 -#, fuzzy msgid "(unknown)" -msgstr "okänd" +msgstr "(okänd)" #: mmix-dis.c:517 -#, fuzzy, c-format +#, c-format msgid "*unknown operands type: %d*" -msgstr "okänt operandskifte: %x\n" +msgstr "*okänd operandtyp: %d*" #. I and Z are output operands and can`t be immediate #. * A is an address and we can`t have the address of @@ -283,62 +297,62 @@ msgstr "okänt operandskifte: %x\n" msgid "$<undefined>" msgstr "$<odefinierad>" -#: ppc-opc.c:765 ppc-opc.c:798 +#: ppc-opc.c:777 ppc-opc.c:810 msgid "invalid conditional option" msgstr "ogiltig villkorlig flagga" -#: ppc-opc.c:800 +#: ppc-opc.c:812 msgid "attempt to set y bit when using + or - modifier" msgstr "försök att ställa in y-biten då modifieraren + eller - användes" -#: ppc-opc.c:832 ppc-opc.c:884 +#: ppc-opc.c:844 ppc-opc.c:896 msgid "offset not a multiple of 4" -msgstr "" +msgstr "avståndet är inte en multipel av 4" -#: ppc-opc.c:857 +#: ppc-opc.c:869 msgid "offset not between -2048 and 2047" -msgstr "" +msgstr "avståndet är inte mellan -2048 och 2047" -#: ppc-opc.c:882 +#: ppc-opc.c:894 msgid "offset not between -8192 and 8191" -msgstr "" +msgstr "avståndet är inte mellan -8192 och 8191" -#: ppc-opc.c:910 +#: ppc-opc.c:922 msgid "ignoring least significant bits in branch offset" msgstr "ignorerar minst signifikanta bitarna i grenavstånd" -#: ppc-opc.c:944 ppc-opc.c:981 +#: ppc-opc.c:956 ppc-opc.c:993 msgid "illegal bitmask" msgstr "otillåten bitmask" -#: ppc-opc.c:1054 +#: ppc-opc.c:1066 msgid "value out of range" msgstr "värdet är utanför intervallet" -#: ppc-opc.c:1130 +#: ppc-opc.c:1142 msgid "index register in load range" msgstr "indexregistret är i inläsningsintervallet" -#: ppc-opc.c:1146 +#: ppc-opc.c:1158 msgid "invalid register operand when updating" msgstr "ogiltig registeroperand vid uppdatering" #. Mark as non-valid instruction -#: sparc-dis.c:749 +#: sparc-dis.c:750 msgid "unknown" msgstr "okänd" -#: sparc-dis.c:824 +#: sparc-dis.c:825 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:835 +#: sparc-dis.c:836 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:884 +#: sparc-dis.c:885 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "Internt fel: felaktig sparc-opcode.h: \"%s\" == \"%s\"\n" @@ -360,8 +374,7 @@ msgstr "okänt pop-register: %d\n" #. specific command line option is given to GAS. #: v850-opc.c:68 msgid "displacement value is not in range and is not aligned" -msgstr "" -"förskjutningsvärdet är inte inom intervallet och ligger inte på jämn gräns" +msgstr "förskjutningsvärdet är inte inom intervallet och ligger inte på jämn gräns" #: v850-opc.c:69 msgid "displacement value is out of range" @@ -404,35 +417,32 @@ msgid "immediate value must be even" msgstr "omedelbara värdet måste vara jämnt" #: xstormy16-asm.c:74 -#, fuzzy msgid "Bad register in preincrement" -msgstr "indexregistret är i inläsningsintervallet" +msgstr "Felaktigt register i förhandsökning" #: xstormy16-asm.c:79 -#, fuzzy msgid "Bad register in postincrement" -msgstr "ogiltigt register för stackjustering" +msgstr "Felaktigt register i efterhandsökning" #: xstormy16-asm.c:81 -#, fuzzy msgid "Bad register name" -msgstr "indexregistret är i inläsningsintervallet" +msgstr "Felaktigt registernamn" #: xstormy16-asm.c:85 msgid "Label conflicts with register name" -msgstr "" +msgstr "Etiketten är i konflikt med registernamn" #: xstormy16-asm.c:89 msgid "Label conflicts with `Rx'" -msgstr "" +msgstr "Etiketten är i konflikt med \"Rx\"" #: xstormy16-asm.c:91 msgid "Bad immediate expression" -msgstr "" +msgstr "Felaktigt omedelbart uttryck" #: xstormy16-asm.c:120 msgid "Small operand was not an immediate number" -msgstr "" +msgstr "Liten operand var inte ett omedelbart tal" #~ msgid "unrecognized keyword/register name" #~ msgstr "okänt namn på nyckelord/register" diff --git a/opcodes/po/tr.po b/opcodes/po/tr.po index e776662..75ef049 100644 --- a/opcodes/po/tr.po +++ b/opcodes/po/tr.po @@ -4,9 +4,9 @@ # msgid "" msgstr "" -"Project-Id-Version: opcodes 2.12-pre020121\n" -"POT-Creation-Date: 2002-01-17 13:58+0000\n" -"PO-Revision-Date: 2002-02-17 11:26EET\n" +"Project-Id-Version: opcodes 2.12.91\n" +"POT-Creation-Date: 2002-07-23 15:55-0400\n" +"PO-Revision-Date: 2002-07-24 11:26EET\n" "Last-Translator: Deniz Akkus Kanca <deniz@arayan.com>\n" "Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n" "MIME-Version: 1.0\n" @@ -26,21 +26,21 @@ msgstr "atlama iÅŸareti hizalı deÄŸil" msgid "Illegal limm reference in last instruction!\n" msgstr "Son iÅŸlemde geçersiz limm referansı!\n" -#: arm-dis.c:509 +#: arm-dis.c:507 msgid "<illegal precision>" msgstr "<geçersiz kesinlik>" -#: arm-dis.c:1019 +#: arm-dis.c:1010 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "Bilinmeyen yazmaç ad kümesi: %s\n" -#: arm-dis.c:1026 +#: arm-dis.c:1017 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "Bilinmeyen karşıt-çevirici seçeneÄŸi: %s\n" -#: arm-dis.c:1198 +#: arm-dis.c:1191 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -63,7 +63,8 @@ msgstr "İç karşıt-çevirici hatası " msgid "unknown constraint `%c'" msgstr "`%c' bilinmeyen kısıtı" -#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 +#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 +#: openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "Kapsam dışı terim (%ld, %ld ve %ld arasında deÄŸil) " @@ -89,106 +90,126 @@ msgstr "Bilinmeyen hata %d\n" msgid "Address 0x%x is out of bounds.\n" msgstr "0x%x adresi sınırların dışında.\n" -#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 +#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 +#: xstormy16-asm.c:231 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "Ayrıştırma esnasında bilinmeyen alan %d bulundu.\n" -#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 +#: xstormy16-asm.c:281 msgid "missing mnemonic in syntax string" msgstr "biçem dizgesinde ipucu eksik" #. We couldn't parse it. -#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 -#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 -#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 +#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 +#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 msgid "unrecognized instruction" msgstr "bilinmeyen iÅŸlem" -#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 +#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 +#: xstormy16-asm.c:464 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "biçem hatası (char `%c' beklenirken `%c' bulundu)" -#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 +#: xstormy16-asm.c:474 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "biçem hatası (char `%c' beklenirken iÅŸlem sonu bulundu)" -#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 +#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 +#: xstormy16-asm.c:502 msgid "junk at end of line" msgstr "Satır sonu bozuk " -#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 +#: xstormy16-asm.c:609 msgid "unrecognized form of instruction" msgstr "bilinmeyen iÅŸlem türü" -#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 +#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 +#: xstormy16-asm.c:621 #, c-format msgid "bad instruction `%.50s...'" msgstr "geçersiz iÅŸlem `%.50s...'" -#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 +#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 +#: xstormy16-asm.c:624 #, c-format msgid "bad instruction `%.50s'" msgstr "geçersiz iÅŸlem `%.50s'" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 +#: xstormy16-dis.c:39 msgid "*unknown*" msgstr "*bilinmeyen*" -#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 +#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 +#: xstormy16-dis.c:169 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "yönerge yazdırılırken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#: xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "Kapsam dışı iÅŸlenen (%ld, %ld ve %lu arasında deÄŸil) " -#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 +#: xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "kapsam dışı terim (%lu 0 ve %lu arasında deÄŸil) " -#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 +#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 +#: xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "Yönerge oluÅŸturulurken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 +#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 +#: xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "Yönerge çözümlenirken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 +#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 +#: xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "`int' terimi alınırken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 +#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 +#: xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "`vma' terimi alınırken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 +#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 +#: xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "`int' terimi atanırken bilinmeyen alan %d bulundu.\n" -#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 +#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 +#: xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "`vma' terimi atanırken bilinmeyen alan %d bulundu.\n" -#: h8300-dis.c:384 +#: h8300-dis.c:385 #, c-format msgid "Hmmmm %x" msgstr "Hmmmm %x" -#: h8300-dis.c:395 +#: h8300-dis.c:396 #, c-format msgid "Don't understand %x \n" msgstr "%x anlaşılamadı\n" @@ -238,12 +259,12 @@ msgstr "<iÅŸlev kodu %d>" msgid "# <dis error: %08x>" msgstr "# <`dis' hatası: %08x>" -#: mips-dis.c:290 +#: mips-dis.c:337 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "#iç hata, tanımlanmamış deÄŸiÅŸtirici (%c)" -#: mips-dis.c:1154 +#: mips-dis.c:1209 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "#iç karşıt-çevirici hatası, tanımlanmamış deÄŸiÅŸtirici (%c)" @@ -277,62 +298,62 @@ msgstr "bilinmeyen iÅŸlenen türü: %d*" msgid "$<undefined>" msgstr "$<tanımlanmamış>" -#: ppc-opc.c:765 ppc-opc.c:798 +#: ppc-opc.c:777 ppc-opc.c:810 msgid "invalid conditional option" msgstr "koÅŸullu seçenek geçersiz " -#: ppc-opc.c:800 +#: ppc-opc.c:812 msgid "attempt to set y bit when using + or - modifier" msgstr "+ veya - deÄŸiÅŸtiricisini kullanırken y bitini atama denemesi" -#: ppc-opc.c:832 ppc-opc.c:884 +#: ppc-opc.c:844 ppc-opc.c:896 msgid "offset not a multiple of 4" msgstr "görece 4'ün katı deÄŸil" -#: ppc-opc.c:857 +#: ppc-opc.c:869 msgid "offset not between -2048 and 2047" msgstr "görece -2048 ve 2047 arasında deÄŸil" -#: ppc-opc.c:882 +#: ppc-opc.c:894 msgid "offset not between -8192 and 8191" msgstr "görece -8192 ve 8191 arasında deÄŸil" -#: ppc-opc.c:910 +#: ppc-opc.c:922 msgid "ignoring least significant bits in branch offset" msgstr "Dal göreli konumunda en önemsiz bitler atlanıyor" -#: ppc-opc.c:944 ppc-opc.c:981 +#: ppc-opc.c:956 ppc-opc.c:993 msgid "illegal bitmask" msgstr "geçersiz bitmask " -#: ppc-opc.c:1054 +#: ppc-opc.c:1066 msgid "value out of range" msgstr "deÄŸer aralık dışı" -#: ppc-opc.c:1130 +#: ppc-opc.c:1142 msgid "index register in load range" msgstr "yükleme aralığında endeks yazmacı" -#: ppc-opc.c:1146 +#: ppc-opc.c:1158 msgid "invalid register operand when updating" msgstr "güncelleme esnasında geçersiz yazmaç terimi bulundu" #. Mark as non-valid instruction -#: sparc-dis.c:749 +#: sparc-dis.c:750 msgid "unknown" msgstr "bilinmeyen" -#: sparc-dis.c:824 +#: sparc-dis.c:825 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:835 +#: sparc-dis.c:836 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" -#: sparc-dis.c:884 +#: sparc-dis.c:885 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "İç hata: geçersiz sparc-opcode.h: \"%s\" == \"%s\"\n" @@ -395,3 +416,31 @@ msgstr "ÅŸimdiki deÄŸer kapsam dışı ve çift sayı deÄŸil" #: v850-opc.c:375 msgid "immediate value must be even" msgstr "ÅŸimdiki deÄŸer çift sayı olmalı" + +#: xstormy16-asm.c:74 +msgid "Bad register in preincrement" +msgstr "Arttırma öncesinde geçersiz yazmaç" + +#: xstormy16-asm.c:79 +msgid "Bad register in postincrement" +msgstr "Arttırma sonrasında geçersiz yazmaç " + +#: xstormy16-asm.c:81 +msgid "Bad register name" +msgstr "Geçersiz yazmaç adı" + +#: xstormy16-asm.c:85 +msgid "Label conflicts with register name" +msgstr "Etiket, yazmaç adıyla çakışıyor" + +#: xstormy16-asm.c:89 +msgid "Label conflicts with `Rx'" +msgstr "Etiket, `Rx' ile çakışıyor" + +#: xstormy16-asm.c:91 +msgid "Bad immediate expression" +msgstr "Hatalı ÅŸimdiki ifade" + +#: xstormy16-asm.c:120 +msgid "Small operand was not an immediate number" +msgstr "Küçük iÅŸlenen ÅŸimdiki sayı deÄŸil" diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 0ac8275..bd4dfac 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -53,7 +53,29 @@ powerpc_dialect(info) || strcmp (info->disassembler_options, "booke64") == 0)) dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; else - dialect |= PPC_OPCODE_403 | PPC_OPCODE_601; + if ((info->mach == bfd_mach_ppc_e500) + || (info->disassembler_options + && ( strcmp (info->disassembler_options, "e500") == 0 + || strcmp (info->disassembler_options, "e500x2") == 0))) + { + dialect |= PPC_OPCODE_BOOKE + | PPC_OPCODE_SPE | PPC_OPCODE_ISEL + | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK + | PPC_OPCODE_RFMCI; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } + else + if (info->disassembler_options + && (strcmp (info->disassembler_options, "efs") == 0)) + { + dialect |= PPC_OPCODE_EFS; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } + else + dialect |= PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_COMMON; if (info->disassembler_options && strcmp (info->disassembler_options, "power4") == 0) @@ -153,6 +175,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) || (opcode->flags & dialect) == 0) continue; + if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC)) + continue; + /* Make two passes over the operands. First see if any of them have extraction functions, and, if they do, make sure the instruction is valid. */ diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 70167f7..9ba4e25 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -100,6 +100,10 @@ static unsigned long insert_nsi PARAMS ((unsigned long, long, int, const char **)); static long extract_nsi PARAMS ((unsigned long, int, int *)); +static unsigned long insert_pmrn + PARAMS ((unsigned long, long, int, const char **)); +static long extract_pmrn + PARAMS ((unsigned long, int, int *)); static unsigned long insert_ral PARAMS ((unsigned long, long, int, const char **)); static unsigned long insert_ram @@ -122,6 +126,18 @@ static unsigned long insert_tbr PARAMS ((unsigned long, long, int, const char **)); static long extract_tbr PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ev2 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_ev2 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ev4 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_ev4 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ev8 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_ev8 + PARAMS ((unsigned long, int, int *)); /* The operands table. @@ -235,8 +251,21 @@ const struct powerpc_operand powerpc_operands[] = #define CR BT + 1 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + /* The CRB field in an X form instruction. */ +#define CRB CR + 1 + { 5, 6, 0, 0, 0 }, + + /* The CRFD field in an X form instruction. */ +#define CRFD CRB + 1 + { 3, 23, 0, 0, 0 }, + + /* The CRFS field in an X form instruction. */ +#define CRFS CRFD + 1 + { 3, 0, 0, 0, 0 }, + /* The CT field in an X form instruction. */ -#define CT CR + 1 +#define CT CRFS + 1 +#define RD CT { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, /* The D field in a D form instruction. This is a displacement off @@ -365,8 +394,12 @@ const struct powerpc_operand powerpc_operands[] = { 16, 0, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, + /* The PMRN field in an X form instruction. */ +#define PMRN NSI + 1 + { 16, 0, insert_pmrn, extract_pmrn, PPC_OPERAND_GPR }, + /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ -#define RA NSI + 1 +#define RA PMRN + 1 #define RA_MASK (0x1f << 16) { 5, 16, 0, 0, PPC_OPERAND_GPR }, @@ -505,8 +538,24 @@ const struct powerpc_operand powerpc_operands[] = #define SHB UIMM + 1 { 4, 6, 0, 0, 0 }, + /* The other UIMM field in a EVX form instruction. */ +#define EVUIMM SHB + 1 + { 5, 11, 0, 0, 0 }, + + /* The other UIMM field in a half word EVX form instruction. */ +#define EVUIMM_2 EVUIMM + 1 + { 5, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a word EVX form instruction. */ +#define EVUIMM_4 EVUIMM_2 + 1 + { 5, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a double EVX form instruction. */ +#define EVUIMM_8 EVUIMM_4 + 1 + { 8, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, + /* The WS field. */ -#define WS SHB + 1 +#define WS EVUIMM_8 + 1 #define WS_MASK (0x7 << 11) { 3, 11, 0, 0, 0 }, @@ -829,6 +878,75 @@ extract_boe (insn, dialect, invalid) return value & 0x1e; } +static unsigned long +insert_ev2 (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char ** errmsg ATTRIBUTE_UNUSED; +{ + if ((value & 1) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 2"); + if ((value > 62) != 0 && errmsg != NULL) + *errmsg = _("offset greater than 62"); + return insn | ((value & 0xf8) << 8); +} + +static long +extract_ev2 (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int * invalid ATTRIBUTE_UNUSED; +{ + return (insn >> 8) & 0xf8; +} + +static unsigned long +insert_ev4 (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char ** errmsg ATTRIBUTE_UNUSED; +{ + if ((value & 3) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 4"); + if ((value > 124) != 0 && errmsg != NULL) + *errmsg = _("offset greater than 124"); + return insn | ((value & 0xf8) << 8); +} + +static long +extract_ev4 (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int * invalid ATTRIBUTE_UNUSED; +{ + return (insn >> 8) & 0xf8; +} + +static unsigned long +insert_ev8 (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char ** errmsg ATTRIBUTE_UNUSED; +{ + if ((value & 7) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 8"); + if ((value > 248) != 0 && errmsg != NULL) + *errmsg = _("offset greater than 248"); + return insn | ((value & 0xf8) << 8); +} + +static long +extract_ev8 (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int * invalid ATTRIBUTE_UNUSED; +{ + return (insn >> 8) & 0xf8; +} + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ @@ -1111,6 +1229,28 @@ extract_nsi (insn, dialect, invalid) return - (((insn & 0xffff) ^ 0x8000) - 0x8000); } +/* The PMRN field in a X form instruction. + This has 5+5 bits switched around. */ + +static unsigned long +insert_pmrn (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg ATTRIBUTE_UNUSED; +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x3e) << 11); +} + +static long +extract_pmrn (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return ((insn >> 16) & 0x1f) | ((insn >> 11) & 0x3e); +} + /* The RA field in a D or X form instruction which is an updating load, which means that the RA field may not be zero and may not equal the RT field. */ @@ -1332,6 +1472,14 @@ extract_tbr (insn, dialect, invalid) #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) +/* An Context form instruction. */ +#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) +#define CTX_MASK CTX(0x3f, 0x7) + +/* An User Context form instruction. */ +#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define UCTX_MASK UCTX(0x3f, 0x1f) + /* The main opcode mask with the RA field clear. */ #define DRA_MASK (OP_MASK | RA_MASK) @@ -1343,6 +1491,10 @@ extract_tbr (insn, dialect, invalid) #define DEO(op, xop) (OP (op) | ((xop) & 0xf)) #define DE_MASK DEO (0x3e, 0xf) +/* An EVSEL form instruction. */ +#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) +#define EVSEL_MASK EVSEL(0x3f, 0xff) + /* An M form instruction. */ #define M(op, rc) (OP (op) | ((rc) & 1)) #define M_MASK M (0x3f, 1) @@ -1457,6 +1609,10 @@ extract_tbr (insn, dialect, invalid) #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) +/* An X form isel instruction. */ +#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) +#define XISEL_MASK XISEL(0x3f, 0x1f) + /* An XL form instruction with the LK field set to 0. */ #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) @@ -1528,6 +1684,10 @@ extract_tbr (insn, dialect, invalid) /* An X form instruction with everything filled in except the E field. */ #define XE_MASK (0xffff7fff) +/* An X form user context instruction. */ +#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define XUC_MASK XUC(0x3f, 0x1f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -1609,6 +1769,14 @@ extract_tbr (insn, dialect, invalid) #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 #define BOOKE PPC_OPCODE_BOOKE #define BOOKE64 PPC_OPCODE_BOOKE64 +#define CLASSIC PPC_OPCODE_CLASSIC +#define PPCSPE PPC_OPCODE_SPE +#define PPCISEL PPC_OPCODE_ISEL +#define PPCEFS PPC_OPCODE_EFS +#define PPCBRLK PPC_OPCODE_BRLOCK +#define PPCPMR PPC_OPCODE_PMR +#define PPCCHLK PPC_OPCODE_CACHELCK +#define PPCRFMCI PPC_OPCODE_RFMCI /* The opcode table. @@ -1918,6 +2086,306 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RD, RB, UIMM } }, +{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RD, UIMM, RB } }, +{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RD, RA } }, +{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RD, RA } }, +{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RD, RA } }, +{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RD, RA } }, +{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RD, RA } }, +{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RD, RA } }, +{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RD, RA } }, + +{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RD, RA, EVUIMM } }, +{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RD, RA, EVUIMM } }, +{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RD, RA, EVUIMM } }, +{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RD, RA, EVUIMM } }, +{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RD, SIMM } }, +{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RD, SIMM } }, +{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RD, RA, RB, CRFS } }, + +{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RD, RA } }, +{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RD, RA } }, +{ "evfsneg", VX(4, 656), VX_MASK, PPCSPE, { RD, RA } }, +{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RD, RB } }, +{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RD, RB } }, + +{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RD, RA } }, +{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RD, RA } }, +{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RD, RA } }, +{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RD, RA, RB } }, +{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RD, RA, RB } }, +{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RD, RA, RB } }, +{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RD, RA, RB } }, +{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RD, RB } }, +{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RD, RB } }, +{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RD, RB } }, +{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RD, RB } }, +{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RD, RB } }, + +{ "evsabs", VX(4, 708), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsnabs", VX(4, 709), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsneg", VX(4, 710), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsadd", VX(4, 704), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evssub", VX(4, 705), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evsmul", VX(4, 712), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evsdiv", VX(4, 713), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evscmpgt", VX(4, 716), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evsgmplt", VX(4, 717), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evsgmpeq", VX(4, 718), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evststgt", VX(4, 732), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evststlt", VX(4, 733), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evststeq", VX(4, 734), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evscfui", VX(4, 720), VX_MASK, PPCSPE, { RD, RB } }, +{ "evscfsi", VX(4, 721), VX_MASK, PPCSPE, { RD, RB } }, +{ "evscfuf", VX(4, 722), VX_MASK, PPCSPE, { RD, RB } }, +{ "evscfsf", VX(4, 723), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctui", VX(4, 724), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctuiz", VX(4, 728), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctsi", VX(4, 725), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctsiz", VX(4, 730), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctuf", VX(4, 726), VX_MASK, PPCSPE, { RD, RB } }, +{ "evsctsf", VX(4, 727), VX_MASK, PPCSPE, { RD, RB } }, + +{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwlssf", VX(4, 1091), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlssfa", VX(4, 1123), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmf", VX(4, 1099), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmfa", VX(4, 1131), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwhssfaa",VX(4, 1351), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhssmaa",VX(4, 1349), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmfaa",VX(4, 1359), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmiaa",VX(4, 1357), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhusiaa",VX(4, 1348), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhumiaa",VX(4, 1356), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwlssfaaw",VX(4, 1347), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmfaaw",VX(4, 1355), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwhssfan",VX(4, 1479), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhssian",VX(4, 1477), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmfan",VX(4, 1487), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhsmian",VX(4, 1485), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhusian",VX(4, 1476), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhumian",VX(4, 1484), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwlssfanw",VX(4, 1475), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmfanw",VX(4, 1483), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwhgssfaa",VX(4, 1383), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgsmfaa",VX(4, 1391), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgsmiaa",VX(4, 1381), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgumiaa",VX(4, 1380), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwhgssfan",VX(4, 1511), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgsmfan",VX(4, 1519), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgsmian",VX(4, 1509), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwhgumian",VX(4, 1508), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RD, RA, RB } }, + +{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RD, RA } }, +{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RD, RA } }, +{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RD, RA } }, +{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RD, RA } }, + +{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RD, RA } }, +{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RD, RA } }, + +{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RD, RA } }, + +{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RD, RA, RB } }, +{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RD, RA, RB } }, + { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, @@ -2467,6 +2935,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, +{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, + { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, @@ -2785,6 +3255,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "isel", XISEL(31,15),XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, + { "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, @@ -2914,6 +3386,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, { "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } }, +{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, @@ -2932,6 +3406,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK, { CT, RA, RB }}, + { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, @@ -2957,6 +3433,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "wrteei", X(31,163), XE_MASK, PPC403, { E } }, { "wrteei", X(31,163), XE_MASK, BOOKE, { E } }, +{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, +{ "dcbtlse", X(31,174), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, @@ -3001,6 +3480,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, @@ -3033,6 +3514,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "icblce", X(31,238), X_MASK, PPCCHLK, { CT, RA, RB }}, { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, @@ -3137,6 +3619,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, +{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMRN }}, + { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, @@ -3181,6 +3665,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, +{ "mfspefscr",XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, @@ -3296,9 +3781,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, -{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } }, -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, +{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, +{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, @@ -3308,12 +3793,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, +{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "dcblce", X(31,398), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, @@ -3444,6 +3933,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, +{ "mtspefscr",XSPR(31,467,512),XSPR_MASK, PPCSPE, { RT } }, { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, @@ -3514,6 +4004,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, +{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMRN, RS }}, + +{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, @@ -3534,6 +4028,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "icbtlse", X(31,494), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, @@ -3542,6 +4038,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, +{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } }, { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, @@ -3572,6 +4069,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } }, +{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, @@ -4060,6 +4558,9 @@ const struct powerpc_macro powerpc_macros[] = { { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, +{ "mftbl", 1, BOOKE, "mfspr %0,tbl" }, +{ "mftbu", 1, BOOKE, "mfspr %0,tbu" }, +{ "mftb", 2, BOOKE, "mfspr %0,%1" }, }; const int powerpc_num_macros = diff --git a/opcodes/sparc-dis.c b/opcodes/sparc-dis.c index 4c59398..47ebb31 100644 --- a/opcodes/sparc-dis.c +++ b/opcodes/sparc-dis.c @@ -1,6 +1,6 @@ /* Print SPARC instructions. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000 Free Software Foundation, Inc. + 2000, 2002 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -188,7 +188,7 @@ is_delayed_branch (insn) for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { - CONST struct sparc_opcode *opcode = op->opcode; + const struct sparc_opcode *opcode = op->opcode; if ((opcode->match & insn) == opcode->match && (opcode->lose & insn) == 0) return (opcode->flags & F_DELAYED); @@ -272,7 +272,7 @@ print_insn_sparc (memaddr, info) for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { - CONST struct sparc_opcode *opcode = op->opcode; + const struct sparc_opcode *opcode = op->opcode; /* If the insn isn't supported by the current architecture, skip it. */ if (! (opcode->architecture & current_arch_mask)) @@ -312,7 +312,7 @@ print_insn_sparc (memaddr, info) (*info->fprintf_func) (stream, opcode->name); { - register CONST char *s; + register const char *s; if (opcode->args[0] != ',') (*info->fprintf_func) (stream, " "); diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c index d375e69..6c19138 100644 --- a/opcodes/z8k-dis.c +++ b/opcodes/z8k-dis.c @@ -515,10 +515,10 @@ unparse_instr (instr_data, is_segmented) break; case CLASS_BA: if (is_segmented) - sprintf (tmp_str, "rr%ld(#%lx)", instr_data->arg_reg[datum_value], + sprintf (tmp_str, "rr%ld(#0x%lx)", instr_data->arg_reg[datum_value], instr_data->immediate); else - sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value], + sprintf (tmp_str, "r%ld(#0x%lx)", instr_data->arg_reg[datum_value], instr_data->immediate); strcat (out_str, tmp_str); break; diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h index 025cfab..0e478bf 100644 --- a/opcodes/z8k-opc.h +++ b/opcodes/z8k-opc.h @@ -1621,14 +1621,14 @@ opcode_entry_type z8k_table[] = { {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,135}, -/* 0011 1101 dddd 0100 imm16 *** in rd,imm16 */ +/* 0011 1011 dddd 0100 imm16 *** in rd,imm16 */ { #ifdef NICENAMES "in rd,imm16",16,12, 0x00, #endif "in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,136}, + {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,136}, /* 0011 1100 ssN0 dddd *** inb rbd,@rs */ diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c index fa85059..5bd9240 100644 --- a/opcodes/z8kgen.c +++ b/opcodes/z8kgen.c @@ -209,8 +209,8 @@ struct op opt[] = "------", 8, 16, "0111 1010 0000 0000", "halt", 0, "------", 10, 16, "0011 1101 ssN0 dddd", "in rd,@rs", 0, - "------", 12, 16, "0011 1101 dddd 0100 imm16", "in rd,imm16", 0, "------", 12, 8, "0011 1100 ssN0 dddd", "inb rbd,@rs", 0, + "------", 12, 16, "0011 1011 dddd 0100 imm16", "in rd,imm16", 0, "------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0, "-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0, "-ZSV--", 14, 16, "0110 1001 ddN0 imm4m1 address_dst", "inc address_dst(rd),imm4m1", 0, |