diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 66 | ||||
| -rw-r--r-- | opcodes/aarch64-asm-2.c | 119 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.c | 434 | ||||
| -rw-r--r-- | opcodes/aarch64-asm.h | 10 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 125 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.c | 532 | ||||
| -rw-r--r-- | opcodes/aarch64-dis.h | 11 | ||||
| -rw-r--r-- | opcodes/aarch64-gen.c | 14 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 4 |
9 files changed, 759 insertions, 556 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ea407e3..a30e823 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,69 @@ +2018-05-15 Tamar Christina <tamar.christina@arm.com> + + PR binutils/21446 + * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean + and take error struct. + * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, + aarch64_ins_reglist, aarch64_ins_ldst_reglist, + aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, + aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, + aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, + aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, + aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, + aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, + aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, + aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, + aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, + aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, + aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, + aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, + aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, + aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, + aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, + aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, + aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, + aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, + aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, + aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, + aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, + aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. + * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. + * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, + aarch64_ext_reglist, aarch64_ext_ldst_reglist, + aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, + aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, + aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, + aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, + aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, + aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, + aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, + aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, + aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, + aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, + aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, + aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, + aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, + aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, + aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, + aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, + aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, + aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, + aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, + aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, + aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, + aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, + aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. + (determine_disassembling_preference, aarch64_decode_insn, + print_insn_aarch64_word, print_insn_data): Take errors struct. + (print_insn_aarch64): Use errors. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-gen.c (print_operand_inserter): Use errors and change type to + boolean in aarch64_insert_operan. + (print_operand_extractor): Likewise. + * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. + 2018-05-15 Francois H. Theron <francois.theron@netronome.com> * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 7987384..01bc0e1 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -579,10 +579,11 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) return aarch64_opcode_table + value; } -const char* +bfd_boolean aarch64_insert_operand (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { /* Use the index as the key. */ int key = self - aarch64_operands; @@ -634,26 +635,26 @@ aarch64_insert_operand (const aarch64_operand *self, case 182: case 186: case 189: - return aarch64_ins_regno (self, info, code, inst); + return aarch64_ins_regno (self, info, code, inst, errors); case 13: - return aarch64_ins_reg_extended (self, info, code, inst); + return aarch64_ins_reg_extended (self, info, code, inst, errors); case 14: - return aarch64_ins_reg_shifted (self, info, code, inst); + return aarch64_ins_reg_shifted (self, info, code, inst, errors); case 19: - return aarch64_ins_ft (self, info, code, inst); + return aarch64_ins_ft (self, info, code, inst, errors); case 30: case 31: case 32: case 191: - return aarch64_ins_reglane (self, info, code, inst); + return aarch64_ins_reglane (self, info, code, inst, errors); case 33: - return aarch64_ins_reglist (self, info, code, inst); + return aarch64_ins_reglist (self, info, code, inst, errors); case 34: - return aarch64_ins_ldst_reglist (self, info, code, inst); + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 35: - return aarch64_ins_ldst_reglist_r (self, info, code, inst); + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 36: - return aarch64_ins_ldst_elemlist (self, info, code, inst); + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); case 37: case 38: case 39: @@ -686,85 +687,85 @@ aarch64_insert_operand (const aarch64_operand *self, case 171: case 172: case 173: - return aarch64_ins_imm (self, info, code, inst); + return aarch64_ins_imm (self, info, code, inst, errors); case 41: case 42: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst); + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); case 43: case 44: case 45: - return aarch64_ins_advsimd_imm_modified (self, info, code, inst); + return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); case 49: case 140: - return aarch64_ins_fpimm (self, info, code, inst); + return aarch64_ins_fpimm (self, info, code, inst, errors); case 64: case 147: - return aarch64_ins_limm (self, info, code, inst); + return aarch64_ins_limm (self, info, code, inst, errors); case 65: - return aarch64_ins_aimm (self, info, code, inst); + return aarch64_ins_aimm (self, info, code, inst, errors); case 66: - return aarch64_ins_imm_half (self, info, code, inst); + return aarch64_ins_imm_half (self, info, code, inst, errors); case 67: - return aarch64_ins_fbits (self, info, code, inst); + return aarch64_ins_fbits (self, info, code, inst, errors); case 69: case 70: case 145: - return aarch64_ins_imm_rotate2 (self, info, code, inst); + return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); case 71: case 144: - return aarch64_ins_imm_rotate1 (self, info, code, inst); + return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); case 72: case 73: - return aarch64_ins_cond (self, info, code, inst); + return aarch64_ins_cond (self, info, code, inst, errors); case 79: case 86: - return aarch64_ins_addr_simple (self, info, code, inst); + return aarch64_ins_addr_simple (self, info, code, inst, errors); case 80: - return aarch64_ins_addr_regoff (self, info, code, inst); + return aarch64_ins_addr_regoff (self, info, code, inst, errors); case 81: case 82: case 83: - return aarch64_ins_addr_simm (self, info, code, inst); + return aarch64_ins_addr_simm (self, info, code, inst, errors); case 84: - return aarch64_ins_addr_simm10 (self, info, code, inst); + return aarch64_ins_addr_simm10 (self, info, code, inst, errors); case 85: - return aarch64_ins_addr_uimm12 (self, info, code, inst); + return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); case 87: - return aarch64_ins_addr_offset (self, info, code, inst); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 88: - return aarch64_ins_simd_addr_post (self, info, code, inst); + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 89: - return aarch64_ins_sysreg (self, info, code, inst); + return aarch64_ins_sysreg (self, info, code, inst, errors); case 90: - return aarch64_ins_pstatefield (self, info, code, inst); + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 91: case 92: case 93: case 94: - return aarch64_ins_sysins_op (self, info, code, inst); + return aarch64_ins_sysins_op (self, info, code, inst, errors); case 95: case 96: - return aarch64_ins_barrier (self, info, code, inst); + return aarch64_ins_barrier (self, info, code, inst, errors); case 97: - return aarch64_ins_prfop (self, info, code, inst); + return aarch64_ins_prfop (self, info, code, inst, errors); case 98: - return aarch64_ins_hint (self, info, code, inst); + return aarch64_ins_hint (self, info, code, inst, errors); case 99: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 100: case 101: case 102: case 103: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 104: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 105: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst); + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 106: case 107: case 108: case 109: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst); + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 110: case 111: case 112: @@ -778,7 +779,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 120: case 121: case 122: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst); + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 123: case 124: case 125: @@ -787,49 +788,49 @@ aarch64_insert_operand (const aarch64_operand *self, case 128: case 129: case 130: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst); + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 131: case 132: case 133: case 134: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 135: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 136: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst); + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 137: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 138: - return aarch64_ins_sve_aimm (self, info, code, inst); + return aarch64_ins_sve_aimm (self, info, code, inst, errors); case 139: - return aarch64_ins_sve_asimm (self, info, code, inst); + return aarch64_ins_sve_asimm (self, info, code, inst, errors); case 141: - return aarch64_ins_sve_float_half_one (self, info, code, inst); + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); case 142: - return aarch64_ins_sve_float_half_two (self, info, code, inst); + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); case 143: - return aarch64_ins_sve_float_zero_one (self, info, code, inst); + return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); case 146: - return aarch64_ins_inv_limm (self, info, code, inst); + return aarch64_ins_inv_limm (self, info, code, inst, errors); case 148: - return aarch64_ins_sve_limm_mov (self, info, code, inst); + return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); case 150: - return aarch64_ins_sve_scale (self, info, code, inst); + return aarch64_ins_sve_scale (self, info, code, inst, errors); case 162: case 163: - return aarch64_ins_sve_shlimm (self, info, code, inst); + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); case 164: case 165: - return aarch64_ins_sve_shrimm (self, info, code, inst); + return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 183: case 184: case 185: - return aarch64_ins_sve_quad_index (self, info, code, inst); + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); case 187: - return aarch64_ins_sve_index (self, info, code, inst); + return aarch64_ins_sve_index (self, info, code, inst, errors); case 188: case 190: - return aarch64_ins_sve_reglist (self, info, code, inst); + return aarch64_ins_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index a4c6a27..67c9b6e 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -78,21 +78,23 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code, /* Operand inserters. */ /* Insert register number. */ -const char * +bfd_boolean aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->reg.regno, 0); - return NULL; + return TRUE; } /* Insert register number, index and/or other data for SIMD register element operand, e.g. the last source operand in SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ -const char * +bfd_boolean aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* regno */ insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask); @@ -173,28 +175,30 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, assert (0); } } - return NULL; + return TRUE; } /* Insert regno and len field of a register list operand, e.g. Vn in TBL. */ -const char * +bfd_boolean aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* R */ insert_field (self->fields[0], code, info->reglist.first_regno, 0); /* len */ insert_field (FLD_len, code, info->reglist.num_regs - 1, 0); - return NULL; + return TRUE; } /* Insert Rt and opcode fields for a register list operand, e.g. Vt in AdvSIMD load/store instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value = 0; /* Number of elements in each structure to be loaded/stored. */ @@ -229,15 +233,16 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_field (FLD_opcode, code, value, 0); - return NULL; + return TRUE; } /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load single structure to all lanes instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; /* The opcode dependent area stores the number of elements in @@ -254,15 +259,16 @@ aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, value = (aarch64_insn) 1; insert_field (FLD_S, code, value, 0); - return NULL; + return TRUE; } /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list operand e.g. Vt in AdvSIMD load/store single element instructions. */ -const char * +bfd_boolean aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_field field = {0, 0}; aarch64_insn QSsize = 0; /* fields Q:S:size. */ @@ -302,16 +308,17 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); insert_field_2 (&field, code, opcodeh2, 0); - return NULL; + return TRUE; } /* Insert fields immh:immb and/or Q for e.g. the shift immediate in SSHR <Vd>.<T>, <Vn>.<T>, #<shift> or SSHR <V><d>, <V><n>, #<shift>. */ -const char * +bfd_boolean aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { unsigned val = aarch64_get_qualifier_standard_value (info->qualifier); aarch64_insn Q, imm; @@ -357,15 +364,16 @@ aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, imm = info->imm.value + (8 << (unsigned)val); insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh); - return NULL; + return TRUE; } /* Insert fields for e.g. the immediate operands in BFM <Wd>, <Wn>, #<immr>, #<imms>. */ -const char * +bfd_boolean aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int64_t imm; @@ -373,29 +381,32 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, if (operand_need_shift_by_two (self)) imm >>= 2; insert_all_fields (self, code, imm); - return NULL; + return TRUE; } /* Insert immediate and its shift amount for e.g. the last operand in MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ -const char * +bfd_boolean aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { /* imm16 */ - aarch64_ins_imm (self, info, code, inst); + aarch64_ins_imm (self, info, code, inst, errors); /* hw */ insert_field (FLD_hw, code, info->shifter.amount >> 4, 0); - return NULL; + return TRUE; } /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ -const char * +bfd_boolean aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors + ATTRIBUTE_UNUSED) { enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; uint64_t imm = info->imm.value; @@ -417,7 +428,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc); if (kind == AARCH64_MOD_NONE) - return NULL; + return TRUE; /* shift amount partially in cmode */ assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL); @@ -429,7 +440,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, /* For 8-bit move immediate, the optional LSL #0 does not require encoding. */ if (esize == 1) - return NULL; + return TRUE; amount >>= 3; if (esize == 4) gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */ @@ -444,74 +455,80 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_field_2 (&field, code, amount, 0); - return NULL; + return TRUE; } /* Insert fields for an 8-bit floating-point immediate. */ -const char * +bfd_boolean aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_all_fields (self, code, info->imm.value); - return NULL; + return TRUE; } /* Insert 1-bit rotation immediate (#90 or #270). */ -const char * +bfd_boolean aarch64_ins_imm_rotate1 (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = (info->imm.value - 90) / 180; assert (rot < 2U); insert_field (self->fields[0], code, rot, inst->opcode->mask); - return NULL; + return TRUE; } /* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */ -const char * +bfd_boolean aarch64_ins_imm_rotate2 (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = info->imm.value / 90; assert (rot < 4U); insert_field (self->fields[0], code, rot, inst->opcode->mask); - return NULL; + return TRUE; } /* Insert #<fbits> for the immediate operand in fp fix-point instructions, e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ -const char * +bfd_boolean aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, 64 - info->imm.value, 0); - return NULL; + return TRUE; } /* Insert arithmetic immediate for e.g. the last operand in SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ -const char * +bfd_boolean aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED) + aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* shift */ aarch64_insn value = info->shifter.amount ? 1 : 0; insert_field (self->fields[0], code, value, 0); /* imm12 (unsigned) */ insert_field (self->fields[1], code, info->imm.value, 0); - return NULL; + return TRUE; } /* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether the operand should be inverted before encoding. */ -static const char * +static bfd_boolean aarch64_ins_limm_1 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst, bfd_boolean invert_p) + const aarch64_inst *inst, bfd_boolean invert_p, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; uint64_t imm = info->imm.value; @@ -524,40 +541,43 @@ aarch64_ins_limm_1 (const aarch64_operand *self, insert_fields (code, value, 0, 3, self->fields[2], self->fields[1], self->fields[0]); - return NULL; + return TRUE; } /* Insert logical/bitmask immediate for e.g. the last operand in ORR <Wd|WSP>, <Wn>, #<imm>. */ -const char * +bfd_boolean aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { return aarch64_ins_limm_1 (self, info, code, inst, - inst->opcode->op == OP_BIC); + inst->opcode->op == OP_BIC, errors); } /* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */ -const char * +bfd_boolean aarch64_ins_inv_limm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - return aarch64_ins_limm_1 (self, info, code, inst, TRUE); + return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors); } /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ -const char * +bfd_boolean aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, - aarch64_insn *code, const aarch64_inst *inst) + aarch64_insn *code, const aarch64_inst *inst, + aarch64_operand_error *errors) { aarch64_insn value = 0; assert (info->idx == 0); /* Rt */ - aarch64_ins_regno (self, info, code, inst); + aarch64_ins_regno (self, info, code, inst, errors); if (inst->opcode->iclass == ldstpair_indexed || inst->opcode->iclass == ldstnapair_offs || inst->opcode->iclass == ldstpair_off @@ -580,26 +600,28 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ -const char * +bfd_boolean aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (FLD_Rn, code, info->addr.base_regno, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ -const char * +bfd_boolean aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn S; enum aarch64_modifier_kind kind = info->shifter.kind; @@ -624,15 +646,16 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, S = info->shifter.operator_present && info->shifter.amount_present; insert_field (FLD_S, code, S, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. stlur <Xt>, [<Xn|SP>{, <amount>}]. */ -const char * +bfd_boolean aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (self->fields[0], code, info->addr.base_regno, 0); @@ -647,15 +670,16 @@ aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, assert (info->addr.preind == 1 && info->addr.postind == 0); insert_field (self->fields[2], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */ -const char * +bfd_boolean aarch64_ins_addr_simm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int imm; @@ -679,15 +703,16 @@ aarch64_ins_addr_simm (const aarch64_operand *self, insert_field (self->fields[1], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ -const char * +bfd_boolean aarch64_ins_addr_simm10 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int imm; @@ -703,15 +728,16 @@ aarch64_ins_addr_simm10 (const aarch64_operand *self, assert (info->addr.preind == 1 && info->addr.postind == 0); insert_field (self->fields[3], code, 1, 0); } - return NULL; + return TRUE; } /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */ -const char * +bfd_boolean aarch64_ins_addr_uimm12 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -719,15 +745,16 @@ aarch64_ins_addr_uimm12 (const aarch64_operand *self, insert_field (self->fields[0], code, info->addr.base_regno, 0); /* uimm12 */ insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0); - return NULL; + return TRUE; } /* Encode the address operand for e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ -const char * +bfd_boolean aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ insert_field (FLD_Rn, code, info->addr.base_regno, 0); @@ -736,100 +763,108 @@ aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, insert_field (FLD_Rm, code, info->addr.offset.regno, 0); else insert_field (FLD_Rm, code, 0x1f, 0); - return NULL; + return TRUE; } /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ -const char * +bfd_boolean aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* cond */ insert_field (FLD_cond, code, info->cond->value, 0); - return NULL; + return TRUE; } /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */ -const char * +bfd_boolean aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst, + aarch64_operand_error *detail ATTRIBUTE_UNUSED) { /* op0:op1:CRn:CRm:op2 */ - insert_fields (code, info->sysreg, inst->opcode->mask, 5, + insert_fields (code, info->sysreg.value, inst->opcode->mask, 5, FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0); - return NULL; + return TRUE; } /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ -const char * +bfd_boolean aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op1:op2 */ insert_fields (code, info->pstatefield, inst->opcode->mask, 2, FLD_op2, FLD_op1); - return NULL; + return TRUE; } /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ -const char * +bfd_boolean aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op1:CRn:CRm:op2 */ insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4, FLD_op2, FLD_CRm, FLD_CRn, FLD_op1); - return NULL; + return TRUE; } /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ -const char * +bfd_boolean aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* CRm */ insert_field (FLD_CRm, code, info->barrier->value, 0); - return NULL; + return TRUE; } /* Encode the prefetch operation option operand for e.g. PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ -const char * +bfd_boolean aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* prfop in Rt */ insert_field (FLD_Rt, code, info->prfop->value, 0); - return NULL; + return TRUE; } /* Encode the hint number for instructions that alias HINT but take an operand. */ -const char * +bfd_boolean aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* CRm:op2. */ insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm); - return NULL; + return TRUE; } /* Encode the extended register operand for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ -const char * +bfd_boolean aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { enum aarch64_modifier_kind kind; @@ -844,15 +879,16 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, /* imm3 */ insert_field (FLD_imm3, code, info->shifter.amount, 0); - return NULL; + return TRUE; } /* Encode the shifted register operand for e.g. SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ -const char * +bfd_boolean aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rm */ insert_field (FLD_Rm, code, info->reg.regno, 0); @@ -862,39 +898,41 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, /* imm6 */ insert_field (FLD_imm6, code, info->shifter.amount, 0); - return NULL; + return TRUE; } /* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL], where <simm4> is a 4-bit signed value and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm4> is encoded in the SVE_imm4 field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 + get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0); - return NULL; + return TRUE; } /* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL], where <simm6> is a 6-bit signed value and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm6> is encoded in the SVE_imm6 field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 + get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0); - return NULL; + return TRUE; } /* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL], @@ -902,68 +940,73 @@ aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self, SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6 and imm3 fields, with imm3 being the less-significant part. */ -const char * +bfd_boolean aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 + get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_fields (code, info->addr.offset.imm / factor, 0, 2, FLD_imm3, FLD_SVE_imm6); - return NULL; + return TRUE; } /* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4> is a 4-bit signed number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 << get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0); - return NULL; + return TRUE; } /* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6> is a 6-bit unsigned number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 << get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0); - return NULL; + return TRUE; } /* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (self->fields[1], code, info->addr.offset.regno, 0); - return NULL; + return TRUE; } /* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field, fields[1] specifies the offset register field and fields[2] is a single-bit field that selects SXTW over UXTW. */ -const char * +bfd_boolean aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (self->fields[1], code, info->addr.offset.regno, 0); @@ -971,77 +1014,83 @@ aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self, insert_field (self->fields[2], code, 0, 0); else insert_field (self->fields[2], code, 1, 0); - return NULL; + return TRUE; } /* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a 5-bit unsigned number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int factor = 1 << get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0); - return NULL; + return TRUE; } /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}], where <modifier> is fixed by the instruction and where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -static const char * +static bfd_boolean aarch64_ext_sve_addr_zz (const aarch64_operand *self, - const aarch64_opnd_info *info, aarch64_insn *code) + const aarch64_opnd_info *info, aarch64_insn *code, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_field (self->fields[1], code, info->addr.offset.regno, 0); insert_field (FLD_SVE_msz, code, info->shifter.amount, 0); - return NULL; + return TRUE; } /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors) { - return aarch64_ext_sve_addr_zz (self, info, code); + return aarch64_ext_sve_addr_zz (self, info, code, errors); } /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors) { - return aarch64_ext_sve_addr_zz (self, info, code); + return aarch64_ext_sve_addr_zz (self, info, code, errors); } /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -const char * +bfd_boolean aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors) { - return aarch64_ext_sve_addr_zz (self, info, code); + return aarch64_ext_sve_addr_zz (self, info, code, errors); } /* Encode an SVE ADD/SUB immediate. */ -const char * +bfd_boolean aarch64_ins_sve_aimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (info->shifter.amount == 8) insert_all_fields (self, code, (info->imm.value & 0xff) | 256); @@ -1049,87 +1098,94 @@ aarch64_ins_sve_aimm (const aarch64_operand *self, insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256); else insert_all_fields (self, code, info->imm.value & 0xff); - return NULL; + return TRUE; } /* Encode an SVE CPY/DUP immediate. */ -const char * +bfd_boolean aarch64_ins_sve_asimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - return aarch64_ins_sve_aimm (self, info, code, inst); + return aarch64_ins_sve_aimm (self, info, code, inst, errors); } /* Encode Zn[MM], where MM has a 7-bit triangular encoding. The fields array specifies which field to use for Zn. MM is encoded in the concatenation of imm5 and SVE_tszh, with imm5 being the less significant part. */ -const char * +bfd_boolean aarch64_ins_sve_index (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { unsigned int esize = aarch64_get_qualifier_esize (info->qualifier); insert_field (self->fields[0], code, info->reglane.regno, 0); insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0, 2, FLD_imm5, FLD_SVE_tszh); - return NULL; + return TRUE; } /* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */ -const char * +bfd_boolean aarch64_ins_sve_limm_mov (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - return aarch64_ins_limm (self, info, code, inst); + return aarch64_ins_limm (self, info, code, inst, errors); } /* Encode Zn[MM], where Zn occupies the least-significant part of the field and where MM occupies the most-significant part. The operand-dependent value specifies the number of bits in Zn. */ -const char * +bfd_boolean aarch64_ins_sve_quad_index (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { unsigned int reg_bits = get_operand_specific_data (self); assert (info->reglane.regno < (1U << reg_bits)); unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno; insert_all_fields (self, code, val); - return NULL; + return TRUE; } /* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field to use for Zn. */ -const char * +bfd_boolean aarch64_ins_sve_reglist (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_field (self->fields[0], code, info->reglist.first_regno, 0); - return NULL; + return TRUE; } /* Encode <pattern>{, MUL #<amount>}. The fields array specifies which fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4 field. */ -const char * +bfd_boolean aarch64_ins_sve_scale (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { insert_all_fields (self, code, info->imm.value); insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0); - return NULL; + return TRUE; } /* Encode an SVE shift left immediate. */ -const char * +bfd_boolean aarch64_ins_sve_shlimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { const aarch64_opnd_info *prev_operand; unsigned int esize; @@ -1138,14 +1194,15 @@ aarch64_ins_sve_shlimm (const aarch64_operand *self, prev_operand = &inst->operands[info->idx - 1]; esize = aarch64_get_qualifier_esize (prev_operand->qualifier); insert_all_fields (self, code, 8 * esize + info->imm.value); - return NULL; + return TRUE; } /* Encode an SVE shift right immediate. */ -const char * +bfd_boolean aarch64_ins_sve_shrimm (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { const aarch64_opnd_info *prev_operand; unsigned int esize; @@ -1154,52 +1211,55 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self, prev_operand = &inst->operands[info->idx - 1]; esize = aarch64_get_qualifier_esize (prev_operand->qualifier); insert_all_fields (self, code, 16 * esize - info->imm.value); - return NULL; + return TRUE; } /* Encode a single-bit immediate that selects between #0.5 and #1.0. The fields array specifies which field to use. */ -const char * +bfd_boolean aarch64_ins_sve_float_half_one (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (info->imm.value == 0x3f000000) insert_field (self->fields[0], code, 0, 0); else insert_field (self->fields[0], code, 1, 0); - return NULL; + return TRUE; } /* Encode a single-bit immediate that selects between #0.5 and #2.0. The fields array specifies which field to use. */ -const char * +bfd_boolean aarch64_ins_sve_float_half_two (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (info->imm.value == 0x3f000000) insert_field (self->fields[0], code, 0, 0); else insert_field (self->fields[0], code, 1, 0); - return NULL; + return TRUE; } /* Encode a single-bit immediate that selects between #0.0 and #1.0. The fields array specifies which field to use. */ -const char * +bfd_boolean aarch64_ins_sve_float_zero_one (const aarch64_operand *self, const aarch64_opnd_info *info, aarch64_insn *code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (info->imm.value == 0) insert_field (self->fields[0], code, 0, 0); else insert_field (self->fields[0], code, 1, 0); - return NULL; + return TRUE; } /* Miscellaneous encoding functions. */ @@ -1853,7 +1913,7 @@ convert_to_real_return: Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the matched operand qualifier sequence in *QLF_SEQ. */ -int +bfd_boolean aarch64_opcode_encode (const aarch64_opcode *opcode, const aarch64_inst *inst_ori, aarch64_insn *code, aarch64_opnd_qualifier_t *qlf_seq, @@ -1930,8 +1990,10 @@ aarch64_opcode_encode (const aarch64_opcode *opcode, continue; } opnd = &aarch64_operands[type]; - if (operand_has_inserter (opnd)) - aarch64_insert_operand (opnd, info, &inst->value, inst); + if (operand_has_inserter (opnd) + && !aarch64_insert_operand (opnd, info, &inst->value, inst, + mismatch_detail)) + return FALSE; } /* Call opcode encoders indicated by flags. */ @@ -1947,5 +2009,5 @@ encoding_exit: *code = inst->value; - return 1; + return TRUE; } diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index 0589c9c..0524f91 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -30,15 +30,17 @@ const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *); /* Switch-table-based high-level operand inserter. */ -const char* aarch64_insert_operand (const aarch64_operand *, +bfd_boolean aarch64_insert_operand (const aarch64_operand *, const aarch64_opnd_info *, aarch64_insn *, - const aarch64_inst *); + const aarch64_inst *, + aarch64_operand_error *); /* Operand inserters. */ #define AARCH64_DECL_OPD_INSERTER(x) \ - const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \ - aarch64_insn *, const aarch64_inst *) + bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \ + aarch64_insn *, const aarch64_inst *, \ + aarch64_operand_error *) AARCH64_DECL_OPD_INSERTER (ins_regno); AARCH64_DECL_OPD_INSERTER (ins_reglane); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 3507329..c4ec3ca 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -19688,10 +19688,11 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) return aarch64_opcode_table + value; } -int +bfd_boolean aarch64_extract_operand (const aarch64_operand *self, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors) { /* Use the index as the key. */ int key = self - aarch64_operands; @@ -19742,30 +19743,30 @@ aarch64_extract_operand (const aarch64_operand *self, case 182: case 186: case 189: - return aarch64_ext_regno (self, info, code, inst); + return aarch64_ext_regno (self, info, code, inst, errors); case 8: - return aarch64_ext_regrt_sysins (self, info, code, inst); + return aarch64_ext_regrt_sysins (self, info, code, inst, errors); case 12: - return aarch64_ext_regno_pair (self, info, code, inst); + return aarch64_ext_regno_pair (self, info, code, inst, errors); case 13: - return aarch64_ext_reg_extended (self, info, code, inst); + return aarch64_ext_reg_extended (self, info, code, inst, errors); case 14: - return aarch64_ext_reg_shifted (self, info, code, inst); + return aarch64_ext_reg_shifted (self, info, code, inst, errors); case 19: - return aarch64_ext_ft (self, info, code, inst); + return aarch64_ext_ft (self, info, code, inst, errors); case 30: case 31: case 32: case 191: - return aarch64_ext_reglane (self, info, code, inst); + return aarch64_ext_reglane (self, info, code, inst, errors); case 33: - return aarch64_ext_reglist (self, info, code, inst); + return aarch64_ext_reglist (self, info, code, inst, errors); case 34: - return aarch64_ext_ldst_reglist (self, info, code, inst); + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 35: - return aarch64_ext_ldst_reglist_r (self, info, code, inst); + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 36: - return aarch64_ext_ldst_elemlist (self, info, code, inst); + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); case 37: case 38: case 39: @@ -19799,87 +19800,87 @@ aarch64_extract_operand (const aarch64_operand *self, case 171: case 172: case 173: - return aarch64_ext_imm (self, info, code, inst); + return aarch64_ext_imm (self, info, code, inst, errors); case 41: case 42: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst); + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); case 43: case 44: case 45: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst); + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 46: - return aarch64_ext_shll_imm (self, info, code, inst); + return aarch64_ext_shll_imm (self, info, code, inst, errors); case 49: case 140: - return aarch64_ext_fpimm (self, info, code, inst); + return aarch64_ext_fpimm (self, info, code, inst, errors); case 64: case 147: - return aarch64_ext_limm (self, info, code, inst); + return aarch64_ext_limm (self, info, code, inst, errors); case 65: - return aarch64_ext_aimm (self, info, code, inst); + return aarch64_ext_aimm (self, info, code, inst, errors); case 66: - return aarch64_ext_imm_half (self, info, code, inst); + return aarch64_ext_imm_half (self, info, code, inst, errors); case 67: - return aarch64_ext_fbits (self, info, code, inst); + return aarch64_ext_fbits (self, info, code, inst, errors); case 69: case 70: case 145: - return aarch64_ext_imm_rotate2 (self, info, code, inst); + return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); case 71: case 144: - return aarch64_ext_imm_rotate1 (self, info, code, inst); + return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); case 72: case 73: - return aarch64_ext_cond (self, info, code, inst); + return aarch64_ext_cond (self, info, code, inst, errors); case 79: case 86: - return aarch64_ext_addr_simple (self, info, code, inst); + return aarch64_ext_addr_simple (self, info, code, inst, errors); case 80: - return aarch64_ext_addr_regoff (self, info, code, inst); + return aarch64_ext_addr_regoff (self, info, code, inst, errors); case 81: case 82: case 83: - return aarch64_ext_addr_simm (self, info, code, inst); + return aarch64_ext_addr_simm (self, info, code, inst, errors); case 84: - return aarch64_ext_addr_simm10 (self, info, code, inst); + return aarch64_ext_addr_simm10 (self, info, code, inst, errors); case 85: - return aarch64_ext_addr_uimm12 (self, info, code, inst); + return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); case 87: - return aarch64_ext_addr_offset (self, info, code, inst); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 88: - return aarch64_ext_simd_addr_post (self, info, code, inst); + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 89: - return aarch64_ext_sysreg (self, info, code, inst); + return aarch64_ext_sysreg (self, info, code, inst, errors); case 90: - return aarch64_ext_pstatefield (self, info, code, inst); + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 91: case 92: case 93: case 94: - return aarch64_ext_sysins_op (self, info, code, inst); + return aarch64_ext_sysins_op (self, info, code, inst, errors); case 95: case 96: - return aarch64_ext_barrier (self, info, code, inst); + return aarch64_ext_barrier (self, info, code, inst, errors); case 97: - return aarch64_ext_prfop (self, info, code, inst); + return aarch64_ext_prfop (self, info, code, inst, errors); case 98: - return aarch64_ext_hint (self, info, code, inst); + return aarch64_ext_hint (self, info, code, inst, errors); case 99: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst); + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 100: case 101: case 102: case 103: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst); + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 104: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst); + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 105: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst); + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 106: case 107: case 108: case 109: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst); + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 110: case 111: case 112: @@ -19893,7 +19894,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 120: case 121: case 122: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst); + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 123: case 124: case 125: @@ -19902,49 +19903,49 @@ aarch64_extract_operand (const aarch64_operand *self, case 128: case 129: case 130: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst); + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 131: case 132: case 133: case 134: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 135: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 136: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst); + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 137: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 138: - return aarch64_ext_sve_aimm (self, info, code, inst); + return aarch64_ext_sve_aimm (self, info, code, inst, errors); case 139: - return aarch64_ext_sve_asimm (self, info, code, inst); + return aarch64_ext_sve_asimm (self, info, code, inst, errors); case 141: - return aarch64_ext_sve_float_half_one (self, info, code, inst); + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); case 142: - return aarch64_ext_sve_float_half_two (self, info, code, inst); + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); case 143: - return aarch64_ext_sve_float_zero_one (self, info, code, inst); + return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); case 146: - return aarch64_ext_inv_limm (self, info, code, inst); + return aarch64_ext_inv_limm (self, info, code, inst, errors); case 148: - return aarch64_ext_sve_limm_mov (self, info, code, inst); + return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); case 150: - return aarch64_ext_sve_scale (self, info, code, inst); + return aarch64_ext_sve_scale (self, info, code, inst, errors); case 162: case 163: - return aarch64_ext_sve_shlimm (self, info, code, inst); + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); case 164: case 165: - return aarch64_ext_sve_shrimm (self, info, code, inst); + return aarch64_ext_sve_shrimm (self, info, code, inst, errors); case 183: case 184: case 185: - return aarch64_ext_sve_quad_index (self, info, code, inst); + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); case 187: - return aarch64_ext_sve_index (self, info, code, inst); + return aarch64_ext_sve_index (self, info, code, inst, errors); case 188: case 190: - return aarch64_ext_sve_reglist (self, info, code, inst); + return aarch64_ext_sve_reglist (self, info, code, inst, errors); default: assert (0); abort (); } } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index e7bece9..5994b2b 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -242,31 +242,34 @@ get_expected_qualifier (const aarch64_inst *inst, int i) /* Operand extractors. */ -int +bfd_boolean aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->reg.regno = extract_field (self->fields[0], code, 0); - return 1; + return TRUE; } -int +bfd_boolean aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code ATTRIBUTE_UNUSED, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { assert (info->idx == 1 || info->idx ==3); info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1; - return 1; + return TRUE; } /* e.g. IC <ic_op>{, <Xt>}. */ -int +bfd_boolean aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->reg.regno = extract_field (self->fields[0], code, 0); assert (info->idx == 1 @@ -277,14 +280,15 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, not. */ info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op); - return 1; + return TRUE; } /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */ -int +bfd_boolean aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* regno */ info->reglane.regno = extract_field (self->fields[0], code, @@ -320,7 +324,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, while (++pos <= 3 && (value & 0x1) == 0) value >>= 1; if (pos > 3) - return 0; + return FALSE; info->qualifier = get_sreg_qualifier_from_value (pos); info->reglane.index = (unsigned) (value >> 1); } @@ -337,7 +341,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.regno &= 0x1f; break; default: - return 0; + return FALSE; } } else if (inst->opcode->iclass == cryptosm3) @@ -369,38 +373,40 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_field (FLD_H, code, 0); break; default: - return 0; + return FALSE; } if (inst->opcode->op == OP_FCMLA_ELEM) { /* Complex operand takes two elements. */ if (info->reglane.index & 1) - return 0; + return FALSE; info->reglane.index /= 2; } } - return 1; + return TRUE; } -int +bfd_boolean aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* R */ info->reglist.first_regno = extract_field (self->fields[0], code, 0); /* len */ info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1; - return 1; + return TRUE; } /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */ -int +bfd_boolean aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; /* Number of elements in each structure to be loaded/stored. */ @@ -431,20 +437,21 @@ aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, value = extract_field (FLD_opcode, code, 0); /* PR 21595: Check for a bogus value. */ if (value >= ARRAY_SIZE (data)) - return 0; + return FALSE; if (expected_num != data[value].num_elements || data[value].is_reserved) - return 0; + return FALSE; info->reglist.num_regs = data[value].num_regs; - return 1; + return TRUE; } /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all lanes instructions. */ -int +bfd_boolean aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -462,15 +469,16 @@ aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1) info->reglist.num_regs = 2; - return 1; + return TRUE; } /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD load/store single element instructions. */ -int +bfd_boolean aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_field field = {0, 0}; aarch64_insn QSsize; /* fields Q:S:size. */ @@ -493,7 +501,7 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, case 0x1: if (QSsize & 0x1) /* UND. */ - return 0; + return FALSE; info->qualifier = AARCH64_OPND_QLF_S_H; /* Index encoded in "Q:S:size<1>". */ info->reglist.index = QSsize >> 1; @@ -501,7 +509,7 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, case 0x2: if ((QSsize >> 1) & 0x1) /* UND. */ - return 0; + return FALSE; if ((QSsize & 0x1) == 0) { info->qualifier = AARCH64_OPND_QLF_S_S; @@ -512,14 +520,14 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, { if (extract_field (FLD_S, code, 0)) /* UND */ - return 0; + return FALSE; info->qualifier = AARCH64_OPND_QLF_S_D; /* Index encoded in "Q". */ info->reglist.index = QSsize >> 3; } break; default: - return 0; + return FALSE; } info->reglist.has_index = 1; @@ -529,17 +537,18 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4); - return 1; + return TRUE; } /* Decode fields immh:immb and/or Q for e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift> or SSHR <V><d>, <V><n>, #<shift>. */ -int +bfd_boolean aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int pos; aarch64_insn Q, imm, immh; @@ -547,7 +556,7 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, immh = extract_field (FLD_immh, code, 0); if (immh == 0) - return 0; + return FALSE; imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb); pos = 4; /* Get highest set bit in immh. */ @@ -595,14 +604,15 @@ aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, 1xxx (UInt(immh:immb)-64) */ info->imm.value = imm - (8 << pos); - return 1; + return TRUE; } /* Decode shift immediate for e.g. sshr (imm). */ -int +bfd_boolean aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int64_t imm; aarch64_insn val; @@ -612,18 +622,19 @@ aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, case 0: imm = 8; break; case 1: imm = 16; break; case 2: imm = 32; break; - default: return 0; + default: return FALSE; } info->imm.value = imm; - return 1; + return TRUE; } /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. value in the field(s) will be extracted as unsigned immediate value. */ -int +bfd_boolean aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int64_t imm; @@ -639,28 +650,30 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, imm <<= 12; info->imm.value = imm; - return 1; + return TRUE; } /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */ -int +bfd_boolean aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors) { - aarch64_ext_imm (self, info, code, inst); + aarch64_ext_imm (self, info, code, inst, errors); info->shifter.kind = AARCH64_MOD_LSL; info->shifter.amount = extract_field (FLD_hw, code, 0) << 4; - return 1; + return TRUE; } /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g. MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */ -int +bfd_boolean aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t imm; enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier; @@ -704,7 +717,7 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ - default: assert (0); return 0; + default: assert (0); return FALSE; } /* 00: 0; 01: 8; 10:16; 11:24. */ info->shifter.amount = extract_field_2 (&field, code, 0) << 3; @@ -717,63 +730,68 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, break; default: assert (0); - return 0; + return FALSE; } - return 1; + return TRUE; } /* Decode an 8-bit floating-point immediate. */ -int +bfd_boolean aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->imm.value = extract_all_fields (self, code); info->imm.is_fp = 1; - return 1; + return TRUE; } /* Decode a 1-bit rotate immediate (#90 or #270). */ -int +bfd_boolean aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = extract_field (self->fields[0], code, 0); assert (rot < 2U); info->imm.value = rot * 180 + 90; - return 1; + return TRUE; } /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */ -int +bfd_boolean aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint64_t rot = extract_field (self->fields[0], code, 0); assert (rot < 4U); info->imm.value = rot * 90; - return 1; + return TRUE; } /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */ -int +bfd_boolean aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->imm.value = 64- extract_field (FLD_scale, code, 0); - return 1; + return TRUE; } /* Decode arithmetic immediate for e.g. SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */ -int +bfd_boolean aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -781,18 +799,18 @@ aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, /* shift */ value = extract_field (FLD_shift, code, 0); if (value >= 2) - return 0; + return FALSE; info->shifter.amount = value ? 12 : 0; /* imm12 (unsigned) */ info->imm.value = extract_field (FLD_imm12, code, 0); - return 1; + return TRUE; } /* Return true if VALUE is a valid logical immediate encoding, storing the decoded value in *RESULT if so. ESIZE is the number of bytes in the decoded immediate. */ -static int +static bfd_boolean decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) { uint64_t imm, mask; @@ -820,7 +838,7 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break; case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break; case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break; - default: return 0; + default: return FALSE; } mask = (1ull << simd_size) - 1; /* Top bits are IGNORED. */ @@ -828,11 +846,11 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) } if (simd_size > esize * 8) - return 0; + return FALSE; /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */ if (S == simd_size - 1) - return 0; + return FALSE; /* S+1 consecutive bits to 1. */ /* NOTE: S can't be 63 due to detection above. */ imm = (1ull << (S + 1)) - 1; @@ -858,14 +876,15 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); - return 1; + return TRUE; } /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */ -int +bfd_boolean aarch64_ext_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { uint32_t esize; aarch64_insn value; @@ -877,23 +896,25 @@ aarch64_ext_limm (const aarch64_operand *self, } /* Decode a logical immediate for the BIC alias of AND (etc.). */ -int +bfd_boolean aarch64_ext_inv_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - if (!aarch64_ext_limm (self, info, code, inst)) - return 0; + if (!aarch64_ext_limm (self, info, code, inst, errors)) + return FALSE; info->imm.value = ~info->imm.value; - return 1; + return TRUE; } /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}] or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */ -int +bfd_boolean aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - const aarch64_insn code, const aarch64_inst *inst) + const aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -913,7 +934,7 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, case 0: qualifier = AARCH64_OPND_QLF_S_S; break; case 1: qualifier = AARCH64_OPND_QLF_S_D; break; case 2: qualifier = AARCH64_OPND_QLF_S_Q; break; - default: return 0; + default: return FALSE; } info->qualifier = qualifier; } @@ -922,31 +943,33 @@ aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, /* opc1:size */ value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size); if (value > 0x4) - return 0; + return FALSE; info->qualifier = get_sreg_qualifier_from_value (value); } - return 1; + return TRUE; } /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */ -int +bfd_boolean aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* Rn */ info->addr.base_regno = extract_field (FLD_Rn, code, 0); - return 1; + return TRUE; } /* Decode the address operand for e.g. stlur <Xt>, [<Xn|SP>{, <amount>}]. */ -int +bfd_boolean aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->qualifier = get_expected_qualifier (inst, info->idx); @@ -960,15 +983,16 @@ aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, info->addr.writeback = 1; info->addr.preind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ -int +bfd_boolean aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn S, value; @@ -1004,13 +1028,14 @@ aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, info->shifter.amount_present = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */ -int +bfd_boolean aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn imm; info->qualifier = get_expected_qualifier (inst, info->idx); @@ -1039,14 +1064,15 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.postind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */ -int +bfd_boolean aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int shift; info->qualifier = get_expected_qualifier (inst, info->idx); @@ -1055,14 +1081,15 @@ aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.base_regno = extract_field (self->fields[0], code, 0); /* uimm12 */ info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift; - return 1; + return TRUE; } /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */ -int +bfd_boolean aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn imm; @@ -1076,15 +1103,16 @@ aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, info->addr.writeback = 1; info->addr.preind = 1; } - return 1; + return TRUE; } /* Decode the address operand for e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */ -int +bfd_boolean aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst) + aarch64_insn code, const aarch64_inst *inst, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* The opcode dependent area stores the number of elements in each structure to be loaded/stored. */ @@ -1110,57 +1138,61 @@ aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, info->addr.offset.is_reg = 1; info->addr.writeback = 1; - return 1; + return TRUE; } /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */ -int +bfd_boolean aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED) + aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; /* cond */ value = extract_field (FLD_cond, code, 0); info->cond = get_cond_from_value (value); - return 1; + return TRUE; } /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */ -int +bfd_boolean aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* op0:op1:CRn:CRm:op2 */ - info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, - FLD_CRm, FLD_op2); + info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn, + FLD_CRm, FLD_op2); return 1; } /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */ -int +bfd_boolean aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int i; /* op1:op2 */ info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2); for (i = 0; aarch64_pstatefields[i].name != NULL; ++i) if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield) - return 1; + return TRUE; /* Reserved value in <pstatefield>. */ - return 0; + return FALSE; } /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */ -int +bfd_boolean aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int i; aarch64_insn value; @@ -1176,7 +1208,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break; case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break; case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break; - default: assert (0); return 0; + default: assert (0); return FALSE; } for (i = 0; sysins_ops[i].name != NULL; ++i) @@ -1187,46 +1219,49 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, info->sysins_op->name, (unsigned)info->sysins_op->value, aarch64_sys_ins_reg_has_xt (info->sysins_op), i); - return 1; + return TRUE; } - return 0; + return FALSE; } /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */ -int +bfd_boolean aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* CRm */ info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0); - return 1; + return TRUE; } /* Decode the prefetch operation option operand for e.g. PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */ -int +bfd_boolean aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, - aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED) + aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* prfop in Rt */ info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0); - return 1; + return TRUE; } /* Decode the hint number for an alias taking an operand. Set info->hint_option to the matching name/value pair in aarch64_hint_options. */ -int +bfd_boolean aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { /* CRm:op2. */ unsigned hint_number; @@ -1239,20 +1274,21 @@ aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, if (hint_number == aarch64_hint_options[i].value) { info->hint_option = &(aarch64_hint_options[i]); - return 1; + return TRUE; } } - return 0; + return FALSE; } /* Decode the extended register operand for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */ -int +bfd_boolean aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -1276,16 +1312,17 @@ aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, || info->shifter.kind == AARCH64_MOD_SXTX)) info->qualifier = AARCH64_OPND_QLF_X; - return 1; + return TRUE; } /* Decode the shifted register operand for e.g. SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */ -int +bfd_boolean aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { aarch64_insn value; @@ -1299,21 +1336,21 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, && inst->opcode->iclass != log_shift) /* ROR is not available for the shifted register operand in arithmetic instructions. */ - return 0; + return FALSE; /* imm6 */ info->shifter.amount = extract_field (FLD_imm6, code, 0); /* This makes the constraint checking happy. */ info->shifter.operator_present = 1; - return 1; + return TRUE; } /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL], where <offset> is given by the OFFSET parameter and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that holds <base>. */ -static int +static bfd_boolean aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, int64_t offset) @@ -1328,17 +1365,18 @@ aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, info->shifter.amount = 1; info->shifter.operator_present = (info->addr.offset.imm != 0); info->shifter.amount_present = FALSE; - return 1; + return TRUE; } /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL], where <simm4> is a 4-bit signed value and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm4> is encoded in the SVE_imm4 field. */ -int +bfd_boolean aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset; @@ -1351,10 +1389,11 @@ aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, where <simm6> is a 6-bit signed value and where <factor> is 1 plus SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm6> is encoded in the SVE_imm6 field. */ -int +bfd_boolean aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset; @@ -1368,11 +1407,12 @@ aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, SELF's operand-dependent value. fields[0] specifies the field that holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6 and imm3 fields, with imm3 being the less-significant part. */ -int +bfd_boolean aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset; @@ -1384,7 +1424,7 @@ aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset> is given by the OFFSET parameter and where <shift> is SELF's operand- dependent value. fields[0] specifies the base register field <base>. */ -static int +static bfd_boolean aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, int64_t offset) @@ -1396,16 +1436,17 @@ aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, info->addr.preind = TRUE; info->shifter.operator_present = FALSE; info->shifter.amount_present = FALSE; - return 1; + return TRUE; } /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4> is a 4-bit signed number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -int +bfd_boolean aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3); return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); @@ -1414,10 +1455,11 @@ aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6> is a 6-bit unsigned number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -int +bfd_boolean aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset = extract_field (FLD_SVE_imm6, code, 0); return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); @@ -1426,16 +1468,17 @@ aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -int +bfd_boolean aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int index_regno; index_regno = extract_field (self->fields[1], code, 0); if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0) - return 0; + return FALSE; info->addr.base_regno = extract_field (self->fields[0], code, 0); info->addr.offset.regno = index_regno; @@ -1446,17 +1489,18 @@ aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, info->shifter.amount = get_operand_specific_data (self); info->shifter.operator_present = (info->shifter.amount != 0); info->shifter.amount_present = (info->shifter.amount != 0); - return 1; + return TRUE; } /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field, fields[1] specifies the offset register field and fields[2] is a single-bit field that selects SXTW over UXTW. */ -int +bfd_boolean aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->addr.base_regno = extract_field (self->fields[0], code, 0); info->addr.offset.regno = extract_field (self->fields[1], code, 0); @@ -1470,16 +1514,17 @@ aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, info->shifter.amount = get_operand_specific_data (self); info->shifter.operator_present = TRUE; info->shifter.amount_present = (info->shifter.amount != 0); - return 1; + return TRUE; } /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a 5-bit unsigned number and where <shift> is SELF's operand-dependent value. fields[0] specifies the base register field. */ -int +bfd_boolean aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int offset = extract_field (FLD_imm5, code, 0); return aarch64_ext_sve_addr_reg_imm (self, info, code, offset); @@ -1489,7 +1534,7 @@ aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, where <modifier> is given by KIND and where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -static int +static bfd_boolean aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, enum aarch64_modifier_kind kind) { @@ -1503,16 +1548,17 @@ aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, info->shifter.operator_present = (kind != AARCH64_MOD_LSL || info->shifter.amount != 0); info->shifter.amount_present = (info->shifter.amount != 0); - return 1; + return TRUE; } /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -int +bfd_boolean aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL); } @@ -1520,10 +1566,11 @@ aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -int +bfd_boolean aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW); } @@ -1531,17 +1578,18 @@ aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where <msz> is a 2-bit unsigned number. fields[0] specifies the base register field and fields[1] specifies the offset register field. */ -int +bfd_boolean aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW); } /* Finish decoding an SVE arithmetic immediate, given that INFO already has the raw field value and that the low 8 bits decode to VALUE. */ -static int +static bfd_boolean decode_sve_aimm (aarch64_opnd_info *info, int64_t value) { info->shifter.kind = AARCH64_MOD_LSL; @@ -1557,82 +1605,88 @@ decode_sve_aimm (aarch64_opnd_info *info, int64_t value) info->shifter.operator_present = (info->shifter.amount != 0); info->shifter.amount_present = (info->shifter.amount != 0); info->imm.value = value; - return 1; + return TRUE; } /* Decode an SVE ADD/SUB immediate. */ -int +bfd_boolean aarch64_ext_sve_aimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - return (aarch64_ext_imm (self, info, code, inst) + return (aarch64_ext_imm (self, info, code, inst, errors) && decode_sve_aimm (info, (uint8_t) info->imm.value)); } /* Decode an SVE CPY/DUP immediate. */ -int +bfd_boolean aarch64_ext_sve_asimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { - return (aarch64_ext_imm (self, info, code, inst) + return (aarch64_ext_imm (self, info, code, inst, errors) && decode_sve_aimm (info, (int8_t) info->imm.value)); } /* Decode a single-bit immediate that selects between #0.5 and #1.0. The fields array specifies which field to use. */ -int +bfd_boolean aarch64_ext_sve_float_half_one (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (extract_field (self->fields[0], code, 0)) info->imm.value = 0x3f800000; else info->imm.value = 0x3f000000; info->imm.is_fp = TRUE; - return 1; + return TRUE; } /* Decode a single-bit immediate that selects between #0.5 and #2.0. The fields array specifies which field to use. */ -int +bfd_boolean aarch64_ext_sve_float_half_two (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (extract_field (self->fields[0], code, 0)) info->imm.value = 0x40000000; else info->imm.value = 0x3f000000; info->imm.is_fp = TRUE; - return 1; + return TRUE; } /* Decode a single-bit immediate that selects between #0.0 and #1.0. The fields array specifies which field to use. */ -int +bfd_boolean aarch64_ext_sve_float_zero_one (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { if (extract_field (self->fields[0], code, 0)) info->imm.value = 0x3f800000; else info->imm.value = 0x0; info->imm.is_fp = TRUE; - return 1; + return TRUE; } /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields array specifies which field to use for Zn. MM is encoded in the concatenation of imm5 and SVE_tszh, with imm5 being the less significant part. */ -int +bfd_boolean aarch64_ext_sve_index (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { int val; @@ -1643,66 +1697,69 @@ aarch64_ext_sve_index (const aarch64_operand *self, while ((val & 1) == 0) val /= 2; info->reglane.index = val / 2; - return 1; + return TRUE; } /* Decode a logical immediate for the MOV alias of SVE DUPM. */ -int +bfd_boolean aarch64_ext_sve_limm_mov (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, + aarch64_operand_error *errors) { int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier); - return (aarch64_ext_limm (self, info, code, inst) + return (aarch64_ext_limm (self, info, code, inst, errors) && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize)); } /* Decode Zn[MM], where Zn occupies the least-significant part of the field and where MM occupies the most-significant part. The operand-dependent value specifies the number of bits in Zn. */ -int +bfd_boolean aarch64_ext_sve_quad_index (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { unsigned int reg_bits = get_operand_specific_data (self); unsigned int val = extract_all_fields (self, code); info->reglane.regno = val & ((1 << reg_bits) - 1); info->reglane.index = val >> reg_bits; - return 1; + return TRUE; } /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field to use for Zn. The opcode-dependent value specifies the number of registers in the list. */ -int +bfd_boolean aarch64_ext_sve_reglist (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst ATTRIBUTE_UNUSED) + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { info->reglist.first_regno = extract_field (self->fields[0], code, 0); info->reglist.num_regs = get_opcode_dependent_value (inst->opcode); - return 1; + return TRUE; } /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4 field. */ -int +bfd_boolean aarch64_ext_sve_scale (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, aarch64_operand_error *errors) { int val; - if (!aarch64_ext_imm (self, info, code, inst)) - return 0; + if (!aarch64_ext_imm (self, info, code, inst, errors)) + return FALSE; val = extract_field (FLD_SVE_imm4, code, 0); info->shifter.kind = AARCH64_MOD_MUL; info->shifter.amount = val + 1; info->shifter.operator_present = (val != 0); info->shifter.amount_present = (val != 0); - return 1; + return TRUE; } /* Return the top set bit in VALUE, which is expected to be relatively @@ -1716,31 +1773,31 @@ get_top_bit (uint64_t value) } /* Decode an SVE shift-left immediate. */ -int +bfd_boolean aarch64_ext_sve_shlimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, aarch64_operand_error *errors) { - if (!aarch64_ext_imm (self, info, code, inst) + if (!aarch64_ext_imm (self, info, code, inst, errors) || info->imm.value == 0) - return 0; + return FALSE; info->imm.value -= get_top_bit (info->imm.value); - return 1; + return TRUE; } /* Decode an SVE shift-right immediate. */ -int +bfd_boolean aarch64_ext_sve_shrimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, - const aarch64_inst *inst) + const aarch64_inst *inst, aarch64_operand_error *errors) { - if (!aarch64_ext_imm (self, info, code, inst) + if (!aarch64_ext_imm (self, info, code, inst, errors) || info->imm.value == 0) - return 0; + return FALSE; info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value; - return 1; + return TRUE; } /* Bitfields that are commonly used to encode certain operands' information @@ -2474,8 +2531,9 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias) } } -static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, - aarch64_inst *, int); +static bfd_boolean +aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, + aarch64_inst *, int, aarch64_operand_error *errors); /* Given the instruction information in *INST, check if the instruction has any alias form that can be used to represent *INST. If the answer is yes, @@ -2531,7 +2589,8 @@ static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */ static void -determine_disassembling_preference (struct aarch64_inst *inst) +determine_disassembling_preference (struct aarch64_inst *inst, + aarch64_operand_error *errors) { const aarch64_opcode *opcode; const aarch64_opcode *alias; @@ -2606,7 +2665,7 @@ determine_disassembling_preference (struct aarch64_inst *inst) /* Directly decode the alias opcode. */ aarch64_inst temp; memset (&temp, '\0', sizeof (aarch64_inst)); - if (aarch64_opcode_decode (alias, inst->value, &temp, 1) == 1) + if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1) { DEBUG_TRACE ("succeed with %s via direct decoding", alias->name); memcpy (inst, &temp, sizeof (aarch64_inst)); @@ -2723,9 +2782,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) determined and used to disassemble CODE; this is done just before the return. */ -static int +static bfd_boolean aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, - aarch64_inst *inst, int noaliases_p) + aarch64_inst *inst, int noaliases_p, + aarch64_operand_error *errors) { int i; @@ -2781,7 +2841,8 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, break; opnd = &aarch64_operands[type]; if (operand_has_extractor (opnd) - && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst))) + && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst, + errors))) { DEBUG_TRACE ("operand decoder FAIL at operand %d", i); goto decode_fail; @@ -2804,9 +2865,9 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, alias and should be disassembled in the form of its alias instead. If the answer is yes, *INST will be updated. */ if (!noaliases_p) - determine_disassembling_preference (inst); + determine_disassembling_preference (inst, errors); DEBUG_TRACE ("SUCCESS"); - return 1; + return TRUE; } else { @@ -2814,7 +2875,7 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code, } decode_fail: - return 0; + return FALSE; } /* This does some user-friendly fix-up to *INST. It is currently focus on @@ -2846,7 +2907,8 @@ user_friendly_fixup (aarch64_inst *inst) int aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, - bfd_boolean noaliases_p) + bfd_boolean noaliases_p, + aarch64_operand_error *errors) { const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); @@ -2873,7 +2935,7 @@ aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, { /* But only one opcode can be decoded successfully for, as the decoding routine will check the constraint carefully. */ - if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1) + if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1) return ERR_OK; opcode = aarch64_find_next_opcode (opcode); } @@ -2988,7 +3050,8 @@ print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, static void print_insn_aarch64_word (bfd_vma pc, uint32_t word, - struct disassemble_info *info) + struct disassemble_info *info, + aarch64_operand_error *errors) { static const char *err_msg[6] = { @@ -3015,7 +3078,7 @@ print_insn_aarch64_word (bfd_vma pc, addresses, since the addend is not currently pc-relative. */ pc = 0; - ret = aarch64_decode_insn (word, &inst, no_aliases); + ret = aarch64_decode_insn (word, &inst, no_aliases, errors); if (((word >> 21) & 0x3ff) == 1) { @@ -3068,7 +3131,8 @@ aarch64_symbol_is_valid (asymbol * sym, static void print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, uint32_t word, - struct disassemble_info *info) + struct disassemble_info *info, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) { switch (info->bytes_per_chunk) { @@ -3132,10 +3196,12 @@ print_insn_aarch64 (bfd_vma pc, { bfd_byte buffer[INSNLEN]; int status; - void (*printer) (bfd_vma, uint32_t, struct disassemble_info *); + void (*printer) (bfd_vma, uint32_t, struct disassemble_info *, + aarch64_operand_error *); bfd_boolean found = FALSE; unsigned int size = 4; unsigned long data; + aarch64_operand_error errors; if (info->disassembler_options) { @@ -3253,7 +3319,7 @@ print_insn_aarch64 (bfd_vma pc, data = bfd_get_bits (buffer, size * 8, info->display_endian == BFD_ENDIAN_BIG); - (*printer) (pc, data, info); + (*printer) (pc, data, info, &errors); return size; } diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 2a1ec29..b09a5ee 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -50,14 +50,17 @@ const aarch64_opcode* aarch64_find_next_alias_opcode (const aarch64_opcode *); /* Switch-table-based high-level operand extractor. */ -int aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *, - const aarch64_insn, const aarch64_inst *); +bfd_boolean +aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *, + const aarch64_insn, const aarch64_inst *, + aarch64_operand_error *); /* Operand extractors. */ #define AARCH64_DECL_OPD_EXTRACTOR(x) \ - int aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \ - const aarch64_insn, const aarch64_inst *) + bfd_boolean aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \ + const aarch64_insn, const aarch64_inst *, \ + aarch64_operand_error *) AARCH64_DECL_OPD_EXTRACTOR (ext_regno); AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair); diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index 994805f..2527d93 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -984,10 +984,11 @@ print_operand_inserter (void) printf ("Enter print_operand_inserter\n"); printf ("\n"); - printf ("const char*\n"); + printf ("bfd_boolean\n"); printf ("aarch64_insert_operand (const aarch64_operand *self,\n\ const aarch64_opnd_info *info,\n\ - aarch64_insn *code, const aarch64_inst *inst)\n"); + aarch64_insn *code, const aarch64_inst *inst,\n\ + aarch64_operand_error *errors)\n"); printf ("{\n"); printf (" /* Use the index as the key. */\n"); printf (" int key = self - aarch64_operands;\n"); @@ -1017,7 +1018,7 @@ print_operand_inserter (void) opnd2->processed = 1; } } - printf (" return aarch64_%s (self, info, code, inst);\n", + printf (" return aarch64_%s (self, info, code, inst, errors);\n", opnd->inserter); } } @@ -1040,10 +1041,11 @@ print_operand_extractor (void) printf ("Enter print_operand_extractor\n"); printf ("\n"); - printf ("int\n"); + printf ("bfd_boolean\n"); printf ("aarch64_extract_operand (const aarch64_operand *self,\n\ aarch64_opnd_info *info,\n\ - aarch64_insn code, const aarch64_inst *inst)\n"); + aarch64_insn code, const aarch64_inst *inst,\n\ + aarch64_operand_error *errors)\n"); printf ("{\n"); printf (" /* Use the index as the key. */\n"); printf (" int key = self - aarch64_operands;\n"); @@ -1073,7 +1075,7 @@ print_operand_extractor (void) opnd2->processed = 1; } } - printf (" return aarch64_%s (self, info, code, inst);\n", + printf (" return aarch64_%s (self, info, code, inst, errors);\n", opnd->extractor); } } diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e2c24cf..c688b7c7 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3556,7 +3556,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SYSREG: for (i = 0; aarch64_sys_regs[i].name; ++i) - if (aarch64_sys_regs[i].value == opnd->sysreg + if (aarch64_sys_regs[i].value == opnd->sysreg.value && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])) break; if (aarch64_sys_regs[i].name) @@ -3564,7 +3564,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, else { /* Implementation defined system register. */ - unsigned int value = opnd->sysreg; + unsigned int value = opnd->sysreg.value; snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3, (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf, value & 0x7); |