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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/arc-opc.c4
2 files changed, 6 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b510736..c9cf9ed 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-23 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-opc.c: Correct description of availability of NPS400
+ features.
+
2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index df18167..ad50ebc 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -27,9 +27,7 @@
#include "libiberty.h"
/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
- instructions. Support for this target is available when binutils is
- configured and built for the 'arc*-mellanox-*-*' target. As far as
- possible all ARC NPS400 features are built into all ARC target builds as
+ instructions. All NPS400 features are built into all ARC target builds as
this reduces the chances that regressions might creep in. */
/* Insert RB register into a 32-bit opcode. */