diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex.h | 8 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 8 |
3 files changed, 23 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4895fc3..7def411 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,16 @@ 2018-09-14 H.J. Lu <hongjiu.lu@intel.com> + PR binutils/23655 + * i386-dis-evex.h (evex_table): Replace Eq with Edqa for + vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ. + * i386-dis.c (Edqa): New. + (dqa_mode): Likewise. + (intel_operand_size): Handle dqa_mode as m_mode. + (OP_E_register): Handle dqa_mode as dq_mode. + (OP_E_memory): Set shift for dqa_mode based on address_mode. + +2018-09-14 H.J. Lu <hongjiu.lu@intel.com> + * i386-dis.c (OP_E_memory): Reformat. 2018-09-14 Jan Beulich <jbeulich@suse.com> diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 8b82578..f59c7cc 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -3046,12 +3046,12 @@ static const struct dis386 evex_table[][256] = { /* EVEX_W_0F2A_P_1 */ { { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 }, }, /* EVEX_W_0F2A_P_3 */ { { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 }, }, /* EVEX_W_0F2B_P_0 */ { @@ -3383,7 +3383,7 @@ static const struct dis386 evex_table[][256] = { /* EVEX_W_0F7B_P_1 */ { { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Ed }, 0 }, - { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtusi2ss%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 }, }, /* EVEX_W_0F7B_P_2 */ { @@ -3393,7 +3393,7 @@ static const struct dis386 evex_table[][256] = { /* EVEX_W_0F7B_P_3 */ { { "vcvtusi2sd%LQ", { XMScalar, VexScalar, Ed }, 0 }, - { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Eq }, 0 }, + { "vcvtusi2sd%LQ", { XMScalar, VexScalar, EXxEVexR, Edqa }, 0 }, }, /* EVEX_W_0F7E_P_1 */ { diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index f453989..83c6107 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -260,6 +260,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } #define Edqd { OP_E, dqd_mode } +#define Edqa { OP_E, dqa_mode } #define Eq { OP_E, q_mode } #define indirEv { OP_indirE, indir_v_mode } #define indirEp { OP_indirE, f_mode } @@ -591,6 +592,8 @@ enum dw_mode, /* registers like dq_mode, memory like d_mode. */ dqd_mode, + /* operand size depends on the W bit as well as address mode. */ + dqa_mode, /* normal vex mode */ vex_mode, /* 128bit vex mode */ @@ -14805,6 +14808,7 @@ intel_operand_size (int bytemode, int sizeflag) case q_swap_mode: oappend ("QWORD PTR "); break; + case dqa_mode: case m_mode: if (address_mode == mode_64bit) oappend ("QWORD PTR "); @@ -15163,6 +15167,7 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: + case dqa_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -15305,6 +15310,9 @@ OP_E_memory (int bytemode, int sizeflag) case xmm_mb_mode: shift = 0; break; + case dqa_mode: + shift = address_mode == mode_64bit ? 3 : 2; + break; default: abort (); } |