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-rw-r--r--opcodes/ChangeLog94
-rw-r--r--opcodes/Makefile.am2
-rw-r--r--opcodes/Makefile.in10
-rw-r--r--opcodes/alpha-opc.c8
-rw-r--r--opcodes/arm-dis.c27
-rw-r--r--opcodes/arm-opc.h140
-rw-r--r--opcodes/dis-buf.c11
-rw-r--r--opcodes/dis-init.c2
-rw-r--r--opcodes/disassemble.c18
-rw-r--r--opcodes/h8300-dis.c19
-rw-r--r--opcodes/i370-opc.c1
-rw-r--r--opcodes/m32r-asm.c12
-rw-r--r--opcodes/m32r-desc.c181
-rw-r--r--opcodes/m32r-desc.h44
-rw-r--r--opcodes/m32r-dis.c19
-rw-r--r--opcodes/m32r-ibld.c36
-rw-r--r--opcodes/m32r-opc.c141
-rw-r--r--opcodes/m32r-opc.h62
-rw-r--r--opcodes/m32r-opinst.c199
-rw-r--r--opcodes/mips-opc.c2
-rw-r--r--opcodes/mmix-opc.c23
-rw-r--r--opcodes/openrisc-asm.c65
-rw-r--r--opcodes/pj-opc.c2
-rw-r--r--opcodes/ppc-opc.c49
-rw-r--r--opcodes/sh-dis.c126
-rw-r--r--opcodes/sh-opc.h192
-rw-r--r--opcodes/z8k-dis.c53
-rw-r--r--opcodes/z8k-opc.h226
-rw-r--r--opcodes/z8kgen.c274
29 files changed, 1414 insertions, 624 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2f613cb..7bf5b45 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,93 @@
+2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r-opc.c: Regenerate.
+
+2003-12-14 Mark Mitchell <mark@codesourcery.com>
+
+ * arm-opc.h (arm_opcodes): Put V6 instructions before XScale
+ instructions.
+
+2003-12-13 Hans-Peter Nilsson <hp@bitrange.com>
+
+ * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE,
+ SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE
+ and SWYM_INSN_BYTE instead of raw numbers.
+
+2003-12-10 Zack Weinberg <zack@codesourcery.com>
+
+ * ppc-opc.c (MO): Make optional.
+ (RAO, RSO, SHO): New optional forms of RA, RS, SH operands.
+ (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional.
+
+2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com>
+ Mark Mitchell <mark@codesourcery.com>
+ Richard Earnshaw <rearnsha@arm.com>
+
+ * arm-dis.c (print_arm_insn): Add 'W' macro.
+ * arm-opc.h (arm_opcodes): Add V6 instructions.
+ (thumb_opcodes): Likewise.
+
+2003-12-04 Alan Modra <amodra@bigpond.net.au>
+
+ * openrisc-asm.c: Regenerate.
+ * pj-opc.c: Update copyright date.
+
+2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
+ * m32r-opinst.c: Regenerate.
+
+2003-12-02 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh-opc.h: Add support for sh4a and no-fpu variants.
+ * sh-dis.c: Ditto.
+
+2003-12-02 Kazu Hirata <kazu@cs.umass.edu>
+
+ * alpha-opc.c: Remove ARGSUSED.
+ * i370-opc.c: Likewise.
+ * ppc-opc.c: Likewise.
+
+2003-12-02 Alan Modra <amodra@bigpond.net.au>
+
+ * Makefile.am: Run "make dep-am".
+ * Makefile.in: Regenerate.
+
+2003-11-28 Christian Groessler <chris@groessler.org>
+
+ * z8k-dis.c: Convert to ISO C90.
+ * z8kgen.c: Convert to ISO C90.
+ (opt): Move long opcode for "ldb rdb,imm8" after short one, now
+ the short one is created when assembling.
+ * z8k-opc.h: Regenerate with new z8kgen.c.
+
+2003-11-19 Kazu Hirata <kazu@cs.umass.edu>
+
+ * h8300-dis.c (print_colon_thingie): Remove.
+
+2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
+
+ * mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and
+ "dlca".
+
+2003-11-14 Nick Clifton <nickc@redhat.com>
+
+ * dis-init.c (init_disassemble_info): Initialise
+ symbol_is_valid field.
+ * dis-buf.c (generic_symbol_is_valid): New function. Always
+ returns TRUE.
+ * arm-dis.c (arm_symbol_is_valid): New function. Return FALSE
+ for ARM ELF mapping symbols.
+ * disassemble.c (disassemble_init_for_target): Set
+ symbol_is_valid field to arm_symbol_is_valid of the target is
+ an ARM.
+
2003-11-05 H.J. Lu <hongjiu.lu@intel.com>
* m68k-opc.c (m68k_opcodes): Reorder "fmovel".
@@ -15,7 +105,7 @@
* m68hc11-dis.c: Convert to ISO C90 prototypes.
2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com>
- Bernardo Innocenti <bernie@develer.com>
+ Bernardo Innocenti <bernie@develer.com>
* m68k-dis.c: Add MCFv4/MCF5528x support.
* m68k-opc.c: Likewise.
@@ -75,7 +165,7 @@
* v850-dis.c (disassemble): Accept bfd_mach_v850e1.
* v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions.
-
+
2003-09-04 Alan Modra <amodra@bigpond.net.au>
* ppc-dis.c (struct dis_private): New.
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 6859a9d..e227b1f 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -558,7 +558,7 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
- $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 57aee2d..de427ea 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -1,6 +1,6 @@
-# Makefile.in generated automatically by automake 1.4 from Makefile.am
+# Makefile.in generated automatically by automake 1.4-p6 from Makefile.am
-# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.
+# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
@@ -468,7 +468,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
-TAR = gtar
+TAR = tar
GZIP_ENV = --best
SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
@@ -617,7 +617,7 @@ maintainer-clean-recursive:
dot_seen=no; \
rev=''; list='$(SUBDIRS)'; for subdir in $$list; do \
rev="$$subdir $$rev"; \
- test "$$subdir" = "." && dot_seen=yes; \
+ test "$$subdir" != "." || dot_seen=yes; \
done; \
test "$$dot_seen" = "no" && rev=". $$rev"; \
target=`echo $@ | sed s/-recursive//`; \
@@ -1054,7 +1054,7 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \
- $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h
+ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \
$(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index 7cac7f8..5371597 100644
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -214,7 +214,6 @@ const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operand
the RA field into the RB field, and the extraction function just
checks that the fields are the same. */
-/*ARGSUSED*/
static unsigned
insert_rba(insn, value, errmsg)
unsigned insn;
@@ -238,7 +237,6 @@ extract_rba(insn, invalid)
/* The same for the RC field */
-/*ARGSUSED*/
static unsigned
insert_rca(insn, value, errmsg)
unsigned insn;
@@ -262,7 +260,6 @@ extract_rca(insn, invalid)
/* Fake arguments in which the registers must be set to ZERO */
-/*ARGSUSED*/
static unsigned
insert_za(insn, value, errmsg)
unsigned insn;
@@ -282,7 +279,6 @@ extract_za(insn, invalid)
return 0;
}
-/*ARGSUSED*/
static unsigned
insert_zb(insn, value, errmsg)
unsigned insn;
@@ -302,7 +298,6 @@ extract_zb(insn, invalid)
return 0;
}
-/*ARGSUSED*/
static unsigned
insert_zc(insn, value, errmsg)
unsigned insn;
@@ -336,7 +331,6 @@ insert_bdisp(insn, value, errmsg)
return insn | ((value / 4) & 0x1FFFFF);
}
-/*ARGSUSED*/
static int
extract_bdisp(insn, invalid)
unsigned insn;
@@ -359,7 +353,6 @@ insert_jhint(insn, value, errmsg)
return insn | ((value / 4) & 0x3FFF);
}
-/*ARGSUSED*/
static int
extract_jhint(insn, invalid)
unsigned insn;
@@ -381,7 +374,6 @@ insert_ev6hwjhint(insn, value, errmsg)
return insn | ((value / 4) & 0x1FFF);
}
-/*ARGSUSED*/
static int
extract_ev6hwjhint(insn, invalid)
unsigned insn;
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 5f8fc4c..e918daf 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -639,6 +639,16 @@ print_insn_arm (pc, info, given)
func (stream, "%d", reg);
}
break;
+ case 'W':
+ {
+ long reg;
+
+ reg = given >> bitstart;
+ reg &= (2 << (bitend - bitstart)) - 1;
+
+ func (stream, "%d", reg + 1);
+ }
+ break;
case 'x':
{
long reg;
@@ -1145,6 +1155,23 @@ print_insn_thumb (pc, info, given)
abort ();
}
+/* Disallow mapping symbols ($a, $b, $d, $t etc) from
+ being displayed in symbol relative addresses. */
+
+bfd_boolean
+arm_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+ const char * name;
+
+ if (sym == NULL)
+ return FALSE;
+
+ name = bfd_asymbol_name (sym);
+
+ return (name && *name != '$');
+}
+
/* Parse an individual disassembler option. */
void
diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h
index 22313cb..cc59b8f 100644
--- a/opcodes/arm-opc.h
+++ b/opcodes/arm-opc.h
@@ -35,6 +35,7 @@ struct thumb_opcode
%<bitfield>d print the bitfield in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>X print the bitfield as 1 hex digit without leading "0x"
+ %<bitfield>w print the bitfield plus one in decimal
%<bitfield>r print as an ARM register
%<bitfield>f print a floating point constant if >7 else a
floating point register
@@ -97,6 +98,132 @@ static const struct arm_opcode arm_opcodes[] =
{0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
{0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ /* ARM V6 instructions. */
+ {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+ {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
+ {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"},
+ {0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
+ {0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"},
+ {0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
+ {0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
+ {0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
+ {0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
+ {0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
+ {0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
+ {0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
+ {0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
+ {0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
+ {0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
+ {0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
+ {0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
+ {0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
+ {0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
+ {0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
+ {0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
+ {0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
+ {0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
+ {0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
+ {0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
+ {0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
+ {0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
+ {0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
+ {0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
+ {0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
+ {0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
+ {0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
+ {0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
+ {0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
+ {0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
+ {0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
+ {0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
+ {0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
+ {0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
+ {0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
+ {0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
+ {0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
+ {0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
+ {0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
+ {0xf1010000, 0xfffffc00, "setend\t%9?ble"},
+ {0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
+ {0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
+ {0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
+ {0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"},
+ {0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
+ {0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
+ {0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
+ {0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
+ {0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
+ {0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
+ {0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
+ {0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
+ {0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
+ {0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
+ {0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
+ {0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
+
/* V5J instruction. */
{0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
@@ -459,6 +586,19 @@ static const struct thumb_opcode thumb_opcodes[] =
{
/* Thumb instructions. */
+ /* ARM V6. */
+ {0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"},
+ {0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"},
+ {0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"},
+ {0xba00, 0xffc0, "rev\t%0-2r, %3-5r"},
+ {0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"},
+ {0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"},
+ {0xb650, 0xfff7, "setend\t%3?ble\t"},
+ {0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"},
+ {0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"},
+ {0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"},
+ {0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"},
+
/* ARM V5 ISA extends Thumb. */
{0xbe00, 0xff00, "bkpt\t%0-7x"},
{0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c
index 8f846a9..83fbfbd 100644
--- a/opcodes/dis-buf.c
+++ b/opcodes/dis-buf.c
@@ -107,7 +107,7 @@ generic_strcat_address (addr, buf, len)
}
#endif
-/* Just return the given address. */
+/* Just return true. */
int
generic_symbol_at_address (addr, info)
@@ -116,3 +116,12 @@ generic_symbol_at_address (addr, info)
{
return 1;
}
+
+/* Just return TRUE. */
+
+bfd_boolean
+generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED,
+ struct disassemble_info *info ATTRIBUTE_UNUSED)
+{
+ return TRUE;
+}
diff --git a/opcodes/dis-init.c b/opcodes/dis-init.c
index 4c3e36e..35a5ee7 100644
--- a/opcodes/dis-init.c
+++ b/opcodes/dis-init.c
@@ -26,6 +26,7 @@ init_disassemble_info (struct disassemble_info *info, void *stream,
fprintf_ftype fprintf_func)
{
memset (info, 0, sizeof (*info));
+
info->flavour = bfd_target_unknown_flavour;
info->arch = bfd_arch_unknown;
info->endian = BFD_ENDIAN_UNKNOWN;
@@ -36,6 +37,7 @@ init_disassemble_info (struct disassemble_info *info, void *stream,
info->memory_error_func = perror_memory;
info->print_address_func = generic_print_address;
info->symbol_at_address_func = generic_symbol_at_address;
+ info->symbol_is_valid = generic_symbol_is_valid;
info->display_endian = BFD_ENDIAN_UNKNOWN;
}
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 14113b5..d5b17be 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -397,3 +397,21 @@ disassembler_usage (stream)
return;
}
+
+void
+disassemble_init_for_target (struct disassemble_info * info)
+{
+ if (info == NULL)
+ return;
+
+ switch (info->arch)
+ {
+#ifdef ARCH_arm
+ case bfd_arch_arm:
+ info->symbol_is_valid = arm_symbol_is_valid;
+ break;
+#endif
+ default:
+ break;
+ }
+}
diff --git a/opcodes/h8300-dis.c b/opcodes/h8300-dis.c
index ea8d30b..895a9ef 100644
--- a/opcodes/h8300-dis.c
+++ b/opcodes/h8300-dis.c
@@ -45,25 +45,6 @@ static void extract_immediate PARAMS ((FILE *,
int *, int *,
const struct h8_opcode *));
-static void print_colon_thingie PARAMS ((op_type *));
-
-static void
-print_colon_thingie (op_type *nib)
-{
- switch (*nib & SIZE) {
- case L_2: fprintf (stdout, "2"); break;
- case L_3:
- case L_3NZ: fprintf (stdout, "3"); break;
- case L_4: fprintf (stdout, "4"); break;
- case L_5: fprintf (stdout, "5"); break;
- case L_8: fprintf (stdout, "8"); break;
- case L_16:
- case L_16U: fprintf (stdout, "16"); break;
- case L_24: fprintf (stdout, "24"); break;
- case L_32: fprintf (stdout, "32"); break;
- }
-}
-
/* Run through the opcodes and sort them into order to make them easy
to disassemble. */
diff --git a/opcodes/i370-opc.c b/opcodes/i370-opc.c
index 4ce7994..a045f72 100644
--- a/opcodes/i370-opc.c
+++ b/opcodes/i370-opc.c
@@ -229,7 +229,6 @@ const struct i370_operand i370_operands[] =
/* The functions used to insert and extract complicated operands. */
-/*ARGSUSED*/
static i370_insn_t
insert_ss_b2 (i370_insn_t insn, long value,
const char **errmsg ATTRIBUTE_UNUSED)
diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c
index a8c9485..8c2cc81 100644
--- a/opcodes/m32r-asm.c
+++ b/opcodes/m32r-asm.c
@@ -147,7 +147,11 @@ parse_slo16 (cd, strp, opindex, valuep)
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
- value &= 0xffff;
+ {
+ value &= 0xffff;
+ if (value & 0x8000)
+ value |= 0xffff0000;
+ }
*valuep = value;
return errmsg;
}
@@ -310,12 +314,18 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
fields->f_uimm24 = value;
}
break;
+ case M32R_OPERAND_UIMM3 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM3, &fields->f_uimm3);
+ break;
case M32R_OPERAND_UIMM4 :
errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM4, &fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM5, &fields->f_uimm5);
break;
+ case M32R_OPERAND_UIMM8 :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, M32R_OPERAND_UIMM8, &fields->f_uimm8);
+ break;
case M32R_OPERAND_ULO16 :
errmsg = parse_ulo16 (cd, strp, M32R_OPERAND_ULO16, &fields->f_uimm16);
break;
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 023ab62..711aff0 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
{ "base", MACH_BASE },
{ "m32r", MACH_M32R },
{ "m32rx", MACH_M32RX },
+ { "m32r2", MACH_M32R2 },
{ "max", MACH_MAX },
{ 0, 0 }
};
@@ -65,6 +66,7 @@ static const CGEN_ATTR_ENTRY PIPE_attr[] =
{ "O", PIPE_O },
{ "S", PIPE_S },
{ "OS", PIPE_OS },
+ { "O_OS", PIPE_O_OS },
{ 0, 0 }
};
@@ -123,6 +125,8 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
{ "PBB", &bool_attr[0], &bool_attr[0] },
{ "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
{ "SPECIAL", &bool_attr[0], &bool_attr[0] },
+ { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
+ { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
@@ -138,6 +142,7 @@ static const CGEN_ISA m32r_cgen_isa_table[] = {
static const CGEN_MACH m32r_cgen_mach_table[] = {
{ "m32r", "m32r", MACH_M32R, 0 },
{ "m32rx", "m32rx", MACH_M32RX, 0 },
+ { "m32r2", "m32r2", MACH_M32R2, 0 },
{ 0, 0, 0, 0 }
};
@@ -180,6 +185,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
{ "bpc", 6, {0, {0}}, 0, 0 },
{ "bbpsw", 8, {0, {0}}, 0, 0 },
{ "bbpc", 14, {0, {0}}, 0, 0 },
+ { "evb", 5, {0, {0}}, 0, 0 },
{ "cr0", 0, {0, {0}}, 0, 0 },
{ "cr1", 1, {0, {0}}, 0, 0 },
{ "cr2", 2, {0, {0}}, 0, 0 },
@@ -201,7 +207,7 @@ static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
CGEN_KEYWORD m32r_cgen_opval_cr_names =
{
& m32r_cgen_opval_cr_names_entries[0],
- 23,
+ 24,
0, 0, 0, 0, ""
};
@@ -241,7 +247,7 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
{ "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
+ { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
{ "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
@@ -273,8 +279,10 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
{ M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
@@ -287,6 +295,7 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
{ M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
+ { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
{ M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
@@ -354,6 +363,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+/* uimm3: 3 bit unsigned number */
+ { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
@@ -362,6 +375,10 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+/* uimm8: 8 bit unsigned immediate */
+ { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
@@ -369,19 +386,19 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
+ { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
- { 0, { (1<<MACH_M32RX) } } },
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
@@ -564,12 +581,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* bcl.s $disp8 */
{
M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bcl.l $disp24 */
{
M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* bnc.s $disp8 */
{
@@ -599,12 +616,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* bncl.s $disp8 */
{
M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bncl.l $disp24 */
{
M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* cmp $src1,$src2 */
{
@@ -629,12 +646,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* cmpeq $src1,$src2 */
{
M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
- { 0, { (1<<MACH_M32RX), PIPE_OS } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* cmpz $src2 */
{
M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
- { 0, { (1<<MACH_M32RX), PIPE_OS } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* div $dr,$sr */
{
@@ -656,20 +673,55 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
M32R_INSN_REMU, "remu", "remu", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
+/* remh $dr,$sr */
+ {
+ M32R_INSN_REMH, "remh", "remh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remuh $dr,$sr */
+ {
+ M32R_INSN_REMUH, "remuh", "remuh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remb $dr,$sr */
+ {
+ M32R_INSN_REMB, "remb", "remb", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* remub $dr,$sr */
+ {
+ M32R_INSN_REMUB, "remub", "remub", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divuh $dr,$sr */
+ {
+ M32R_INSN_DIVUH, "divuh", "divuh", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divb $dr,$sr */
+ {
+ M32R_INSN_DIVB, "divb", "divb", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
+/* divub $dr,$sr */
+ {
+ M32R_INSN_DIVUB, "divub", "divub", 32,
+ { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ },
/* divh $dr,$sr */
{
M32R_INSN_DIVH, "divh", "divh", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* jc $sr */
{
M32R_INSN_JC, "jc", "jc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* jnc $sr */
{
M32R_INSN_JNC, "jnc", "jnc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* jl $sr */
{
@@ -764,7 +816,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* machi $src1,$src2,$acc */
{
M32R_INSN_MACHI_A, "machi-a", "machi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* maclo $src1,$src2 */
{
@@ -774,7 +826,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* maclo $src1,$src2,$acc */
{
M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwhi $src1,$src2 */
{
@@ -784,7 +836,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* macwhi $src1,$src2,$acc */
{
M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwlo $src1,$src2 */
{
@@ -794,7 +846,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* macwlo $src1,$src2,$acc */
{
M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mul $dr,$sr */
{
@@ -809,7 +861,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mulhi $src1,$src2,$acc */
{
M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mullo $src1,$src2 */
{
@@ -819,7 +871,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mullo $src1,$src2,$acc */
{
M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwhi $src1,$src2 */
{
@@ -829,7 +881,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mulwhi $src1,$src2,$acc */
{
M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwlo $src1,$src2 */
{
@@ -839,7 +891,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mulwlo $src1,$src2,$acc */
{
M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mv $dr,$sr */
{
@@ -854,7 +906,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mvfachi $dr,$accs */
{
M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfaclo $dr */
{
@@ -864,7 +916,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mvfaclo $dr,$accs */
{
M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfacmi $dr */
{
@@ -874,7 +926,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mvfacmi $dr,$accs */
{
M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvfc $dr,$scr */
{
@@ -889,7 +941,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mvtachi $src1,$accs */
{
M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvtaclo $src1 */
{
@@ -899,7 +951,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* mvtaclo $src1,$accs */
{
M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mvtc $sr,$dcr */
{
@@ -929,7 +981,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* rac $accd,$accs,$imm1 */
{
M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach */
{
@@ -939,7 +991,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* rach $accd,$accs,$imm1 */
{
M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rte */
{
@@ -954,7 +1006,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* sll $dr,$sr */
{
M32R_INSN_SLL, "sll", "sll", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sll3 $dr,$sr,$simm16 */
{
@@ -964,12 +1016,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* slli $dr,$uimm5 */
{
M32R_INSN_SLLI, "slli", "slli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sra $dr,$sr */
{
M32R_INSN_SRA, "sra", "sra", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* sra3 $dr,$sr,$simm16 */
{
@@ -979,12 +1031,12 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* srai $dr,$uimm5 */
{
M32R_INSN_SRAI, "srai", "srai", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* srl $dr,$sr */
{
M32R_INSN_SRL, "srl", "srl", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* srl3 $dr,$sr,$simm16 */
{
@@ -994,7 +1046,7 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* srli $dr,$uimm5 */
{
M32R_INSN_SRLI, "srli", "srli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { (1<<MACH_BASE), PIPE_O_OS } }
},
/* st $src1,@$src2 */
{
@@ -1031,6 +1083,16 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
M32R_INSN_ST_PLUS, "st-plus", "st", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
+/* sth $src1,@$src2+ */
+ {
+ M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
+/* stb $src1,@$src2+ */
+ {
+ M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
/* st $src1,@-$src2 */
{
M32R_INSN_ST_MINUS, "st-minus", "st", 16,
@@ -1064,57 +1126,82 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* satb $dr,$sr */
{
M32R_INSN_SATB, "satb", "satb", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* sath $dr,$sr */
{
M32R_INSN_SATH, "sath", "sath", 32,
- { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* sat $dr,$sr */
{
M32R_INSN_SAT, "sat", "sat", 32,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* pcmpbz $src2 */
{
M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+ { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
},
/* sadd */
{
M32R_INSN_SADD, "sadd", "sadd", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* macwu1 $src1,$src2 */
{
M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* msblo $src1,$src2 */
{
M32R_INSN_MSBLO, "msblo", "msblo", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* mulwu1 $src1,$src2 */
{
M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* maclh1 $src1,$src2 */
{
M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
- { 0, { (1<<MACH_M32RX), PIPE_S } }
+ { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* sc */
{
M32R_INSN_SC, "sc", "sc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* snc */
{
M32R_INSN_SNC, "snc", "snc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ },
+/* clrpsw $uimm8 */
+ {
+ M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* setpsw $uimm8 */
+ {
+ M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ },
+/* bset $uimm3,@($slo16,$sr) */
+ {
+ M32R_INSN_BSET, "bset", "bset", 32,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* bclr $uimm3,@($slo16,$sr) */
+ {
+ M32R_INSN_BCLR, "bclr", "bclr", 32,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ },
+/* btst $uimm3,$sr */
+ {
+ M32R_INSN_BTST, "btst", "btst", 16,
+ { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
},
};
diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h
index 8781772..ef61b69 100644
--- a/opcodes/m32r-desc.h
+++ b/opcodes/m32r-desc.h
@@ -38,6 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Selected cpu families. */
#define HAVE_CPU_M32RBF
#define HAVE_CPU_M32RXF
+#define HAVE_CPU_M32R2F
#define CGEN_INSN_LSB0_P 0
@@ -90,18 +91,19 @@ typedef enum gr_names {
/* Enum declaration for . */
typedef enum cr_names {
H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
- , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
- , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
- , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
- , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
+ , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5
+ , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3
+ , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7
+ , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11
+ , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
} CR_NAMES;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
- MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
+ MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
@@ -112,6 +114,7 @@ typedef enum isa_attr {
/* Enum declaration for parallel execution pipeline selection. */
typedef enum pipe_attr {
PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
+ , PIPE_O_OS
} PIPE_ATTR;
/* Number of architecture variants. */
@@ -138,11 +141,12 @@ typedef enum cgen_ifld_attr {
typedef enum ifield_type {
M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2
, M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8
- , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5
- , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8
- , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3
- , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67
- , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX
+ , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4
+ , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24
+ , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24
+ , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS
+ , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14
+ , M32R_F_IMM1, M32R_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) M32R_F_MAX)
@@ -186,15 +190,16 @@ typedef enum cgen_operand_attr {
typedef enum cgen_operand_type {
M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
, M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
- , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
+ , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5
+ , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD
+ , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16
+ , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8
+ , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM
+ , M32R_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 26
+#define MAX_OPERANDS 28
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 11
@@ -206,8 +211,8 @@ typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
- , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
- , CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
@@ -228,6 +233,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_gr_names;
extern CGEN_KEYWORD m32r_cgen_opval_cr_names;
extern CGEN_KEYWORD m32r_cgen_opval_h_accums;
+extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index e8abbc6..6e5ea70 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -100,6 +100,8 @@ my_print_insn (cd, pc, info)
char *buf = buffer;
int status;
int buflen = (pc & 3) == 0 ? 4 : 2;
+ int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
+ char *x;
/* Read the base part of the insn. */
@@ -111,22 +113,25 @@ my_print_insn (cd, pc, info)
}
/* 32 bit insn? */
- if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
+ x = (big_p ? &buf[0] : &buf[3]);
+ if ((pc & 3) == 0 && (*x & 0x80) != 0)
return print_insn (cd, pc, info, buf, buflen);
/* Print the first insn. */
+ buf += (big_p ? 0 : 2);
if ((pc & 3) == 0)
{
if (print_insn (cd, pc, info, buf, 2) == 0)
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
- buf += 2;
}
+ buf += (big_p ? 2 : -2);
- if (buf[0] & 0x80)
+ x = (big_p ? &buf[0] : &buf[1]);
+ if (*x & 0x80)
{
/* Parallel. */
(*info->fprintf_func) (info->stream, " || ");
- buf[0] &= 0x7f;
+ *x &= 0x7f;
}
else
(*info->fprintf_func) (info->stream, " -> ");
@@ -235,12 +240,18 @@ m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
case M32R_OPERAND_UIMM24 :
print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
break;
+ case M32R_OPERAND_UIMM3 :
+ print_normal (cd, info, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+ break;
case M32R_OPERAND_UIMM4 :
print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case M32R_OPERAND_UIMM5 :
print_normal (cd, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
+ case M32R_OPERAND_UIMM8 :
+ print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+ break;
case M32R_OPERAND_ULO16 :
print_normal (cd, info, fields->f_uimm16, 0, pc, length);
break;
diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c
index 2a8d104..32224da 100644
--- a/opcodes/m32r-ibld.c
+++ b/opcodes/m32r-ibld.c
@@ -646,12 +646,18 @@ m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
case M32R_OPERAND_UIMM24 :
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
break;
+ case M32R_OPERAND_UIMM3 :
+ errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
+ break;
case M32R_OPERAND_UIMM4 :
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
break;
case M32R_OPERAND_UIMM5 :
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
break;
+ case M32R_OPERAND_UIMM8 :
+ errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
+ break;
case M32R_OPERAND_ULO16 :
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
break;
@@ -779,12 +785,18 @@ m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
case M32R_OPERAND_UIMM24 :
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
break;
+ case M32R_OPERAND_UIMM3 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
+ break;
case M32R_OPERAND_UIMM4 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
break;
case M32R_OPERAND_UIMM5 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
break;
+ case M32R_OPERAND_UIMM8 :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
+ break;
case M32R_OPERAND_ULO16 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
break;
@@ -889,12 +901,18 @@ m32r_cgen_get_int_operand (cd, opindex, fields)
case M32R_OPERAND_UIMM24 :
value = fields->f_uimm24;
break;
+ case M32R_OPERAND_UIMM3 :
+ value = fields->f_uimm3;
+ break;
case M32R_OPERAND_UIMM4 :
value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
value = fields->f_uimm5;
break;
+ case M32R_OPERAND_UIMM8 :
+ value = fields->f_uimm8;
+ break;
case M32R_OPERAND_ULO16 :
value = fields->f_uimm16;
break;
@@ -979,12 +997,18 @@ m32r_cgen_get_vma_operand (cd, opindex, fields)
case M32R_OPERAND_UIMM24 :
value = fields->f_uimm24;
break;
+ case M32R_OPERAND_UIMM3 :
+ value = fields->f_uimm3;
+ break;
case M32R_OPERAND_UIMM4 :
value = fields->f_uimm4;
break;
case M32R_OPERAND_UIMM5 :
value = fields->f_uimm5;
break;
+ case M32R_OPERAND_UIMM8 :
+ value = fields->f_uimm8;
+ break;
case M32R_OPERAND_ULO16 :
value = fields->f_uimm16;
break;
@@ -1077,12 +1101,18 @@ m32r_cgen_set_int_operand (cd, opindex, fields, value)
case M32R_OPERAND_UIMM24 :
fields->f_uimm24 = value;
break;
+ case M32R_OPERAND_UIMM3 :
+ fields->f_uimm3 = value;
+ break;
case M32R_OPERAND_UIMM4 :
fields->f_uimm4 = value;
break;
case M32R_OPERAND_UIMM5 :
fields->f_uimm5 = value;
break;
+ case M32R_OPERAND_UIMM8 :
+ fields->f_uimm8 = value;
+ break;
case M32R_OPERAND_ULO16 :
fields->f_uimm16 = value;
break;
@@ -1163,12 +1193,18 @@ m32r_cgen_set_vma_operand (cd, opindex, fields, value)
case M32R_OPERAND_UIMM24 :
fields->f_uimm24 = value;
break;
+ case M32R_OPERAND_UIMM3 :
+ fields->f_uimm3 = value;
+ break;
case M32R_OPERAND_UIMM4 :
fields->f_uimm4 = value;
break;
case M32R_OPERAND_UIMM5 :
fields->f_uimm5 = value;
break;
+ case M32R_OPERAND_UIMM8 :
+ fields->f_uimm8 = value;
+ break;
case M32R_OPERAND_ULO16 :
fields->f_uimm16 = value;
break;
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c
index 8143b61..a18d5cc 100644
--- a/opcodes/m32r-opc.c
+++ b/opcodes/m32r-opc.c
@@ -30,6 +30,31 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "m32r-opc.h"
#include "libiberty.h"
+/* -- opc.c */
+unsigned int
+m32r_cgen_dis_hash (buf, value)
+ const char * buf ATTRIBUTE_UNUSED;
+ CGEN_INSN_INT value;
+{
+ unsigned int x;
+
+ if (value & 0xffff0000) /* 32bit instructions */
+ value = (value >> 16) & 0xffff;
+
+ x = (value>>8) & 0xf0;
+ if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
+ return x;
+
+ if (x == 0x70 || x == 0xf0)
+ return x | ((value>>8) & 0x0f);
+
+ if (x == 0x30)
+ return x | ((value & 0x70) >> 4);
+ else
+ return x | ((value & 0xf0) >> 4);
+}
+
+/* -- */
/* The hash functions are recorded here to help keep assembler code out of
the disassembler and vice versa. */
@@ -173,6 +198,18 @@ static const CGEN_IFMT ifmt_satb = {
32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
};
+static const CGEN_IFMT ifmt_clrpsw = {
+ 16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bset = {
+ 32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_btst = {
+ 16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
+};
+
#undef F
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@@ -448,6 +485,48 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
& ifmt_div, { 0x90300000 }
},
+/* remh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90200010 }
+ },
+/* remuh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90300010 }
+ },
+/* remb $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90200018 }
+ },
+/* remub $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90300018 }
+ },
+/* divuh $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90100010 }
+ },
+/* divb $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90000018 }
+ },
+/* divub $dr,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+ & ifmt_div, { 0x90100018 }
+ },
/* divh $dr,$sr */
{
{ 0, 0, 0, 0 },
@@ -898,6 +977,18 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
& ifmt_cmp, { 0x2060 }
},
+/* sth $src1,@$src2+ */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+ & ifmt_cmp, { 0x2030 }
+ },
+/* stb $src1,@$src2+ */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
+ & ifmt_cmp, { 0x2010 }
+ },
/* st $src1,@-$src2 */
{
{ 0, 0, 0, 0 },
@@ -1000,6 +1091,36 @@ static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, 0 } },
& ifmt_nop, { 0x7501 }
},
+/* clrpsw $uimm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM8), 0 } },
+ & ifmt_clrpsw, { 0x7200 }
+ },
+/* setpsw $uimm8 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM8), 0 } },
+ & ifmt_clrpsw, { 0x7100 }
+ },
+/* bset $uimm3,@($slo16,$sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ & ifmt_bset, { 0xa0600000 }
+ },
+/* bclr $uimm3,@($slo16,$sr) */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
+ & ifmt_bset, { 0xa0700000 }
+ },
+/* btst $uimm3,$sr */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
+ & ifmt_btst, { 0xf0 }
+ },
};
#undef A
@@ -1202,12 +1323,12 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
/* bcl $disp8 */
{
-1, "bcl8r", "bcl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bcl $disp24 */
{
-1, "bcl24r", "bcl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* bnc $disp8 */
{
@@ -1232,12 +1353,12 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
/* bncl $disp8 */
{
-1, "bncl8r", "bncl", 16,
- { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } }
+ { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
},
/* bncl $disp24 */
{
-1, "bncl24r", "bncl", 32,
- { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } }
+ { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
},
/* ld $dr,@($sr) */
{
@@ -1292,7 +1413,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
/* pop $dr */
{
-1, "pop", "pop", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
/* ldi $dr,$simm8 */
{
@@ -1307,22 +1428,22 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
/* rac $accd */
{
-1, "rac-d", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rac $accd,$accs */
{
-1, "rac-ds", "rac", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach $accd */
{
-1, "rach-d", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* rach $accd,$accs */
{
-1, "rach-ds", "rach", 16,
- { 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } }
+ { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
},
/* st $src1,@($src2) */
{
@@ -1357,7 +1478,7 @@ static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
/* push $src1 */
{
-1, "push", "push", 16,
- { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
},
};
diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h
index 22e6924..5fe7106 100644
--- a/opcodes/m32r-opc.h
+++ b/opcodes/m32r-opc.h
@@ -30,6 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
+#if 0
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
@@ -37,6 +38,10 @@ with this program; if not, write to the Free Software Foundation, Inc.,
: X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \
: X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \
: ((((unsigned char *) (buffer))[1] & 0xf0) >> 4)))
+#else
+#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash(buffer, value)
+extern unsigned int m32r_cgen_dis_hash(const char *, CGEN_INSN_INT);
+#endif
/* -- */
/* Enum declaration for m32r instruction types. */
@@ -51,37 +56,41 @@ typedef enum cgen_insn_type {
, M32R_INSN_BNE, M32R_INSN_BRA8, M32R_INSN_BRA24, M32R_INSN_BNCL8
, M32R_INSN_BNCL24, M32R_INSN_CMP, M32R_INSN_CMPI, M32R_INSN_CMPU
, M32R_INSN_CMPUI, M32R_INSN_CMPEQ, M32R_INSN_CMPZ, M32R_INSN_DIV
- , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_DIVH
- , M32R_INSN_JC, M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP
- , M32R_INSN_LD, M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D
- , M32R_INSN_LDH, M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D
- , M32R_INSN_LDUH, M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24
- , M32R_INSN_LDI8, M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI
- , M32R_INSN_MACHI_A, M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI
- , M32R_INSN_MACWHI_A, M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL
- , M32R_INSN_MULHI, M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A
- , M32R_INSN_MULWHI, M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A
- , M32R_INSN_MV, M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO
- , M32R_INSN_MVFACLO_A, M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC
- , M32R_INSN_MVTACHI, M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A
- , M32R_INSN_MVTC, M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT
- , M32R_INSN_RAC, M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI
- , M32R_INSN_RTE, M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3
- , M32R_INSN_SLLI, M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI
- , M32R_INSN_SRL, M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST
- , M32R_INSN_ST_D, M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH
- , M32R_INSN_STH_D, M32R_INSN_ST_PLUS, M32R_INSN_ST_MINUS, M32R_INSN_SUB
- , M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP, M32R_INSN_UNLOCK
- , M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT, M32R_INSN_PCMPBZ
- , M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO, M32R_INSN_MULWU1
- , M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_DIVU, M32R_INSN_REM, M32R_INSN_REMU, M32R_INSN_REMH
+ , M32R_INSN_REMUH, M32R_INSN_REMB, M32R_INSN_REMUB, M32R_INSN_DIVUH
+ , M32R_INSN_DIVB, M32R_INSN_DIVUB, M32R_INSN_DIVH, M32R_INSN_JC
+ , M32R_INSN_JNC, M32R_INSN_JL, M32R_INSN_JMP, M32R_INSN_LD
+ , M32R_INSN_LD_D, M32R_INSN_LDB, M32R_INSN_LDB_D, M32R_INSN_LDH
+ , M32R_INSN_LDH_D, M32R_INSN_LDUB, M32R_INSN_LDUB_D, M32R_INSN_LDUH
+ , M32R_INSN_LDUH_D, M32R_INSN_LD_PLUS, M32R_INSN_LD24, M32R_INSN_LDI8
+ , M32R_INSN_LDI16, M32R_INSN_LOCK, M32R_INSN_MACHI, M32R_INSN_MACHI_A
+ , M32R_INSN_MACLO, M32R_INSN_MACLO_A, M32R_INSN_MACWHI, M32R_INSN_MACWHI_A
+ , M32R_INSN_MACWLO, M32R_INSN_MACWLO_A, M32R_INSN_MUL, M32R_INSN_MULHI
+ , M32R_INSN_MULHI_A, M32R_INSN_MULLO, M32R_INSN_MULLO_A, M32R_INSN_MULWHI
+ , M32R_INSN_MULWHI_A, M32R_INSN_MULWLO, M32R_INSN_MULWLO_A, M32R_INSN_MV
+ , M32R_INSN_MVFACHI, M32R_INSN_MVFACHI_A, M32R_INSN_MVFACLO, M32R_INSN_MVFACLO_A
+ , M32R_INSN_MVFACMI, M32R_INSN_MVFACMI_A, M32R_INSN_MVFC, M32R_INSN_MVTACHI
+ , M32R_INSN_MVTACHI_A, M32R_INSN_MVTACLO, M32R_INSN_MVTACLO_A, M32R_INSN_MVTC
+ , M32R_INSN_NEG, M32R_INSN_NOP, M32R_INSN_NOT, M32R_INSN_RAC
+ , M32R_INSN_RAC_DSI, M32R_INSN_RACH, M32R_INSN_RACH_DSI, M32R_INSN_RTE
+ , M32R_INSN_SETH, M32R_INSN_SLL, M32R_INSN_SLL3, M32R_INSN_SLLI
+ , M32R_INSN_SRA, M32R_INSN_SRA3, M32R_INSN_SRAI, M32R_INSN_SRL
+ , M32R_INSN_SRL3, M32R_INSN_SRLI, M32R_INSN_ST, M32R_INSN_ST_D
+ , M32R_INSN_STB, M32R_INSN_STB_D, M32R_INSN_STH, M32R_INSN_STH_D
+ , M32R_INSN_ST_PLUS, M32R_INSN_STH_PLUS, M32R_INSN_STB_PLUS, M32R_INSN_ST_MINUS
+ , M32R_INSN_SUB, M32R_INSN_SUBV, M32R_INSN_SUBX, M32R_INSN_TRAP
+ , M32R_INSN_UNLOCK, M32R_INSN_SATB, M32R_INSN_SATH, M32R_INSN_SAT
+ , M32R_INSN_PCMPBZ, M32R_INSN_SADD, M32R_INSN_MACWU1, M32R_INSN_MSBLO
+ , M32R_INSN_MULWU1, M32R_INSN_MACLH1, M32R_INSN_SC, M32R_INSN_SNC
+ , M32R_INSN_CLRPSW, M32R_INSN_SETPSW, M32R_INSN_BSET, M32R_INSN_BCLR
+ , M32R_INSN_BTST
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID M32R_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) M32R_INSN_SNC + 1)
+#define MAX_INSNS ((int) M32R_INSN_BTST + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
@@ -97,8 +106,10 @@ struct cgen_fields
long f_simm8;
long f_simm16;
long f_shift_op2;
+ long f_uimm3;
long f_uimm4;
long f_uimm5;
+ long f_uimm8;
long f_uimm16;
long f_uimm24;
long f_hi16;
@@ -111,6 +122,7 @@ struct cgen_fields
long f_accs;
long f_accd;
long f_bits67;
+ long f_bit4;
long f_bit14;
long f_imm1;
};
diff --git a/opcodes/m32r-opinst.c b/opcodes/m32r-opinst.c
index 5365d15..370aa7c 100644
--- a/opcodes/m32r-opinst.c
+++ b/opcodes/m32r-opinst.c
@@ -42,42 +42,42 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#define COND_REF CGEN_OPINST_COND_REF
static const CGEN_OPINST sfmt_empty_ops[] = {
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_add_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_add3_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_and3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_or3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addi_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addv_ops[] = {
@@ -85,7 +85,7 @@ static const CGEN_OPINST sfmt_addv_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addv3_ops[] = {
@@ -93,7 +93,7 @@ static const CGEN_OPINST sfmt_addv3_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_addx_ops[] = {
@@ -102,21 +102,21 @@ static const CGEN_OPINST sfmt_addx_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bc8_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bc24_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_beq_ops[] = {
@@ -124,14 +124,14 @@ static const CGEN_OPINST sfmt_beq_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_beqz_ops[] = {
{ INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bl8_ops[] = {
@@ -139,7 +139,7 @@ static const CGEN_OPINST sfmt_bl8_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bl24_ops[] = {
@@ -147,7 +147,7 @@ static const CGEN_OPINST sfmt_bl24_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bcl8_ops[] = {
@@ -156,7 +156,7 @@ static const CGEN_OPINST sfmt_bcl8_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bcl24_ops[] = {
@@ -165,53 +165,53 @@ static const CGEN_OPINST sfmt_bcl24_ops[] = {
{ INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bra8_ops[] = {
{ INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_bra24_ops[] = {
{ INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmp_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmpi_ops[] = {
{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_cmpz_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_div_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jc_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jl_ops[] = {
@@ -219,20 +219,20 @@ static const CGEN_OPINST sfmt_jl_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_jmp_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_ops[] = {
{ INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_d_ops[] = {
@@ -240,14 +240,14 @@ static const CGEN_OPINST sfmt_ld_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldb_ops[] = {
{ INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldb_d_ops[] = {
@@ -255,14 +255,14 @@ static const CGEN_OPINST sfmt_ldb_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldh_ops[] = {
{ INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldh_d_ops[] = {
@@ -270,7 +270,7 @@ static const CGEN_OPINST sfmt_ldh_d_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld_plus_ops[] = {
@@ -278,25 +278,25 @@ static const CGEN_OPINST sfmt_ld_plus_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ld24_ops[] = {
{ INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldi8_ops[] = {
{ INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_ldi16_ops[] = {
{ INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_lock_ops[] = {
@@ -304,7 +304,7 @@ static const CGEN_OPINST sfmt_lock_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_machi_ops[] = {
@@ -312,7 +312,7 @@ static const CGEN_OPINST sfmt_machi_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_machi_a_ops[] = {
@@ -320,82 +320,82 @@ static const CGEN_OPINST sfmt_machi_a_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulhi_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mv_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfachi_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvfc_ops[] = {
{ INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtachi_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mvtc_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_nop_ops[] = {
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rac_ops[] = {
{ INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
{ OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
{ INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
{ INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
{ OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_rte_ops[] = {
@@ -407,34 +407,34 @@ static const CGEN_OPINST sfmt_rte_ops[] = {
{ OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
{ OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_seth_ops[] = {
{ INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sll3_ops[] = {
{ INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_slli_ops[] = {
{ INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
{ INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_d_ops[] = {
@@ -442,14 +442,14 @@ static const CGEN_OPINST sfmt_st_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_stb_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_stb_d_ops[] = {
@@ -457,14 +457,14 @@ static const CGEN_OPINST sfmt_stb_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sth_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sth_d_ops[] = {
@@ -472,7 +472,7 @@ static const CGEN_OPINST sfmt_sth_d_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_st_plus_ops[] = {
@@ -480,7 +480,23 @@ static const CGEN_OPINST sfmt_st_plus_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
{ OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sth_plus_ops[] = {
+ { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+ { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_plus_ops[] = {
+ { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
+ { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_trap_ops[] = {
@@ -495,7 +511,7 @@ static const CGEN_OPINST sfmt_trap_ops[] = {
{ OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
{ OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
{ OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_unlock_ops[] = {
@@ -504,27 +520,27 @@ static const CGEN_OPINST sfmt_unlock_ops[] = {
{ INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
{ OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
{ OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_satb_ops[] = {
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sat_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
{ INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
{ OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sadd_ops[] = {
{ INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
{ INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
{ OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_macwu1_ops[] = {
@@ -532,19 +548,48 @@ static const CGEN_OPINST sfmt_macwu1_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_mulwu1_ops[] = {
{ INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
{ INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
{ OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
static const CGEN_OPINST sfmt_sc_ops[] = {
{ INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
- { END }
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_clrpsw_ops[] = {
+ { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
+ { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_setpsw_ops[] = {
+ { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
+ { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bset_ops[] = {
+ { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
+ { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
+ { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+ { OUTPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_btst_ops[] = {
+ { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
+ { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
+ { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
+ { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
};
#undef OP_ENT
@@ -600,6 +645,13 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
& sfmt_div_ops[0],
& sfmt_div_ops[0],
& sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
+ & sfmt_div_ops[0],
& sfmt_jc_ops[0],
& sfmt_jc_ops[0],
& sfmt_jl_ops[0],
@@ -674,6 +726,8 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
& sfmt_sth_ops[0],
& sfmt_sth_d_ops[0],
& sfmt_st_plus_ops[0],
+ & sfmt_sth_plus_ops[0],
+ & sfmt_stb_plus_ops[0],
& sfmt_st_plus_ops[0],
& sfmt_add_ops[0],
& sfmt_addv_ops[0],
@@ -691,6 +745,11 @@ static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
& sfmt_macwu1_ops[0],
& sfmt_sc_ops[0],
& sfmt_sc_ops[0],
+ & sfmt_clrpsw_ops[0],
+ & sfmt_setpsw_ops[0],
+ & sfmt_bset_ops[0],
+ & sfmt_bset_ops[0],
+ & sfmt_btst_ops[0],
};
/* Function to call before using the operand instance table. */
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 340a084..9a80e53 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -517,6 +517,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
+{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, I3 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
@@ -640,6 +641,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
+{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, I1 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
diff --git a/opcodes/mmix-opc.c b/opcodes/mmix-opc.c
index 76dc5d8..8d553e2 100644
--- a/opcodes/mmix-opc.c
+++ b/opcodes/mmix-opc.c
@@ -1,5 +1,5 @@
/* mmix-opc.c -- MMIX opcode table
- Copyright (C) 2001 Free Software Foundation, Inc.
+ Copyright (C) 2001, 2003 Free Software Foundation, Inc.
Written by Hans-Peter Nilsson (hp@bitrange.com)
This file is part of GDB, GAS, and the GNU binutils.
@@ -227,7 +227,8 @@ const struct mmix_opcode mmix_opcodes[] =
{"prego", Z (0x9c), OP (x_regs_z), N},
{"ldunc", Z (0x96), OP (regs_z_opt), MO},
- {"go", Z (0x9e), OP (regs_z_opt), B},
+ {"go", Z (GO_INSN_BYTE),
+ OP (regs_z_opt), B},
{"stb", Z (0xa0), OP (regs_z_opt), MB},
{"stt", Z (0xa8), OP (regs_z_opt), MT},
@@ -251,7 +252,8 @@ const struct mmix_opcode mmix_opcodes[] =
{"syncid", Z (0xbc), OP (x_regs_z), M},
{"stunc", Z (0xb6), OP (regs_z_opt), MO},
- {"pushgo", Z (0xbe), OP (pushgo), J},
+ {"pushgo", Z (PUSHGO_INSN_BYTE),
+ OP (pushgo), J},
/* Synonym for OR with a zero Z. */
{"set", O (0xc1)
@@ -287,16 +289,20 @@ const struct mmix_opcode mmix_opcodes[] =
{"ormh", O (0xe9), OP (reg_yz), N},
{"setml", O (0xe2), OP (reg_yz), N},
- {"setl", O (0xe3), OP (reg_yz), N},
+ {"setl", O (SETL_INSN_BYTE),
+ OP (reg_yz), N},
{"orml", O (0xea), OP (reg_yz), N},
{"orl", O (0xeb), OP (reg_yz), N},
- {"inch", O (0xe4), OP (reg_yz), N},
- {"incmh", O (0xe5), OP (reg_yz), N},
+ {"inch", O (INCH_INSN_BYTE),
+ OP (reg_yz), N},
+ {"incmh", O (INCMH_INSN_BYTE),
+ OP (reg_yz), N},
{"andnh", O (0xec), OP (reg_yz), N},
{"andnmh", O (0xed), OP (reg_yz), N},
- {"incml", O (0xe6), OP (reg_yz), N},
+ {"incml", O (INCML_INSN_BYTE),
+ OP (reg_yz), N},
{"incl", O (0xe7), OP (reg_yz), N},
{"andnml", O (0xee), OP (reg_yz), N},
{"andnl", O (0xef), OP (reg_yz), N},
@@ -314,7 +320,8 @@ const struct mmix_opcode mmix_opcodes[] =
{"geta", Z (0xf4), OP (regaddr), N},
{"sync", O (0xfc), OP (sync), N},
- {"swym", O (0xfd), OP (xyz_opt), N},
+ {"swym", O (SWYM_INSN_BYTE),
+ OP (xyz_opt), N},
{"put", Z (0xf6) | 0xff00, OP (put), N},
{"get", O (0xfe) | 0xffe0, OP (get), N},
diff --git a/opcodes/openrisc-asm.c b/opcodes/openrisc-asm.c
index 9f6ee32..ad97790 100644
--- a/opcodes/openrisc-asm.c
+++ b/opcodes/openrisc-asm.c
@@ -60,7 +60,7 @@ long
openrisc_sign_extend_16bit (value)
long value;
{
- return (long) (short) value;
+ return ((value & 0xffff) ^ 0x8000) - 0x8000;
}
/* Handle hi(). */
@@ -74,15 +74,16 @@ parse_hi16 (cd, strp, opindex, valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
- bfd_vma value;
+ unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "hi(", 3) == 0)
{
- *strp += 3;
+ bfd_vma value;
+ *strp += 3;
#if 0
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
if (errmsg != NULL)
@@ -92,23 +93,31 @@ parse_hi16 (cd, strp, opindex, valuep)
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16,
&result_type, &value);
if (**strp != ')')
- return "missing `)'";
+ return _("missing `)'");
+
++*strp;
if (errmsg == NULL
&& result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
value >>= 16;
- *valuep = (long) (short) value;
-
- return errmsg;
+ ret = value;
}
else
{
if (**strp == '-')
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value);
+ {
+ long value;
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
+ ret = value;
+ }
else
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value);
+ {
+ unsigned long value;
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
+ ret = value;
+ }
}
- *valuep = (long) (short) (value & 0xffff);
+
+ *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
@@ -123,15 +132,16 @@ parse_lo16 (cd, strp, opindex, valuep)
{
const char *errmsg;
enum cgen_parse_operand_result result_type;
- bfd_vma value;
+ unsigned long ret;
if (**strp == '#')
++*strp;
if (strncasecmp (*strp, "lo(", 3) == 0)
{
- *strp += 3;
+ bfd_vma value;
+ *strp += 3;
#if 0
errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep);
if (errmsg != NULL)
@@ -142,21 +152,28 @@ parse_lo16 (cd, strp, opindex, valuep)
errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16,
&result_type, &value);
if (**strp != ')')
- return "missing `)'";
- ++*strp;
- if (errmsg == NULL
- && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
- value &= 0xffff;
- *valuep = (long) (short) value;
+ return _("missing `)'");
- return errmsg;
+ ++*strp;
+ ret = value;
}
-
- if (**strp == '-')
- errmsg = cgen_parse_signed_integer (cd, strp, opindex, (long *) &value);
else
- errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) &value);
- *valuep = (long) (short) (value & 0xffff);
+ {
+ if (**strp == '-')
+ {
+ long value;
+ errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value);
+ ret = value;
+ }
+ else
+ {
+ unsigned long value;
+ errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value);
+ ret = value;
+ }
+ }
+
+ *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000;
return errmsg;
}
diff --git a/opcodes/pj-opc.c b/opcodes/pj-opc.c
index 68ca05e..218496d 100644
--- a/opcodes/pj-opc.c
+++ b/opcodes/pj-opc.c
@@ -1,5 +1,5 @@
/* pj-opc.c -- Definitions for picoJava opcodes.
- Copyright 1999, 2000 Free Software Foundation, Inc.
+ Copyright 1999, 2000, 2002 Free Software Foundation, Inc.
Contributed by Steve Chamberlain of Transmeta (sac@pobox.com).
This program is free software; you can redistribute it and/or modify
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c37943b..d011edf 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -344,7 +344,7 @@ const struct powerpc_operand powerpc_operands[] =
/* The MO field in an mbar instruction. */
#define MO MB6 + 1
- { 5, 21, 0, 0, 0 },
+ { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
/* The NB field in an X form instruction. The value 32 is stored as
0. */
@@ -384,8 +384,12 @@ const struct powerpc_operand powerpc_operands[] =
#define RAS RAM + 1
{ 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
+ /* The RA field of the tlbwe instruction, which is optional. */
+#define RAO RAS + 1
+ { 5, 16, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
/* The RB field in an X, XO, M, or MDS form instruction. */
-#define RB RAS + 1
+#define RB RAO + 1
#define RB_MASK (0x1f << 11)
{ 5, 11, 0, 0, PPC_OPERAND_GPR },
@@ -413,8 +417,12 @@ const struct powerpc_operand powerpc_operands[] =
#define RTQ RSQ + 1
{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+ /* The RS field of the tlbwe instruction, which is optional. */
+#define RSO RTQ + 1
+ { 5, 21, 0, 0, PPC_OPERAND_GPR|PPC_OPERAND_OPTIONAL },
+
/* The SH field in an X or M form instruction. */
-#define SH RTQ + 1
+#define SH RSO + 1
#define SH_MASK (0x1f << 11)
{ 5, 11, 0, 0, 0 },
@@ -423,8 +431,12 @@ const struct powerpc_operand powerpc_operands[] =
#define SH6_MASK ((0x1f << 11) | (1 << 1))
{ 6, 1, insert_sh6, extract_sh6, 0 },
+ /* The SH field of the tlbwe instruction, which is optional. */
+#define SHO SH6 + 1
+ { 5, 11,0, 0, PPC_OPERAND_OPTIONAL },
+
/* The SI field in a D form instruction. */
-#define SI SH6 + 1
+#define SI SHO + 1
{ 16, 0, 0, 0, PPC_OPERAND_SIGNED },
/* The SI field in a D form instruction when we accept a wide range
@@ -548,7 +560,6 @@ const struct powerpc_operand powerpc_operands[] =
and the extraction function just checks that the fields are the
same. */
-/*ARGSUSED*/
static unsigned long
insert_bat (unsigned long insn,
long value ATTRIBUTE_UNUSED,
@@ -574,7 +585,6 @@ extract_bat (unsigned long insn,
and the extraction function just checks that the fields are the
same. */
-/*ARGSUSED*/
static unsigned long
insert_bba (unsigned long insn,
long value ATTRIBUTE_UNUSED,
@@ -597,7 +607,6 @@ extract_bba (unsigned long insn,
/* The BD field in a B form instruction. The lower two bits are
forced to zero. */
-/*ARGSUSED*/
static unsigned long
insert_bd (unsigned long insn,
long value,
@@ -607,7 +616,6 @@ insert_bd (unsigned long insn,
return insn | (value & 0xfffc);
}
-/*ARGSUSED*/
static long
extract_bd (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -629,7 +637,6 @@ extract_bd (unsigned long insn,
in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
for branch on CTR. We only handle the taken/not-taken hint here. */
-/*ARGSUSED*/
static unsigned long
insert_bdm (unsigned long insn,
long value,
@@ -675,7 +682,6 @@ extract_bdm (unsigned long insn,
This is like BDM, above, except that the branch is expected to be
taken. */
-/*ARGSUSED*/
static unsigned long
insert_bdp (unsigned long insn,
long value,
@@ -829,7 +835,6 @@ extract_boe (unsigned long insn,
/* The DQ field in a DQ form instruction. This is like D, but the
lower four bits are forced to zero. */
-/*ARGSUSED*/
static unsigned long
insert_dq (unsigned long insn,
long value,
@@ -841,7 +846,6 @@ insert_dq (unsigned long insn,
return insn | (value & 0xfff0);
}
-/*ARGSUSED*/
static long
extract_dq (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -916,7 +920,6 @@ extract_ev8 (unsigned long insn,
/* The DS field in a DS form instruction. This is like D, but the
lower two bits are forced to zero. */
-/*ARGSUSED*/
static unsigned long
insert_ds (unsigned long insn,
long value,
@@ -928,7 +931,6 @@ insert_ds (unsigned long insn,
return insn | (value & 0xfffc);
}
-/*ARGSUSED*/
static long
extract_ds (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -939,7 +941,6 @@ extract_ds (unsigned long insn,
/* The DE field in a DE form instruction. */
-/*ARGSUSED*/
static unsigned long
insert_de (unsigned long insn,
long value,
@@ -951,7 +952,6 @@ insert_de (unsigned long insn,
return insn | ((value << 4) & 0xfff0);
}
-/*ARGSUSED*/
static long
extract_de (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -962,7 +962,6 @@ extract_de (unsigned long insn,
/* The DES field in a DES form instruction. */
-/*ARGSUSED*/
static unsigned long
insert_des (unsigned long insn,
long value,
@@ -976,7 +975,6 @@ insert_des (unsigned long insn,
return insn | ((value << 2) & 0xfff0);
}
-/*ARGSUSED*/
static long
extract_des (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -1049,7 +1047,6 @@ extract_fxm (unsigned long insn,
/* The LI field in an I form instruction. The lower two bits are
forced to zero. */
-/*ARGSUSED*/
static unsigned long
insert_li (unsigned long insn,
long value,
@@ -1061,7 +1058,6 @@ insert_li (unsigned long insn,
return insn | (value & 0x3fffffc);
}
-/*ARGSUSED*/
static long
extract_li (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -1161,7 +1157,6 @@ extract_mbe (unsigned long insn,
/* The MB or ME field in an MD or MDS form instruction. The high bit
is wrapped to the low end. */
-/*ARGSUSED*/
static unsigned long
insert_mb6 (unsigned long insn,
long value,
@@ -1171,7 +1166,6 @@ insert_mb6 (unsigned long insn,
return insn | ((value & 0x1f) << 6) | (value & 0x20);
}
-/*ARGSUSED*/
static long
extract_mb6 (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -1196,7 +1190,6 @@ insert_nb (unsigned long insn,
return insn | ((value & 0x1f) << 11);
}
-/*ARGSUSED*/
static long
extract_nb (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -1215,7 +1208,6 @@ extract_nb (unsigned long insn,
invalid, since we never want to recognize an instruction which uses
a field of this type. */
-/*ARGSUSED*/
static unsigned long
insert_nsi (unsigned long insn,
long value,
@@ -1267,7 +1259,6 @@ insert_ram (unsigned long insn,
/* The RA field in the DQ form lq instruction, which has special
value restrictions. */
-/*ARGSUSED*/
static unsigned long
insert_raq (unsigned long insn,
long value,
@@ -1302,7 +1293,6 @@ insert_ras (unsigned long insn,
function just copies the BT field into the BA field, and the
extraction function just checks that the fields are the same. */
-/*ARGSUSED*/
static unsigned long
insert_rbs (unsigned long insn,
long value ATTRIBUTE_UNUSED,
@@ -1325,7 +1315,6 @@ extract_rbs (unsigned long insn,
/* The RT field of the DQ form lq instruction, which has special
value restrictions. */
-/*ARGSUSED*/
static unsigned long
insert_rtq (unsigned long insn,
long value,
@@ -1340,7 +1329,6 @@ insert_rtq (unsigned long insn,
/* The RS field of the DS form stq instruction, which has special
value restrictions. */
-/*ARGSUSED*/
static unsigned long
insert_rsq (unsigned long insn,
long value ATTRIBUTE_UNUSED,
@@ -1354,7 +1342,6 @@ insert_rsq (unsigned long insn,
/* The SH field in an MD form instruction. This is split. */
-/*ARGSUSED*/
static unsigned long
insert_sh6 (unsigned long insn,
long value,
@@ -1364,7 +1351,6 @@ insert_sh6 (unsigned long insn,
return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
}
-/*ARGSUSED*/
static long
extract_sh6 (unsigned long insn,
int dialect ATTRIBUTE_UNUSED,
@@ -4282,8 +4268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
-{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
-{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
+{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAO, SHO } },
{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index a23110f..c0e1a2e 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -49,18 +49,28 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
switch (op->arg[n])
{
case A_IND_N:
+ case AX_IND_N:
+ case AXY_IND_N:
+ case AY_IND_N:
+ case AYX_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_INC_N:
+ case AX_INC_N:
+ case AXY_INC_N:
+ case AY_INC_N:
+ case AYX_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
- case A_PMOD_N:
+ case AX_PMOD_N:
+ case AXY_PMOD_N:
fprintf_fn (stream, "@r%d+r8", rn);
break;
- case A_PMODY_N:
+ case AY_PMOD_N:
+ case AYX_PMOD_N:
fprintf_fn (stream, "@r%d+r9", rn);
break;
- case DSP_REG_M:
+ case DSP_REG_A_M:
fprintf_fn (stream, "a%c", '0' + rm);
break;
case DSP_REG_X:
@@ -69,6 +79,26 @@ print_movxy (op, rn, rm, fprintf_fn, stream)
case DSP_REG_Y:
fprintf_fn (stream, "y%c", '0' + rm);
break;
+ case DSP_REG_AX:
+ fprintf_fn (stream, "%c%c",
+ (rm & 1) ? 'x' : 'a',
+ (rm & 2) ? '1' : '0');
+ break;
+ case DSP_REG_XY:
+ fprintf_fn (stream, "%c%c",
+ (rm & 1) ? 'y' : 'x',
+ (rm & 2) ? '1' : '0');
+ break;
+ case DSP_REG_AY:
+ fprintf_fn (stream, "%c%c",
+ (rm & 2) ? 'y' : 'a',
+ (rm & 1) ? '1' : '0');
+ break;
+ case DSP_REG_YX:
+ fprintf_fn (stream, "%c%c",
+ (rm & 2) ? 'x' : 'y',
+ (rm & 1) ? '1' : '0');
+ break;
default:
abort ();
}
@@ -102,7 +132,41 @@ print_insn_ddt (insn, info)
/* Check if either the x or y part is invalid. */
if (((insn & 0xc) == 0 && (insn & 0x2a0))
|| ((insn & 3) == 0 && (insn & 0x150)))
- fprintf_fn (stream, ".word 0x%x", insn);
+ if (info->mach != bfd_mach_sh_dsp
+ && info->mach != bfd_mach_sh3_dsp)
+ {
+ static const sh_opcode_info *first_movx, *first_movy;
+ const sh_opcode_info *op;
+ int is_movy;
+
+ if (! first_movx)
+ {
+ for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
+ first_movx++;
+ for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
+ first_movy++;
+ }
+
+ is_movy = ((insn & 3) != 0);
+
+ if (is_movy)
+ op = first_movy;
+ else
+ op = first_movx;
+
+ while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
+ || op->nibbles[3] != (unsigned) (insn & 0xf))
+ op++;
+
+ print_movxy (op,
+ (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
+ + 2 * is_movy
+ + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
+ (insn >> 6) & 3,
+ fprintf_fn, stream);
+ }
+ else
+ fprintf_fn (stream, ".word 0x%x", insn);
else
{
static const sh_opcode_info *first_movx, *first_movy;
@@ -191,6 +255,7 @@ print_insn_ppi (field_b, info)
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
unsigned int nib1, nib2, nib3;
+ unsigned int altnib1, nib4;
char *dc = NULL;
const sh_opcode_info *op;
@@ -217,6 +282,16 @@ print_insn_ppi (field_b, info)
sy_tab[(field_b >> 4) & 3],
du_tab[(field_b >> 0) & 3]);
}
+ else if ((field_b & 0xf0) == 0x10
+ && info->mach != bfd_mach_sh_dsp
+ && info->mach != bfd_mach_sh3_dsp)
+ {
+ fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
+ }
+ else if ((field_b & 0xf3) != 0)
+ {
+ fprintf_fn (stream, ".word 0x%x\t", field_b);
+ }
fprintf_fn (stream, "pmuls%c%s,%s,%s",
field_b & 0x2000 ? ' ' : '\t',
se_tab[(field_b >> 10) & 3],
@@ -228,6 +303,7 @@ print_insn_ppi (field_b, info)
nib1 = PPIC;
nib2 = field_b >> 12 & 0xf;
nib3 = field_b >> 8 & 0xf;
+ nib4 = field_b >> 4 & 0xf;
switch (nib3 & 0x3)
{
case 0:
@@ -246,14 +322,41 @@ print_insn_ppi (field_b, info)
nib3 -= 2;
break;
}
+ if (nib1 == PPI3)
+ altnib1 = PPI3NC;
+ else
+ altnib1 = nib1;
for (op = sh_table; op->name; op++)
{
- if (op->nibbles[1] == nib1
+ if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
&& op->nibbles[2] == nib2
&& op->nibbles[3] == nib3)
{
int n;
+ switch (op->nibbles[4])
+ {
+ case HEX_0:
+ break;
+ case HEX_XX00:
+ if ((nib4 & 3) != 0)
+ continue;
+ break;
+ case HEX_1:
+ if ((nib4 & 3) != 1)
+ continue;
+ break;
+ case HEX_00YY:
+ if ((nib4 & 0xc) != 0)
+ continue;
+ break;
+ case HEX_4:
+ if ((nib4 & 0xc) != 4)
+ continue;
+ break;
+ default:
+ abort ();
+ }
fprintf_fn (stream, "%s%s\t", dc, op->name);
for (n = 0; n < 3 && op->arg[n] != A_END; n++)
{
@@ -331,8 +434,16 @@ print_insn_sh (memaddr, info)
target_arch = arch_sh3e;
break;
case bfd_mach_sh4:
+ case bfd_mach_sh4_nofpu:
target_arch = arch_sh4;
break;
+ case bfd_mach_sh4a:
+ case bfd_mach_sh4a_nofpu:
+ target_arch = arch_sh4a;
+ break;
+ case bfd_mach_sh4al_dsp:
+ target_arch = arch_sh4al_dsp;
+ break;
case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
status = print_insn_sh64 (memaddr, info);
@@ -514,18 +625,21 @@ print_insn_sh (memaddr, info)
fprintf_fn (stream, "r%d", rn);
break;
case A_INC_N:
+ case AS_INC_N:
fprintf_fn (stream, "@r%d+", rn);
break;
case A_DEC_N:
+ case AS_DEC_N:
fprintf_fn (stream, "@-r%d", rn);
break;
case A_IND_N:
+ case AS_IND_N:
fprintf_fn (stream, "@r%d", rn);
break;
case A_DISP_REG_N:
fprintf_fn (stream, "@(%d,r%d)", imm, rn);
break;
- case A_PMOD_N:
+ case AS_PMOD_N:
fprintf_fn (stream, "@r%d+r8", rn);
break;
case A_REG_M:
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index f415e5e..b9e103c 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -34,6 +34,8 @@ typedef enum
HEX_D,
HEX_E,
HEX_F,
+ HEX_XX00,
+ HEX_00YY,
REG_N,
REG_M,
SDT_REG_N,
@@ -60,9 +62,12 @@ typedef enum
NOPY,
MOVX,
MOVY,
+ MOVX_NOPY,
+ MOVY_NOPX,
PSH,
PMUL,
PPI3,
+ PPI3NC,
PDC,
PPIC,
REPEAT
@@ -88,8 +93,6 @@ typedef enum
A_INC_N,
A_IND_M,
A_IND_N,
- A_PMOD_N,
- A_PMODY_N,
A_IND_R0_REG_M,
A_IND_R0_REG_N,
A_MACH,
@@ -113,6 +116,27 @@ typedef enum
DSP_REG_E,
DSP_REG_F,
DSP_REG_G,
+ DSP_REG_A_M,
+ DSP_REG_AX,
+ DSP_REG_XY,
+ DSP_REG_AY,
+ DSP_REG_YX,
+ AX_INC_N,
+ AY_INC_N,
+ AXY_INC_N,
+ AYX_INC_N,
+ AX_IND_N,
+ AY_IND_N,
+ AXY_IND_N,
+ AYX_IND_N,
+ AX_PMOD_N,
+ AXY_PMOD_N,
+ AY_PMOD_N,
+ AYX_PMOD_N,
+ AS_DEC_N,
+ AS_INC_N,
+ AS_IND_N,
+ AS_PMOD_N,
A_A0,
A_X0,
A_X1,
@@ -156,24 +180,34 @@ sh_dsp_reg_nums;
#define arch_sh3e 0x0008
#define arch_sh4 0x0010
#define arch_sh2e 0x0020
+#define arch_sh4a 0x0040
#define arch_sh_dsp 0x0100
#define arch_sh3_dsp 0x0200
+#define arch_sh4al_dsp 0x0400
+#define arch_sh4_nofpu 0x1000
+#define arch_sh4a_nofpu 0x2000
#define arch_sh1_up (arch_sh1 | arch_sh2_up)
#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
#define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
-#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp)
+#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
+ | arch_sh4_nofp_up)
#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
-#define arch_sh4_up arch_sh4
+#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
+#define arch_sh4a_up (arch_sh4a)
#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
-#define arch_sh3_dsp_up arch_sh3_dsp
+#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
+#define arch_sh4al_dsp_up (arch_sh4al_dsp)
+
+#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
+#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
typedef struct
{
char *name;
sh_arg_type arg[4];
- sh_nibble_type nibbles[4];
+ sh_nibble_type nibbles[5];
int arch;
} sh_opcode_info;
@@ -211,6 +245,8 @@ const sh_opcode_info sh_table[] =
/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
+/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
+
/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
@@ -249,6 +285,8 @@ const sh_opcode_info sh_table[] =
/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
+/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
+
/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
@@ -269,7 +307,7 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up},
-/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up},
+/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up},
@@ -289,10 +327,13 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up},
-/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up},
+/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up},
/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
+/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
+/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
+
/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
@@ -414,11 +455,16 @@ const sh_opcode_info sh_table[] =
/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
-/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up},
+/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up},
+/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
+/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
+/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
+/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
+
/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
@@ -434,11 +480,11 @@ const sh_opcode_info sh_table[] =
/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
-/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up},
+/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up},
-/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up},
+/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up},
-/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up},
+/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up},
/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
@@ -447,7 +493,9 @@ const sh_opcode_info sh_table[] =
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
-/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up},
+/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up},
+
+/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
@@ -461,6 +509,9 @@ const sh_opcode_info sh_table[] =
/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
+/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
+/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
+
/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
@@ -514,9 +565,9 @@ const sh_opcode_info sh_table[] =
/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up},
-/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up},
+/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up},
-/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up},
+/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up},
@@ -536,9 +587,9 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
-/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up},
+/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up},
-/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up},
+/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up},
/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up},
@@ -596,6 +647,8 @@ const sh_opcode_info sh_table[] =
/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
+/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
+
/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
@@ -634,7 +687,7 @@ const sh_opcode_info sh_table[] =
/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
-/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
+/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
@@ -642,7 +695,7 @@ const sh_opcode_info sh_table[] =
/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
-/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
+/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
@@ -650,7 +703,7 @@ const sh_opcode_info sh_table[] =
/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
-/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
+/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
@@ -658,22 +711,51 @@ const sh_opcode_info sh_table[] =
/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
-/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
+/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
-/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
-/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
-/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
-/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
-/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
-/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
-/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
-/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
-/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
-/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
-/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
-/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
+/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
+/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
+/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
+/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
+/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
+/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
+
+/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
+/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
+/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
+/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
+/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
+/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
+
+/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
+/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
+/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
+/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
+/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
+/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
+
+/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
+/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
+/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
+/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
+/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
+/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
+
+/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
+/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
+/* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
+/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
+/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
+/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
+
+/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
+/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
+/* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
+/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
+/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
+/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
@@ -687,13 +769,21 @@ const sh_opcode_info sh_table[] =
/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
-{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up},
+{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
+/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
+{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
-{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up},
+{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
+/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
+{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
-{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up},
+{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
+/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
+{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
-{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up},
+{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
+/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
+{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
@@ -706,6 +796,8 @@ const sh_opcode_info sh_table[] =
/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
+/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
+{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
@@ -718,16 +810,16 @@ const sh_opcode_info sh_table[] =
{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
-/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */
-{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up},
-/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
-{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up},
+/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
+{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
+/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
+{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
/* 10001101xxyynnnn pclr <DSP_REG_N> */
{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
-/* 10011101xxyynnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
-{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up},
-/* 10111101xxyynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
-{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up},
+/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
+{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
+/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
+{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */
{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */
@@ -744,6 +836,10 @@ const sh_opcode_info sh_table[] =
{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
+/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
+{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
+/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
+{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up},
@@ -828,13 +924,19 @@ const sh_opcode_info sh_table[] =
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up},
+/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
+
/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
+/* 1111nnn011111101 fsca FPUL,<F_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_F,HEX_D}, arch_sh4a_up},
+
/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up},
/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
+/* 1111nnnn01111101 fssra <F_REG_N> */{"fssra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4a_up},
+
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
diff --git a/opcodes/z8k-dis.c b/opcodes/z8k-dis.c
index 5d15ee8..02f5dcb 100644
--- a/opcodes/z8k-dis.c
+++ b/opcodes/z8k-dis.c
@@ -24,7 +24,7 @@
#define DEFINE_TABLE
#include "z8k-opc.h"
-
+
#include <setjmp.h>
typedef struct
@@ -53,9 +53,6 @@ typedef struct
}
instr_data_s;
-static int fetch_data PARAMS ((struct disassemble_info *, int));
-
-
/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
to ADDR (exclusive) are valid. Returns 1 for success, longjmps
on error. */
@@ -64,9 +61,7 @@ static int fetch_data PARAMS ((struct disassemble_info *, int));
? 1 : fetch_data ((info), (nibble)))
static int
-fetch_data (info, nibble)
- struct disassemble_info *info;
- int nibble;
+fetch_data (struct disassemble_info *info, int nibble)
{
unsigned char mybuf[20];
int status;
@@ -142,18 +137,13 @@ static char *ctrl_names[8] =
};
static int seg_length;
-static int print_insn_z8k PARAMS ((bfd_vma, disassemble_info *, int));
-int z8k_lookup_instr PARAMS ((unsigned char *, disassemble_info *));
-static void output_instr
- PARAMS ((instr_data_s *, unsigned long, disassemble_info *));
-static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *));
-static void unparse_instr PARAMS ((instr_data_s *, int));
+int z8k_lookup_instr (unsigned char *, disassemble_info *);
+static void output_instr (instr_data_s *, unsigned long, disassemble_info *);
+static void unpack_instr (instr_data_s *, int, disassemble_info *);
+static void unparse_instr (instr_data_s *, int);
static int
-print_insn_z8k (addr, info, is_segmented)
- bfd_vma addr;
- disassemble_info *info;
- int is_segmented;
+print_insn_z8k (bfd_vma addr, disassemble_info *info, int is_segmented)
{
instr_data_s instr_data;
@@ -186,27 +176,20 @@ print_insn_z8k (addr, info, is_segmented)
}
int
-print_insn_z8001 (addr, info)
- bfd_vma addr;
- disassemble_info *info;
+print_insn_z8001 (bfd_vma addr, disassemble_info *info)
{
return print_insn_z8k (addr, info, 1);
}
int
-print_insn_z8002 (addr, info)
- bfd_vma addr;
- disassemble_info *info;
+print_insn_z8002 (bfd_vma addr, disassemble_info *info)
{
return print_insn_z8k (addr, info, 0);
}
int
-z8k_lookup_instr (nibbles, info)
- unsigned char *nibbles;
- disassemble_info *info;
+z8k_lookup_instr (unsigned char *nibbles, disassemble_info *info)
{
-
int nibl_index, tabl_index;
int nibl_matched;
int need_fetch = 0;
@@ -295,10 +278,9 @@ z8k_lookup_instr (nibbles, info)
}
static void
-output_instr (instr_data, addr, info)
- instr_data_s *instr_data;
- unsigned long addr ATTRIBUTE_UNUSED;
- disassemble_info *info;
+output_instr (instr_data_s *instr_data,
+ unsigned long addr ATTRIBUTE_UNUSED,
+ disassemble_info *info)
{
int num_bytes;
char out_str[100];
@@ -314,10 +296,7 @@ output_instr (instr_data, addr, info)
}
static void
-unpack_instr (instr_data, is_segmented, info)
- instr_data_s *instr_data;
- int is_segmented;
- disassemble_info *info;
+unpack_instr (instr_data_s *instr_data, int is_segmented, disassemble_info *info)
{
int nibl_count, loop;
unsigned short instr_nibl, instr_byte, instr_word;
@@ -501,9 +480,7 @@ static char *intr_names[] = {
};
static void
-unparse_instr (instr_data, is_segmented)
- instr_data_s *instr_data;
- int is_segmented;
+unparse_instr (instr_data_s *instr_data, int is_segmented)
{
unsigned short datum_value;
unsigned int tabl_datum, datum_class;
diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h
index c714bde..4caedd4 100644
--- a/opcodes/z8k-opc.h
+++ b/opcodes/z8k-opc.h
@@ -1,117 +1,117 @@
/* DO NOT EDIT! -*- buffer-read-only: t -*-
This file is automatically generated by z8kgen. */
-#define ARG_MASK 0x0f
-#define ARG_SRC 0x01
-#define ARG_DST 0x02
-#define ARG_RS 0x01
-#define ARG_RD 0x02
-#define ARG_RA 0x03
-#define ARG_RB 0x04
-#define ARG_RR 0x05
-#define ARG_RX 0x06
-#define ARG_IMM4 0x01
-#define ARG_IMM8 0x02
-#define ARG_IMM16 0x03
-#define ARG_IMM32 0x04
-#define ARG_IMMN 0x05
-#define ARG_IMMNMINUS1 0x05
-#define ARG_IMM_1 0x06
-#define ARG_IMM_2 0x07
-#define ARG_DISP16 0x08
-#define ARG_NIM8 0x09
-#define ARG_IMM2 0x0a
-#define ARG_IMM1OR2 0x0b
-#define ARG_DISP12 0x0b
-#define ARG_NIM4 0x0c
-#define ARG_DISP8 0x0c
-#define ARG_IMM4M1 0x0d
-#define CLASS_X 0x10
-#define CLASS_BA 0x20
-#define CLASS_DA 0x30
-#define CLASS_BX 0x40
-#define CLASS_DISP 0x50
-#define CLASS_IMM 0x60
-#define CLASS_CC 0x70
-#define CLASS_CTRL 0x80
-#define CLASS_IGNORE 0x90
-#define CLASS_ADDRESS 0xd0
-#define CLASS_0CCC 0xe0
-#define CLASS_1CCC 0xf0
-#define CLASS_0DISP7 0x100
-#define CLASS_1DISP7 0x200
-#define CLASS_01II 0x300
-#define CLASS_00II 0x400
-#define CLASS_BIT 0x500
-#define CLASS_FLAGS 0x600
-#define CLASS_IR 0x700
+#define ARG_MASK 0x0f
+#define ARG_SRC 0x01
+#define ARG_DST 0x02
+#define ARG_RS 0x01
+#define ARG_RD 0x02
+#define ARG_RA 0x03
+#define ARG_RB 0x04
+#define ARG_RR 0x05
+#define ARG_RX 0x06
+#define ARG_IMM4 0x01
+#define ARG_IMM8 0x02
+#define ARG_IMM16 0x03
+#define ARG_IMM32 0x04
+#define ARG_IMMN 0x05
+#define ARG_IMMNMINUS1 0x05
+#define ARG_IMM_1 0x06
+#define ARG_IMM_2 0x07
+#define ARG_DISP16 0x08
+#define ARG_NIM8 0x09
+#define ARG_IMM2 0x0a
+#define ARG_IMM1OR2 0x0b
+#define ARG_DISP12 0x0b
+#define ARG_NIM4 0x0c
+#define ARG_DISP8 0x0c
+#define ARG_IMM4M1 0x0d
+#define CLASS_X 0x10
+#define CLASS_BA 0x20
+#define CLASS_DA 0x30
+#define CLASS_BX 0x40
+#define CLASS_DISP 0x50
+#define CLASS_IMM 0x60
+#define CLASS_CC 0x70
+#define CLASS_CTRL 0x80
+#define CLASS_IGNORE 0x90
+#define CLASS_ADDRESS 0xd0
+#define CLASS_0CCC 0xe0
+#define CLASS_1CCC 0xf0
+#define CLASS_0DISP7 0x100
+#define CLASS_1DISP7 0x200
+#define CLASS_01II 0x300
+#define CLASS_00II 0x400
+#define CLASS_BIT 0x500
+#define CLASS_FLAGS 0x600
+#define CLASS_IR 0x700
#define CLASS_IRO 0x800
#define CLASS_DISP8 0x900
#define CLASS_BIT_1OR2 0xa00
-#define CLASS_REG 0x7000
-#define CLASS_REG_BYTE 0x2000
-#define CLASS_REG_WORD 0x3000
-#define CLASS_REG_QUAD 0x4000
-#define CLASS_REG_LONG 0x5000
-#define CLASS_REGN0 0x8000
-#define CLASS_PR 0x10000
+#define CLASS_REG 0x7000
+#define CLASS_REG_BYTE 0x2000
+#define CLASS_REG_WORD 0x3000
+#define CLASS_REG_QUAD 0x4000
+#define CLASS_REG_LONG 0x5000
+#define CLASS_REGN0 0x8000
+#define CLASS_PR 0x10000
#define CLASS_MASK 0x1fff0
-#define OPC_adc 0
-#define OPC_adcb 1
-#define OPC_add 2
-#define OPC_addb 3
-#define OPC_addl 4
-#define OPC_and 5
-#define OPC_andb 6
-#define OPC_bit 7
-#define OPC_bitb 8
-#define OPC_call 9
-#define OPC_calr 10
-#define OPC_clr 11
-#define OPC_clrb 12
-#define OPC_com 13
-#define OPC_comb 14
-#define OPC_comflg 15
-#define OPC_cp 16
-#define OPC_cpb 17
-#define OPC_cpd 18
-#define OPC_cpdb 19
-#define OPC_cpdr 20
-#define OPC_cpdrb 21
-#define OPC_cpi 22
-#define OPC_cpib 23
-#define OPC_cpir 24
-#define OPC_cpirb 25
-#define OPC_cpl 26
-#define OPC_cpsd 27
-#define OPC_cpsdb 28
-#define OPC_cpsdr 29
-#define OPC_cpsdrb 30
-#define OPC_cpsi 31
-#define OPC_cpsib 32
-#define OPC_cpsir 33
-#define OPC_cpsirb 34
-#define OPC_dab 35
-#define OPC_dbjnz 36
-#define OPC_dec 37
-#define OPC_decb 38
-#define OPC_di 39
-#define OPC_div 40
-#define OPC_divl 41
-#define OPC_djnz 42
-#define OPC_ei 43
-#define OPC_ex 44
-#define OPC_exb 45
-#define OPC_exts 46
-#define OPC_extsb 47
-#define OPC_extsl 48
-#define OPC_halt 49
-#define OPC_in 50
-#define OPC_inb 51
-#define OPC_inc 52
-#define OPC_incb 53
-#define OPC_ind 54
-#define OPC_indb 55
+#define OPC_adc 0
+#define OPC_adcb 1
+#define OPC_add 2
+#define OPC_addb 3
+#define OPC_addl 4
+#define OPC_and 5
+#define OPC_andb 6
+#define OPC_bit 7
+#define OPC_bitb 8
+#define OPC_call 9
+#define OPC_calr 10
+#define OPC_clr 11
+#define OPC_clrb 12
+#define OPC_com 13
+#define OPC_comb 14
+#define OPC_comflg 15
+#define OPC_cp 16
+#define OPC_cpb 17
+#define OPC_cpd 18
+#define OPC_cpdb 19
+#define OPC_cpdr 20
+#define OPC_cpdrb 21
+#define OPC_cpi 22
+#define OPC_cpib 23
+#define OPC_cpir 24
+#define OPC_cpirb 25
+#define OPC_cpl 26
+#define OPC_cpsd 27
+#define OPC_cpsdb 28
+#define OPC_cpsdr 29
+#define OPC_cpsdrb 30
+#define OPC_cpsi 31
+#define OPC_cpsib 32
+#define OPC_cpsir 33
+#define OPC_cpsirb 34
+#define OPC_dab 35
+#define OPC_dbjnz 36
+#define OPC_dec 37
+#define OPC_decb 38
+#define OPC_di 39
+#define OPC_div 40
+#define OPC_divl 41
+#define OPC_djnz 42
+#define OPC_ei 43
+#define OPC_ex 44
+#define OPC_exb 45
+#define OPC_exts 46
+#define OPC_extsb 47
+#define OPC_extsl 48
+#define OPC_halt 49
+#define OPC_in 50
+#define OPC_inb 51
+#define OPC_inc 52
+#define OPC_incb 53
+#define OPC_ind 54
+#define OPC_indb 55
#define OPC_indr 56
#define OPC_indrb 57
#define OPC_ini 58
@@ -1801,21 +1801,21 @@ const opcode_entry_type z8k_table[] = {
"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),},
{CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,74},
-/* 0010 0000 0000 dddd imm8 imm8 *** ldb rbd,imm8 */
+/* 1100 dddd imm8 *** ldb rbd,imm8 */
{
#ifdef NICENAMES
-"ldb rbd,imm8",8,7,0x00,
+"ldb rbd,imm8",8,5,0x00,
#endif
"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
- {CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74},
+ {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,74},
-/* 1100 dddd imm8 *** ldb rbd,imm8 */
+/* 0010 0000 0000 dddd imm8 imm8 *** ldb rbd,imm8 */
{
#ifdef NICENAMES
-"ldb rbd,imm8",8,5,0x00,
+"ldb rbd,imm8",8,7,0x00,
#endif
"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),},
- {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,74},
+ {CLASS_BIT+2,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,74},
/* 1010 0000 ssss dddd *** ldb rbd,rbs */
{
diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c
index df72791..9e46809 100644
--- a/opcodes/z8kgen.c
+++ b/opcodes/z8kgen.c
@@ -36,7 +36,7 @@ struct op
};
#define iswhite(x) ((x) == ' ' || (x) == '\t')
-struct op opt[] =
+static struct op opt[] =
{
{"------", 2, 8, "0011 0110 0000 0000", "bpt", 0}, /* Breakpoint used by the simulator. */
{"------", 10, 8, "0000 1111 0000 1100", "brk", 0}, /* Breakpoint used by real hardware.
@@ -265,8 +265,8 @@ struct op opt[] =
{"------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0},
{"------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0},
{"------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0},
- {"------", 7, 8, "0010 0000 0000 dddd imm8 imm8", "ldb rbd,imm8", 0},
{"------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0},
+ {"------", 7, 8, "0010 0000 0000 dddd imm8 imm8", "ldb rbd,imm8", 0},
{"------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0},
{"------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0},
{"------", 14, 8, "0111 0000 ssN0 dddd 0000 xxxx 0000 0000", "ldb rbd,rs(rx)", 0},
@@ -552,7 +552,7 @@ struct op opt[] =
};
static int
-count ()
+count (void)
{
struct op *p = opt;
int r = 0;
@@ -567,9 +567,7 @@ count ()
}
static int
-func (a, b)
- struct op *a;
- struct op *b;
+func (struct op *a, struct op *b)
{
return strcmp ((a)->name, (b)->name);
}
@@ -588,7 +586,7 @@ struct tok_struct
int length;
};
-struct tok_struct args[] =
+static struct tok_struct args[] =
{
{"address_src(rs)", "CLASS_X+(ARG_RS)",},
{"address_dst(rd)", "CLASS_X+(ARG_RD)",},
@@ -649,7 +647,7 @@ struct tok_struct args[] =
{0, 0}
};
-struct tok_struct toks[] =
+static struct tok_struct toks[] =
{
{"0000", "CLASS_BIT+0", 1},
{"0001", "CLASS_BIT+1", 1},
@@ -728,11 +726,8 @@ struct tok_struct toks[] =
{0, 0}
};
-char *
-translate (table, x, length)
- struct tok_struct *table;
- char *x;
- int *length;
+static char *
+translate (struct tok_struct *table, char *x, int *length)
{
int found;
@@ -760,9 +755,7 @@ translate (table, x, length)
}
static void
-chewbits (bits, length)
- char *bits;
- int *length;
+chewbits (char *bits, int *length)
{
int n = 0;
@@ -788,8 +781,7 @@ chewbits (bits, length)
}
static int
-chewname (name)
- char **name;
+chewname (char **name)
{
char *n;
int nargs = 0;
@@ -830,9 +822,7 @@ chewname (name)
}
static void
-sub (x, c)
- char *x;
- char c;
+sub (char *x, char c)
{
while (*x)
{
@@ -851,8 +841,7 @@ sub (x, c)
#define D(x) ((x) == '1' || (x) =='0')
#define M(y) (strncmp(y,x,4)==0)
static void
-printmangled (x)
- char *x;
+printmangled (char *x)
{
return;
while (*x)
@@ -886,8 +875,7 @@ printmangled (x)
/*#define WORK_TYPE*/
static void
-print_type (n)
- struct op *n;
+print_type (struct op *n)
{
#ifdef WORK_TYPE
while (*s && !iswhite (*s))
@@ -913,7 +901,7 @@ print_type (n)
}
static void
-internal ()
+internal (void)
{
int c = count ();
struct op *new = (struct op *) xmalloc (sizeof (struct op) * c);
@@ -921,7 +909,7 @@ internal ()
memcpy (new, p, c * sizeof (struct op));
/* Sort all names in table alphabetically. */
- qsort (new, c, sizeof (struct op), func);
+ qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *))func);
p = new;
while (p->flags && p->flags[0] != '*')
@@ -966,7 +954,7 @@ internal ()
}
static void
-gas ()
+gas (void)
{
int c = count ();
struct op *p = opt;
@@ -977,129 +965,129 @@ gas ()
memcpy (new, p, c * sizeof (struct op));
/* Sort all names in table alphabetically. */
- qsort (new, c, sizeof (struct op), func);
+ qsort (new, c, sizeof (struct op), (int (*)(const void *, const void *))func);
printf ("/* DO NOT EDIT! -*- buffer-read-only: t -*-\n");
printf (" This file is automatically generated by z8kgen. */\n\n");
- printf ("#define ARG_MASK 0x0f\n");
-
- printf ("#define ARG_SRC 0x01\n");
- printf ("#define ARG_DST 0x02\n");
-
- printf ("#define ARG_RS 0x01\n");
- printf ("#define ARG_RD 0x02\n");
- printf ("#define ARG_RA 0x03\n");
- printf ("#define ARG_RB 0x04\n");
- printf ("#define ARG_RR 0x05\n");
- printf ("#define ARG_RX 0x06\n");
-
- printf ("#define ARG_IMM4 0x01\n");
- printf ("#define ARG_IMM8 0x02\n");
- printf ("#define ARG_IMM16 0x03\n");
- printf ("#define ARG_IMM32 0x04\n");
- printf ("#define ARG_IMMN 0x05\n");
- printf ("#define ARG_IMMNMINUS1 0x05\n");
- printf ("#define ARG_IMM_1 0x06\n");
- printf ("#define ARG_IMM_2 0x07\n");
- printf ("#define ARG_DISP16 0x08\n");
- printf ("#define ARG_NIM8 0x09\n");
- printf ("#define ARG_IMM2 0x0a\n");
- printf ("#define ARG_IMM1OR2 0x0b\n");
-
- printf ("#define ARG_DISP12 0x0b\n");
- printf ("#define ARG_NIM4 0x0c\n");
- printf ("#define ARG_DISP8 0x0c\n");
- printf ("#define ARG_IMM4M1 0x0d\n");
-
- printf ("#define CLASS_X 0x10\n");
- printf ("#define CLASS_BA 0x20\n");
- printf ("#define CLASS_DA 0x30\n");
- printf ("#define CLASS_BX 0x40\n");
- printf ("#define CLASS_DISP 0x50\n");
- printf ("#define CLASS_IMM 0x60\n");
- printf ("#define CLASS_CC 0x70\n");
- printf ("#define CLASS_CTRL 0x80\n");
- printf ("#define CLASS_IGNORE 0x90\n");
- printf ("#define CLASS_ADDRESS 0xd0\n");
- printf ("#define CLASS_0CCC 0xe0\n");
- printf ("#define CLASS_1CCC 0xf0\n");
- printf ("#define CLASS_0DISP7 0x100\n");
- printf ("#define CLASS_1DISP7 0x200\n");
- printf ("#define CLASS_01II 0x300\n");
- printf ("#define CLASS_00II 0x400\n");
- printf ("#define CLASS_BIT 0x500\n");
- printf ("#define CLASS_FLAGS 0x600\n");
- printf ("#define CLASS_IR 0x700\n");
+ printf ("#define ARG_MASK 0x0f\n");
+
+ printf ("#define ARG_SRC 0x01\n");
+ printf ("#define ARG_DST 0x02\n");
+
+ printf ("#define ARG_RS 0x01\n");
+ printf ("#define ARG_RD 0x02\n");
+ printf ("#define ARG_RA 0x03\n");
+ printf ("#define ARG_RB 0x04\n");
+ printf ("#define ARG_RR 0x05\n");
+ printf ("#define ARG_RX 0x06\n");
+
+ printf ("#define ARG_IMM4 0x01\n");
+ printf ("#define ARG_IMM8 0x02\n");
+ printf ("#define ARG_IMM16 0x03\n");
+ printf ("#define ARG_IMM32 0x04\n");
+ printf ("#define ARG_IMMN 0x05\n");
+ printf ("#define ARG_IMMNMINUS1 0x05\n");
+ printf ("#define ARG_IMM_1 0x06\n");
+ printf ("#define ARG_IMM_2 0x07\n");
+ printf ("#define ARG_DISP16 0x08\n");
+ printf ("#define ARG_NIM8 0x09\n");
+ printf ("#define ARG_IMM2 0x0a\n");
+ printf ("#define ARG_IMM1OR2 0x0b\n");
+
+ printf ("#define ARG_DISP12 0x0b\n");
+ printf ("#define ARG_NIM4 0x0c\n");
+ printf ("#define ARG_DISP8 0x0c\n");
+ printf ("#define ARG_IMM4M1 0x0d\n");
+
+ printf ("#define CLASS_X 0x10\n");
+ printf ("#define CLASS_BA 0x20\n");
+ printf ("#define CLASS_DA 0x30\n");
+ printf ("#define CLASS_BX 0x40\n");
+ printf ("#define CLASS_DISP 0x50\n");
+ printf ("#define CLASS_IMM 0x60\n");
+ printf ("#define CLASS_CC 0x70\n");
+ printf ("#define CLASS_CTRL 0x80\n");
+ printf ("#define CLASS_IGNORE 0x90\n");
+ printf ("#define CLASS_ADDRESS 0xd0\n");
+ printf ("#define CLASS_0CCC 0xe0\n");
+ printf ("#define CLASS_1CCC 0xf0\n");
+ printf ("#define CLASS_0DISP7 0x100\n");
+ printf ("#define CLASS_1DISP7 0x200\n");
+ printf ("#define CLASS_01II 0x300\n");
+ printf ("#define CLASS_00II 0x400\n");
+ printf ("#define CLASS_BIT 0x500\n");
+ printf ("#define CLASS_FLAGS 0x600\n");
+ printf ("#define CLASS_IR 0x700\n");
printf ("#define CLASS_IRO 0x800\n");
printf ("#define CLASS_DISP8 0x900\n");
printf ("#define CLASS_BIT_1OR2 0xa00\n");
- printf ("#define CLASS_REG 0x7000\n");
- printf ("#define CLASS_REG_BYTE 0x2000\n");
- printf ("#define CLASS_REG_WORD 0x3000\n");
- printf ("#define CLASS_REG_QUAD 0x4000\n");
- printf ("#define CLASS_REG_LONG 0x5000\n");
- printf ("#define CLASS_REGN0 0x8000\n");
- printf ("#define CLASS_PR 0x10000\n");
+ printf ("#define CLASS_REG 0x7000\n");
+ printf ("#define CLASS_REG_BYTE 0x2000\n");
+ printf ("#define CLASS_REG_WORD 0x3000\n");
+ printf ("#define CLASS_REG_QUAD 0x4000\n");
+ printf ("#define CLASS_REG_LONG 0x5000\n");
+ printf ("#define CLASS_REGN0 0x8000\n");
+ printf ("#define CLASS_PR 0x10000\n");
printf ("#define CLASS_MASK 0x1fff0\n");
- printf ("#define OPC_adc 0\n");
- printf ("#define OPC_adcb 1\n");
- printf ("#define OPC_add 2\n");
- printf ("#define OPC_addb 3\n");
- printf ("#define OPC_addl 4\n");
- printf ("#define OPC_and 5\n");
- printf ("#define OPC_andb 6\n");
- printf ("#define OPC_bit 7\n");
- printf ("#define OPC_bitb 8\n");
- printf ("#define OPC_call 9\n");
- printf ("#define OPC_calr 10\n");
- printf ("#define OPC_clr 11\n");
- printf ("#define OPC_clrb 12\n");
- printf ("#define OPC_com 13\n");
- printf ("#define OPC_comb 14\n");
- printf ("#define OPC_comflg 15\n");
- printf ("#define OPC_cp 16\n");
- printf ("#define OPC_cpb 17\n");
- printf ("#define OPC_cpd 18\n");
- printf ("#define OPC_cpdb 19\n");
- printf ("#define OPC_cpdr 20\n");
- printf ("#define OPC_cpdrb 21\n");
- printf ("#define OPC_cpi 22\n");
- printf ("#define OPC_cpib 23\n");
- printf ("#define OPC_cpir 24\n");
- printf ("#define OPC_cpirb 25\n");
- printf ("#define OPC_cpl 26\n");
- printf ("#define OPC_cpsd 27\n");
- printf ("#define OPC_cpsdb 28\n");
- printf ("#define OPC_cpsdr 29\n");
- printf ("#define OPC_cpsdrb 30\n");
- printf ("#define OPC_cpsi 31\n");
- printf ("#define OPC_cpsib 32\n");
- printf ("#define OPC_cpsir 33\n");
- printf ("#define OPC_cpsirb 34\n");
- printf ("#define OPC_dab 35\n");
- printf ("#define OPC_dbjnz 36\n");
- printf ("#define OPC_dec 37\n");
- printf ("#define OPC_decb 38\n");
- printf ("#define OPC_di 39\n");
- printf ("#define OPC_div 40\n");
- printf ("#define OPC_divl 41\n");
- printf ("#define OPC_djnz 42\n");
- printf ("#define OPC_ei 43\n");
- printf ("#define OPC_ex 44\n");
- printf ("#define OPC_exb 45\n");
- printf ("#define OPC_exts 46\n");
- printf ("#define OPC_extsb 47\n");
- printf ("#define OPC_extsl 48\n");
- printf ("#define OPC_halt 49\n");
- printf ("#define OPC_in 50\n");
- printf ("#define OPC_inb 51\n");
- printf ("#define OPC_inc 52\n");
- printf ("#define OPC_incb 53\n");
- printf ("#define OPC_ind 54\n");
- printf ("#define OPC_indb 55\n");
+ printf ("#define OPC_adc 0\n");
+ printf ("#define OPC_adcb 1\n");
+ printf ("#define OPC_add 2\n");
+ printf ("#define OPC_addb 3\n");
+ printf ("#define OPC_addl 4\n");
+ printf ("#define OPC_and 5\n");
+ printf ("#define OPC_andb 6\n");
+ printf ("#define OPC_bit 7\n");
+ printf ("#define OPC_bitb 8\n");
+ printf ("#define OPC_call 9\n");
+ printf ("#define OPC_calr 10\n");
+ printf ("#define OPC_clr 11\n");
+ printf ("#define OPC_clrb 12\n");
+ printf ("#define OPC_com 13\n");
+ printf ("#define OPC_comb 14\n");
+ printf ("#define OPC_comflg 15\n");
+ printf ("#define OPC_cp 16\n");
+ printf ("#define OPC_cpb 17\n");
+ printf ("#define OPC_cpd 18\n");
+ printf ("#define OPC_cpdb 19\n");
+ printf ("#define OPC_cpdr 20\n");
+ printf ("#define OPC_cpdrb 21\n");
+ printf ("#define OPC_cpi 22\n");
+ printf ("#define OPC_cpib 23\n");
+ printf ("#define OPC_cpir 24\n");
+ printf ("#define OPC_cpirb 25\n");
+ printf ("#define OPC_cpl 26\n");
+ printf ("#define OPC_cpsd 27\n");
+ printf ("#define OPC_cpsdb 28\n");
+ printf ("#define OPC_cpsdr 29\n");
+ printf ("#define OPC_cpsdrb 30\n");
+ printf ("#define OPC_cpsi 31\n");
+ printf ("#define OPC_cpsib 32\n");
+ printf ("#define OPC_cpsir 33\n");
+ printf ("#define OPC_cpsirb 34\n");
+ printf ("#define OPC_dab 35\n");
+ printf ("#define OPC_dbjnz 36\n");
+ printf ("#define OPC_dec 37\n");
+ printf ("#define OPC_decb 38\n");
+ printf ("#define OPC_di 39\n");
+ printf ("#define OPC_div 40\n");
+ printf ("#define OPC_divl 41\n");
+ printf ("#define OPC_djnz 42\n");
+ printf ("#define OPC_ei 43\n");
+ printf ("#define OPC_ex 44\n");
+ printf ("#define OPC_exb 45\n");
+ printf ("#define OPC_exts 46\n");
+ printf ("#define OPC_extsb 47\n");
+ printf ("#define OPC_extsl 48\n");
+ printf ("#define OPC_halt 49\n");
+ printf ("#define OPC_in 50\n");
+ printf ("#define OPC_inb 51\n");
+ printf ("#define OPC_inc 52\n");
+ printf ("#define OPC_incb 53\n");
+ printf ("#define OPC_ind 54\n");
+ printf ("#define OPC_indb 55\n");
printf ("#define OPC_indr 56\n");
printf ("#define OPC_indrb 57\n");
printf ("#define OPC_ini 58\n");
@@ -1322,9 +1310,7 @@ gas ()
}
int
-main (ac, av)
- int ac;
- char **av;
+main (int ac, char **av)
{
struct op *p = opt;
generated by cgit v1.1 at 2024-11-24 21:55:48 +0000