diff options
Diffstat (limited to 'opcodes/v850-opc.c')
| -rw-r--r-- | opcodes/v850-opc.c | 134 |
1 files changed, 70 insertions, 64 deletions
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index 94969ac..2249d16 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -1,37 +1,37 @@ /* Assemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include "opcode/v850.h" #include <stdio.h> #include "opintl.h" -/* regular opcode */ +/* Regular opcodes. */ #define OP(x) ((x & 0x3f) << 5) #define OP_MASK OP (0x3f) -/* conditional branch opcode */ +/* Conditional branch opcodes. */ #define BOP(x) ((0x0b << 7) | (x & 0x0f)) #define BOP_MASK ((0x0f << 7) | 0x0f) -/* one-word opcodes */ +/* One-word opcodes. */ #define one(x) ((unsigned int) (x)) -/* two-word opcodes */ +/* Two-word opcodes. */ #define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); @@ -402,15 +402,15 @@ const struct v850_operand v850_operands[] = #define UNUSED 0 { 0, 0, NULL, NULL, 0 }, -/* The R1 field in a format 1, 6, 7, or 9 insn. */ +/* The R1 field in a format 1, 6, 7, or 9 insn. */ #define R1 (UNUSED + 1) { 5, 0, NULL, NULL, V850_OPERAND_REG }, /* As above, but register 0 is not allowed. */ #define R1_NOTR0 (R1 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, + { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ +/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ #define R2 (R1_NOTR0 + 1) { 5, 11, NULL, NULL, V850_OPERAND_REG }, @@ -418,23 +418,23 @@ const struct v850_operand v850_operands[] = #define R2_NOTR0 (R2 + 1) { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* The imm5 field in a format 2 insn. */ +/* The imm5 field in a format 2 insn. */ #define I5 (R2_NOTR0 + 1) { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, -/* The unsigned imm5 field in a format 2 insn. */ +/* The unsigned imm5 field in a format 2 insn. */ #define I5U (I5 + 1) { 5, 0, NULL, NULL, 0 }, -/* The imm16 field in a format 6 insn. */ +/* The imm16 field in a format 6 insn. */ #define I16 (I5U + 1) { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, -/* The signed disp7 field in a format 4 insn. */ +/* The signed disp7 field in a format 4 insn. */ #define D7 (I16 + 1) { 7, 0, NULL, NULL, 0}, -/* The disp16 field in a format 6 insn. */ +/* The disp16 field in a format 6 insn. */ #define D16_15 (D7 + 1) { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, @@ -446,11 +446,11 @@ const struct v850_operand v850_operands[] = #define CCCC (B3 + 1) { 4, 0, NULL, NULL, V850_OPERAND_CC }, -/* The unsigned DISP8 field in a format 4 insn. */ +/* The unsigned DISP8 field in a format 4 insn. */ #define D8_7 (CCCC + 1) { 7, 0, insert_d8_7, extract_d8_7, 0 }, -/* The unsigned DISP8 field in a format 4 insn. */ +/* The unsigned DISP8 field in a format 4 insn. */ #define D8_6 (D8_7 + 1) { 6, 1, insert_d8_6, extract_d8_6, 0 }, @@ -462,7 +462,7 @@ const struct v850_operand v850_operands[] = #define EP (SR1 + 1) { 0, 0, NULL, NULL, V850_OPERAND_EP }, -/* The imm16 field (unsigned) in a format 6 insn. */ +/* The imm16 field (unsigned) in a format 6 insn. */ #define I16U (EP + 1) { 16, 16, NULL, NULL, 0}, @@ -470,11 +470,11 @@ const struct v850_operand v850_operands[] = #define SR2 (I16U + 1) { 5, 11, NULL, NULL, V850_OPERAND_SRG }, -/* The disp16 field in a format 8 insn. */ +/* The disp16 field in a format 8 insn. */ #define D16 (SR2 + 1) { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, -/* The DISP9 field in a format 3 insn, relaxable. */ +/* The DISP9 field in a format 3 insn, relaxable. */ #define D9_RELAX (D16 + 1) { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, @@ -484,19 +484,19 @@ const struct v850_operand v850_operands[] = #define D22 (D9_RELAX + 1) { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, -/* The signed disp4 field in a format 4 insn. */ +/* The signed disp4 field in a format 4 insn. */ #define D4 (D22 + 1) { 4, 0, NULL, NULL, 0}, -/* The unsigned disp5 field in a format 4 insn. */ +/* The unsigned disp5 field in a format 4 insn. */ #define D5_4 (D4 + 1) { 4, 0, insert_d5_4, extract_d5_4, 0 }, -/* The disp16 field in an format 7 unsigned byte load insn. */ +/* The disp16 field in an format 7 unsigned byte load insn. */ #define D16_16 (D5_4 + 1) { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, -/* Third register in conditional moves. */ +/* Third register in conditional moves. */ #define R3 (D16_16 + 1) { 5, 27, NULL, NULL, V850_OPERAND_REG }, @@ -504,11 +504,11 @@ const struct v850_operand v850_operands[] = #define MOVCC (R3 + 1) { 4, 17, NULL, NULL, V850_OPERAND_CC }, -/* The imm9 field in a multiply word. */ +/* The imm9 field in a multiply word. */ #define I9 (MOVCC + 1) { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, -/* The unsigned imm9 field in a multiply word. */ +/* The unsigned imm9 field in a multiply word. */ #define U9 (I9 + 1) { 9, 0, insert_u9, extract_u9, 0 }, @@ -516,7 +516,7 @@ const struct v850_operand v850_operands[] = #define LIST12 (U9 + 1) { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, -/* The IMM6 field in a call instruction. */ +/* The IMM6 field in a call instruction. */ #define I6 (LIST12 + 1) { 6, 0, NULL, NULL, 0 }, @@ -528,19 +528,19 @@ const struct v850_operand v850_operands[] = #define IMM32 (IMM16 + 1) { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, -/* The imm5 field in a push/pop instruction. */ +/* The imm5 field in a push/pop instruction. */ #define IMM5 (IMM32 + 1) { 5, 1, NULL, NULL, 0 }, -/* Reg2 in dispose instruction. */ +/* Reg2 in dispose instruction. */ #define R2DISPOSE (IMM5 + 1) { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, -/* Stack pointer in prepare instruction. */ +/* Stack pointer in prepare instruction. */ #define SP (R2DISPOSE + 1) { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, -/* The IMM5 field in a divide N step instruction. */ +/* The IMM5 field in a divide N step instruction. */ #define I5DIV (SP + 1) { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, @@ -550,23 +550,24 @@ const struct v850_operand v850_operands[] = /* The list of registers in a PUSHML/POPML instruction. */ #define LIST18_L (LIST18_H + 1) - { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ + /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */ + { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, } ; -/* reg-reg instruction format (Format I) */ +/* Reg - Reg instruction format (Format I). */ #define IF1 {R1, R2} -/* imm-reg instruction format (Format II) */ +/* Imm - Reg instruction format (Format II). */ #define IF2 {I5, R2} -/* conditional branch instruction format (Format III) */ +/* Conditional branch instruction format (Format III). */ #define IF3 {D9_RELAX} -/* 3 operand instruction (Format VI) */ +/* 3 operand instruction (Format VI). */ #define IF6 {I16, R1, R2} -/* 3 operand instruction (Format VI) */ +/* 3 operand instruction (Format VI). */ #define IF6U {I16U, R1, R2} @@ -604,17 +605,22 @@ const struct v850_operand v850_operands[] = const struct v850_opcode v850_opcodes[] = { { "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, +{ "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, -/* load/store instructions */ +/* Load/store instructions. */ +{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, +{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, +{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 }, { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, +{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 }, { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, @@ -639,7 +645,7 @@ const struct v850_opcode v850_opcodes[] = { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -/* byte swap/extend instructions */ +/* Byte swap/extend instructions. */ { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, { "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, @@ -648,12 +654,12 @@ const struct v850_opcode v850_opcodes[] = { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -/* jump table instructions */ +/* Jump table instructions. */ { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, -/* arithmetic operation instructions */ +/* Arithmetic operation instructions. */ { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, @@ -686,14 +692,14 @@ const struct v850_opcode v850_opcodes[] = { "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, -/* saturated operation instructions */ +/* Saturated operation instructions. */ { "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -/* logical operation instructions */ +/* Logical operation instructions. */ { "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, { "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, @@ -710,21 +716,21 @@ const struct v850_opcode v850_opcodes[] = { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, -/* branch instructions */ - /* signed integer */ +/* Branch instructions. */ + /* Signed integer. */ { "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ + /* Unsigned integer. */ { "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ + /* Common. */ { "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ + /* Others. */ { "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, @@ -741,20 +747,20 @@ const struct v850_opcode v850_opcodes[] = We use the short form in the opcode/mask fields. The assembler will twiddle bits as necessary if the long form is needed. */ - /* signed integer */ + /* Signed integer. */ { "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ + /* Unsigned integer. */ { "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ + /* Common. */ { "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ + /* Others. */ { "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, { "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, @@ -769,7 +775,7 @@ const struct v850_opcode v850_opcodes[] = { "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, { "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, -/* bit manipulation instructions */ +/* Bit manipulation instructions. */ { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, @@ -779,7 +785,7 @@ const struct v850_opcode v850_opcodes[] = { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* special instructions */ +/* Special instructions. */ { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, { "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, { "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, @@ -787,10 +793,10 @@ const struct v850_opcode v850_opcodes[] = { "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, { "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, { "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, +{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, { 0, 0, 0, {0}, 0, 0 }, } ; const int v850_num_opcodes = sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); - |