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-rw-r--r--opcodes/riscv-dis.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 827d9b6..2826248 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -614,6 +614,20 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
goto undefined_modifier;
}
break;
+ case 'c': /* Zcb extension 16 bits length instruction fields. */
+ switch (*++oparg)
+ {
+ case 'b':
+ print (info->stream, dis_style_immediate, "%d",
+ (int)EXTRACT_ZCB_BYTE_UIMM (l));
+ break;
+ case 'h':
+ print (info->stream, dis_style_immediate, "%d",
+ (int)EXTRACT_ZCB_HALFWORD_UIMM (l));
+ break;
+ default: break;
+ }
+ break;
default:
goto undefined_modifier;
}