diff options
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index d2f7eb1..80dfa24 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -388,6 +388,8 @@ const struct powerpc_operand powerpc_operands[] = /* The L field in a D or X form instruction. */ #define L IMM20 + 1 + /* The R field in a HTM X form instruction. */ +#define HTM_R L { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The LEV field in a POWER SVC form instruction. */ @@ -572,8 +574,12 @@ const struct powerpc_operand powerpc_operands[] = #define EVUIMM SH { 0x1f, 11, NULL, NULL, 0 }, + /* The SI field in a HTM X form instruction. */ +#define HTM_SI SH + 1 + { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, + /* The SH field in an MD form instruction. This is split. */ -#define SH6 SH + 1 +#define SH6 HTM_SI + 1 #define SH6_MASK ((0x1f << 11) | (1 << 1)) { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, @@ -757,7 +763,9 @@ const struct powerpc_operand powerpc_operands[] = { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, /* The L field in an mtfsf or XFL form instruction. */ + /* The A field in a HTM X form instruction. */ #define XFL_L EH + 1 +#define HTM_A XFL_L { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, /* Xilinx APU related masks and macros */ @@ -2427,15 +2435,33 @@ extract_vleil (unsigned long insn, /* An X_MASK with the RT and RA fields fixed. */ #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) +/* An X_MASK with the RT and RB fields fixed. */ +#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) + /* An XRTRA_MASK, but with L bit clear. */ #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) +/* An X_MASK with the RT, RA and RB fields fixed. */ +#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) + +/* An XRTRARB_MASK, but with L bit clear. */ +#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) + +/* An XRTRARB_MASK, but with A bit clear. */ +#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) + +/* An XRTRARB_MASK, but with BF bits clear. */ +#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) + /* An X form instruction with the L bit specified. */ #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) /* An X form instruction with the L bits specified. */ #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) +/* An X form instruction with the L bit and RC bit specified. */ +#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) + /* An X form instruction with RT fields specified */ #define XRT(op, xop, rt) (X ((op), (xop)) \ | ((((unsigned long)(rt)) & 0x1f) << 21)) @@ -2659,6 +2685,7 @@ extract_vleil (unsigned long insn, #define POWER5 PPC_OPCODE_POWER5 #define POWER6 PPC_OPCODE_POWER6 #define POWER7 PPC_OPCODE_POWER7 +#define POWER8 PPC_OPCODE_POWER8 #define CELL PPC_OPCODE_CELL #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ @@ -2702,6 +2729,7 @@ extract_vleil (unsigned long insn, #define E500 PPC_OPCODE_E500 #define E6500 PPC_OPCODE_E6500 #define PPCVLE PPC_OPCODE_VLE +#define PPCHTM PPC_OPCODE_HTM /* The opcode table. @@ -5315,6 +5343,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvlx", X(31,647), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"stbfcmux", APU(31,647,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, +{"tbegin.", XRC(31,654,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {HTM_R}}, + {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -5350,6 +5380,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvrx", X(31,679), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"sthfcmux", APU(31,679,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, +{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE, {0}}, +{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, PPCNONE, {HTM_A}}, + {"stbcx.", XRC(31,694,1), X_MASK, POWER7, PPCNONE, {RS, RA0, RB}}, {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, @@ -5365,6 +5398,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, +{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, PPCNONE, {BF}}, + {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, PPCNONE, {RT, RA}}, {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA}}, @@ -5415,6 +5450,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, +{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, +{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {L}}, + {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}}, {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}}, @@ -5438,6 +5477,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, +{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, + {"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}}, {"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, @@ -5461,6 +5502,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, + {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, {"erativax", X(31,819), X_MASK, PPCA2, PPCNONE, {RS, RA0, RB}}, @@ -5486,6 +5529,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, +{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, + {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, {"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, @@ -5507,6 +5552,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, + {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}}, @@ -5521,6 +5568,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, +{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, + {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, @@ -5559,6 +5608,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, + {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, {"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}}, @@ -5618,6 +5669,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, |