diff options
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index a2112a7..5e73880 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3313,6 +3313,9 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) /* A VX_MASK with the VA field fixed with a PS field. */ #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) +/* A VX_MASK for instructions using a BF field. */ +#define VXBF_MASK (VX_MASK | (3 << 21)) + /* A VA form instruction. */ #define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) @@ -3910,10 +3913,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, @@ -3939,6 +3944,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, +{"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}}, {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, @@ -3985,6 +3991,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -4024,6 +4031,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4031,11 +4039,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, @@ -4045,8 +4056,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {OBF, VA, VB}}, {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, @@ -4074,6 +4087,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, +{"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, {"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}}, @@ -4090,6 +4105,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, @@ -4098,6 +4114,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, +{"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, @@ -4163,6 +4180,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, {"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4226,6 +4244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, {"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, @@ -4303,6 +4322,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4310,6 +4330,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, +{"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, @@ -4366,6 +4387,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, @@ -4379,6 +4401,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, +{"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, @@ -4612,6 +4635,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, +{"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, {"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, @@ -4647,6 +4671,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, +{"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}}, {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, @@ -4656,6 +4681,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, @@ -4670,6 +4696,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, +{"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}}, @@ -4691,6 +4718,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, +{"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}}, {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, @@ -4711,6 +4739,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, +{"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, {"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}}, @@ -8012,10 +8041,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, {"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, +{"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, {"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, +{"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, +{"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, {"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, +{"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, {"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, {"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, @@ -8044,6 +8077,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, {"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, + +{"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}}, +{"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}}, }; const unsigned int powerpc_num_opcodes = |