diff options
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 726 |
1 files changed, 621 insertions, 105 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index e9d24c8..0ea8d95 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -54,8 +54,18 @@ static long extract_bo (unsigned long, ppc_cpu_t, int *); static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); static long extract_boe (unsigned long, ppc_cpu_t, int *); static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **); +static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **); +static long extract_dcmxs (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **); +static long extract_dxd (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **); +static long extract_dxdn (unsigned long, ppc_cpu_t, int *); static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); static long extract_fxm (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_l0 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_l1 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); static long extract_li20 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); @@ -98,6 +108,8 @@ static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); static long extract_tbr (unsigned long, ppc_cpu_t, int *); static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); static long extract_xt6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xtq6 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); static long extract_xa6 (unsigned long, ppc_cpu_t, int *); static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); @@ -302,9 +314,17 @@ const struct powerpc_operand powerpc_operands[] = #define D8 D + 1 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DCMX field in an X form instruction. */ +#define DCMX D8 + 1 + { 0x7f, 16, NULL, NULL, 0 }, + + /* The split DCMX field in an X form instruction. */ +#define DCMXS DCMX + 1 + { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, + /* The DQ field in a DQ form instruction. This is like D, but the lower four bits are forced to zero. */ -#define DQ D8 + 1 +#define DQ DCMXS + 1 { 0xfff0, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, @@ -320,10 +340,21 @@ const struct powerpc_operand powerpc_operands[] = #define BHRBE DUIS { 0x3ff, 11, NULL, NULL, 0 }, + /* The split D field in a DX form instruction. */ +#define DXD DUIS + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, + PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, + + /* The split ND field in a DX form instruction. + This is the same as the DX field, only negated. */ +#define NDXD DXD + 1 + { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, + PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, + /* The E field in a wrteei instruction. */ /* And the W bit in the pair singles instructions. */ /* And the ST field in a VX form instruction. */ -#define E DUIS + 1 +#define E NDXD + 1 #define PSW E #define ST E { 0x1, 15, NULL, NULL, 0 }, @@ -397,8 +428,16 @@ const struct powerpc_operand powerpc_operands[] = #define HTM_R L { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + /* The L field in an X form instruction which must be zero. */ +#define L0 L + 1 + { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL }, + + /* The L field in an X form instruction which must be one. */ +#define L1 L0 + 1 + { 0x1, 21, insert_l1, extract_l1, 0 }, + /* The LEV field in a POWER SVC form instruction. */ -#define SVC_LEV L + 1 +#define SVC_LEV L1 + 1 { 0x7f, 5, NULL, NULL, 0 }, /* The LEV field in an SC form instruction. */ @@ -513,10 +552,14 @@ const struct powerpc_operand powerpc_operands[] = #define RBOPT RBX + 1 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + /* The RC register field in an maddld, maddhd or maddhdu instruction. */ +#define RC RBOPT + 1 + { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, + /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form instruction or the RT field in a D, DS, X, XFX or XO form instruction. */ -#define RS RBOPT + 1 +#define RS RC + 1 #define RT RS #define RT_MASK (0x1f << 21) #define RD RS @@ -577,6 +620,8 @@ const struct powerpc_operand powerpc_operands[] = #define SH_MASK (0x1f << 11) /* The other UIMM field in a EVX form instruction. */ #define EVUIMM SH + /* The FC field in an atomic X form instruction. */ +#define FC SH { 0x1f, 11, NULL, NULL, 0 }, /* The SI field in a HTM X form instruction. */ @@ -705,8 +750,12 @@ const struct powerpc_operand powerpc_operands[] = #define UIMM3 UIMM + 1 { 0x7, 16, NULL, NULL, 0 }, + /* The 6-bit UIM field in a X form instruction. */ +#define UIM6 UIMM3 + 1 + { 0x3f, 16, NULL, NULL, 0 }, + /* The SIX field in a VX form instruction. */ -#define SIX UIMM3 + 1 +#define SIX UIM6 + 1 { 0xf, 11, NULL, NULL, 0 }, /* The PS field in a VX form instruction. */ @@ -752,9 +801,10 @@ const struct powerpc_operand powerpc_operands[] = #define PSD PSQM + 1 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, - /* The L field in an mtmsrd or A form instruction or W in an X form. */ + /* The L field in an mtmsrd or A form instruction or R or W in an X form. */ #define A_L PSD + 1 #define W A_L +#define X_R A_L { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, #define RMC A_L + 1 @@ -763,7 +813,13 @@ const struct powerpc_operand powerpc_operands[] = #define R RMC + 1 { 0x1, 16, NULL, NULL, 0 }, -#define SP R + 1 +#define RIC R + 1 + { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, + +#define PRS RIC + 1 + { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, + +#define SP PRS + 1 { 0x3, 19, NULL, NULL, 0 }, #define S SP + 1 @@ -838,8 +894,13 @@ const struct powerpc_operand powerpc_operands[] = #define XT6 XS6 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, + /* The XT and XS fields in an DQ form VSX instruction. This is split. */ +#define XSQ6 XT6 + 1 +#define XTQ6 XSQ6 + { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, + /* The XA field in an XX3 form instruction. This is split. */ -#define XA6 XT6 + 1 +#define XA6 XTQ6 + 1 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, /* The XB field in an XX2 or XX3 form instruction. This is split. */ @@ -869,6 +930,8 @@ const struct powerpc_operand powerpc_operands[] = #define UIM DMEX + 1 /* The 2-bit UIMM field in a VX form instruction. */ #define UIMM2 UIM + /* The 2-bit L field in a darn instruction. */ +#define LRAND UIM { 0x3, 16, NULL, NULL, 0 }, #define ERAT_T UIM + 1 @@ -876,6 +939,10 @@ const struct powerpc_operand powerpc_operands[] = #define IH ERAT_T + 1 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, + + /* The 8-bit IMM8 field in a XX1 form instruction. */ +#define IMM8 IH + 1 + { 0xff, 11, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -1272,6 +1339,64 @@ extract_boe (unsigned long insn, return value & 0x1e; } +/* The DCMX field in a X form instruction when the field is split + into separate DC, DM and DX fields. */ + +static unsigned long +insert_dcmxs (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40); +} + +static long +extract_dcmxs (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); +} + +/* The D field in a DX form instruction when the field is split + into separate D0, D1 and D2 fields. */ + +static unsigned long +insert_dxd (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (value & 0xffc1) | ((value & 0x3e) << 15); +} + +static long +extract_dxd (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); + return (dxd ^ 0x8000) - 0x8000; +} + +static unsigned long +insert_dxdn (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insert_dxd (insn, -value, dialect, errmsg); +} + +static long +extract_dxdn (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return -extract_dxd (insn, dialect, invalid); +} + /* FXM mask in mfcr and mtcrf instructions. */ static unsigned long @@ -1343,6 +1468,58 @@ extract_fxm (unsigned long insn, return mask; } +/* The L field in an X form instruction which must have the value zero. */ + +static unsigned long +insert_l0 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value != 0) + *errmsg = _("invalid operand constant"); + return insn & ~(0x1 << 21); +} + +static long +extract_l0 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value; + + value = (insn >> 21) & 0x1; + if (value != 0) + *invalid = 1; + return value; +} + +/* The L field in an X form instruction which must have the value one. */ + +static unsigned long +insert_l1 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if (value != 1) + *errmsg = _("invalid operand constant"); + return insn | (0x1 << 21); +} + +static long +extract_l1 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + long value; + + value = (insn >> 21) & 0x1; + if (value != 1) + *invalid = 1; + return value; +} + static unsigned long insert_li20 (unsigned long insn, long value, @@ -1398,16 +1575,16 @@ insert_ls (unsigned long insn, static unsigned long insert_esync (unsigned long insn, long value, - ppc_cpu_t dialect ATTRIBUTE_UNUSED, + ppc_cpu_t dialect, const char **errmsg) { - unsigned long ls; + unsigned long ls = (insn >> 21) & 0x03; - ls = (insn >> 21) & 0x03; if (value == 0) { - if (ls > 1) - *errmsg = _("illegal L operand value"); + if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) + || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) + *errmsg = _("illegal L operand value"); return insn; } @@ -1945,6 +2122,24 @@ extract_xt6 (unsigned long insn, return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); } +/* The XT and XS fields in an DQ form VSX instruction. This is split. */ +static unsigned long +insert_xtq6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); +} + +static long +extract_xtq6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); +} + /* The XA field in an XX3 form instruction. This is split. */ static unsigned long @@ -2258,10 +2453,18 @@ extract_vleil (unsigned long insn, /* The main opcode mask with the RA field clear. */ #define DRA_MASK (OP_MASK | RA_MASK) +/* A DQ form VSX instruction. */ +#define DQX(op, xop) (OP (op) | ((xop) & 0x7)) +#define DQX_MASK DQX (0x3f, 7) + /* A DS form instruction. */ #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) #define DS_MASK DSO (0x3f, 3) +/* An DX form instruction. */ +#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) +#define DX_MASK DX (0x3f, 0x1f) + /* An EVSEL form instruction. */ #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) #define EVSEL_MASK EVSEL(0x3f, 0xff) @@ -2374,6 +2577,9 @@ extract_vleil (unsigned long insn, /* A VX_MASK with a PS field. */ #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) +/* A VX_MASK with the VA field fixed with a PS field. */ +#define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) + /* A VA form instruction. */ #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) @@ -2389,9 +2595,15 @@ extract_vleil (unsigned long insn, /* The mask for a VXR form instruction. */ #define VXR_MASK VXR(0x3f, 0x3ff, 1) +/* A VX form instruction with a VA tertiary opcode. */ +#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) + /* An X form instruction. */ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) +/* A X form instruction for Quad-Precision FP Instructions. */ +#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) + /* An EX form instruction. */ #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) @@ -2401,6 +2613,9 @@ extract_vleil (unsigned long insn, /* An XX2 form instruction. */ #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) +/* A XX2 form instruction with the VA bits specified. */ +#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) + /* An XX3 form instruction. */ #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) @@ -2416,12 +2631,18 @@ extract_vleil (unsigned long insn, /* An X form instruction with the RC bit specified. */ #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) +/* A X form instruction for Quad-Precision FP Instructions with RC bit. */ +#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) + /* A Z form instruction with the RC bit specified. */ #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) /* The mask for an X form instruction. */ #define X_MASK XRC (0x3f, 0x3ff, 1) +/* The mask for an X form instruction with the BF bits specified. */ +#define XBF_MASK (X_MASK | (3 << 21)) + /* An X form wait instruction with everything filled in except the WC field. */ #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) @@ -2437,9 +2658,18 @@ extract_vleil (unsigned long insn, /* The mask for an XX2 form instruction with the UIM bits specified. */ #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) +/* The mask for an XX2 form instruction with the 4 UIM bits specified. */ +#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) + /* The mask for an XX2 form instruction with the BF bits specified. */ #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) +/* The mask for an XX2 form instruction with the BF and DCMX bits specified. */ +#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) + +/* The mask for an XX2 form instruction with a split DCMX bits specified. */ +#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) + /* The mask for an XX3 form instruction. */ #define XX3_MASK XX3 (0x3f, 0xff) @@ -2460,11 +2690,13 @@ extract_vleil (unsigned long insn, #define Z_MASK ZRC (0x3f, 0x1ff, 1) #define Z2_MASK ZRC (0x3f, 0xff, 1) -/* An X_MASK with the RA field fixed. */ +/* An X_MASK with the RA/VA field fixed. */ #define XRA_MASK (X_MASK | RA_MASK) +#define XVA_MASK XRA_MASK -/* An XRA_MASK with the W field clear. */ +/* An XRA_MASK with the A_L/W field clear. */ #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) +#define XRLA_MASK XWRA_MASK /* An X_MASK with the RB field fixed. */ #define XRB_MASK (X_MASK | RB_MASK) @@ -2478,9 +2710,15 @@ extract_vleil (unsigned long insn, /* An X_MASK with the RA and RB fields fixed. */ #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) +/* An XBF_MASK with the RA and RB fields fixed. */ +#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) + /* An XRARB_MASK, but with the L bit clear. */ #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) +/* An XRARB_MASK, but with the L bits in a darn instruction clear. */ +#define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16)) + /* An X_MASK with the RT and RA fields fixed. */ #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) @@ -2738,6 +2976,7 @@ extract_vleil (unsigned long insn, #define POWER6 PPC_OPCODE_POWER6 #define POWER7 PPC_OPCODE_POWER7 #define POWER8 PPC_OPCODE_POWER8 +#define POWER9 PPC_OPCODE_POWER9 #define CELL PPC_OPCODE_CELL #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE #define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ @@ -2753,8 +2992,10 @@ extract_vleil (unsigned long insn, #define PPCPS PPC_OPCODE_PPCPS #define PPCVEC PPC_OPCODE_ALTIVEC #define PPCVEC2 PPC_OPCODE_ALTIVEC2 +#define PPCVEC3 PPC_OPCODE_ALTIVEC2 #define PPCVSX PPC_OPCODE_VSX #define PPCVSX2 PPC_OPCODE_VSX +#define PPCVSX3 PPC_OPCODE_VSX3 #define POWER PPC_OPCODE_POWER #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON @@ -2864,11 +3105,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"twi", OP(3), OP_MASK, PPCCOM, PPCNONE, {TO, RA, SI}}, {"ti", OP(3), OP_MASK, PWRCOM, PPCNONE, {TO, RA, SI}}, -{"ps_cmpu0", X (4, 0), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}}, {"vaddubm", VX (4, 0), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}}, {"vmaxub", VX (4, 2), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrlb", VX (4, 4), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmuloub", VX (4, 8), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vaddfp", VX (4, 10), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, @@ -2914,6 +3157,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VC, VB}}, +{"maddhd", VXA(4, 48), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}}, +{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}}, +{"maddld", VXA(4, 51), VXA_MASK, POWER9, PPCNONE, {RT, RA, RB, RC}}, {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC}}, @@ -2928,15 +3174,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"ps_cmpo0", X (4, 32), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}}, {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, PPCNONE, {VD, VA, VB, VC}}, {"vadduhm", VX (4, 64), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrlh", VX (4, 68), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmulouh", VX (4, 72), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vsubfp", VX (4, 74), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, PPCNONE, {FRT,RA,RB,PSWM,PSQM}}, @@ -2951,11 +3200,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"machhw.", XO (4, 44,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"nmachhw", XO (4, 46,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"nmachhw.", XO (4, 46,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, -{"ps_cmpu1", X (4, 64), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}}, {"vadduwm", VX (4, 128), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrlw", VX (4, 132), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmrghw", VX (4, 140), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -2964,10 +3215,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, PPCNONE, {FRT, FRB}}, {"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, -{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}}, +{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, PPCNONE, {BF, FRA, FRB}}, {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vrld", VX (4, 196), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, +{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -2977,6 +3229,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, @@ -2991,6 +3244,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"vmrglh", VX (4, 332), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3004,6 +3258,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vslw", VX (4, 388), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, +{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"vmrglw", VX (4, 396), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3012,6 +3268,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"macchwsu.", XO (4, 204,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vsl", VX (4, 452), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"vpkswss", VX (4, 462), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3021,6 +3278,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmacchws.", XO (4, 238,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, PPCNONE, {VD, VA}}, {"evaddiw", VX (4, 514), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RB, UIMM}}, {"vminub", VX (4, 514), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evsubfw", VX (4, 516), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, @@ -3037,6 +3295,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evextsh", VX (4, 523), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"evrndw", VX (4, 524), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"vspltb", VX (4, 524), VXUIMM4_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM4}}, +{"vextractub", VX (4, 525), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, @@ -3075,12 +3334,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, {"vadduhs", VX (4, 576), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vminuh", VX (4, 578), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vsrh", VX (4, 580), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"vsplth", VX (4, 588), VXUIMM3_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM3}}, +{"vextractuh", VX (4, 589), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, PPCNONE, {RT, FSL}}, {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB, CRFS}}, @@ -3100,6 +3361,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"vspltw", VX (4, 652), VXUIMM2_MASK,PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM2}}, +{"vextractuw", VX (4, 653), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, @@ -3131,6 +3393,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"efsdiv", VX (4, 713), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, +{"vextractd", VX (4, 717), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"efscmplt", VX (4, 717), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS|PPCVLE, PPCNONE, {CRFD, RA, RB}}, {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, @@ -3195,6 +3458,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"vinsertb", VX (4, 781), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_2, RA}}, {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vpkpx", VX (4, 782), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3228,6 +3492,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evstwwox", VX (4, 828), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evstwwo", VX (4, 829), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, EVUIMM_4, RA}}, {"vaddshs", VX (4, 832), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vminsh", VX (4, 834), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vsrah", VX (4, 836), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3235,6 +3500,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcfsx", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"vinserth", VX (4, 845), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"mullhw", XRC(4, 424,0), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"mullhw.", XRC(4, 424,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3250,6 +3516,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vctuxs", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, SIMM}}, +{"vinsertw", VX (4, 909), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"maclhwsu", XO (4, 460,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhwsu.", XO (4, 460,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, @@ -3258,6 +3525,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vctsxs", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB, UIMM}}, +{"vinsertd", VX (4, 973), VXUIMM4_MASK,PPCVEC3, PPCNONE, {VD, VB, UIMM4}}, {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VB}}, {"maclhws", XO (4, 492,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhws.", XO (4, 492,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3270,6 +3538,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"evmhossf", VX (4,1031), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, @@ -3302,6 +3571,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, @@ -3331,10 +3601,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vmr", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VBA}}, {"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, @@ -3345,6 +3617,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, +{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}}, {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA}}, @@ -3370,6 +3643,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}}, {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}}, {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vavgsb", VX (4,1282), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, @@ -3379,6 +3653,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, @@ -3399,11 +3674,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vavgsh", VX (4,1346), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vorc", VX (4,1348), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, @@ -3421,6 +3698,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}}, +{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}}, +{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}}, +{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}}, +{"bcdsetsgn.", VXVA(4,1409,31),VXVAPS_MASK, PPCVEC3, PPCNONE, {VD, VB, PS}}, {"vavgsw", VX (4,1410), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vnand", VX (4,1412), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, @@ -3428,6 +3712,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}}, +{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, @@ -3444,6 +3729,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, PS}}, {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"vsld", VX (4,1476), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3452,6 +3738,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, PPCNONE, {VD, VA}}, {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, +{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}}, {"macchwso", XO (4, 236,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3462,17 +3749,35 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"nmacchwso", XO (4, 238,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"nmacchwso.", XO (4, 238,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vsububs", VX (4,1536), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}}, +{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, PPCNONE, {RT, VB}}, +{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vprtybq", VXVA(4,1538,10),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vextsb2w", VXVA(4,1538,16),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vextsh2w", VXVA(4,1538,17),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vextsb2d", VXVA(4,1538,24),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vextsh2d", VXVA(4,1538,25),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vextsw2d", VXVA(4,1538,26),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vctzb", VXVA(4,1538,28),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vctzh", VXVA(4,1538,29),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vctzw", VXVA(4,1538,30),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, +{"vctzd", VXVA(4,1538,31),VXVA_MASK, PPCVEC3, PPCNONE, {VD, VB}}, {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC|PPCVLE, PPCNONE, {VD}}, {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC|PPCVLE, PPCNONE, {VB}}, {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, +{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, {"vsubuws", VX (4,1664), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}}, @@ -3482,6 +3787,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, +{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, ST, SIX}}, {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, @@ -3492,16 +3798,20 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, +{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"maclhwuo", XO (4, 396,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhwuo.", XO (4, 396,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vsubshs", VX (4,1856), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, +{"vslv", VX (4,1860), VX_MASK, PPCVEC3, PPCNONE, {VD, VA, VB}}, {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, +{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"maclhwo", XO (4, 428,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -3516,6 +3826,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}}, {"vsumsws", VX (4,1928), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}}, {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}}, +{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, PPCNONE, {RT, RA, VB}}, {"maclhwsuo", XO (4, 460,1,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"maclhwsuo.", XO (4, 460,1,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}}, {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, PPCNONE, {VD, VB}}, @@ -3854,6 +4165,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCNONE, {BF, BFA}}, +{"addpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, DXD}}, +{"subpcis", DX(19,2), DX_MASK, POWER9, PPCNONE, {RT, NDXD}}, + {"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, {"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2, {0}}, {"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCNONE, {0}}, @@ -4113,17 +4427,20 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"crset", XL(19,289), XL_MASK, PPCCOM, PPCNONE, {BT, BAT, BBA}}, {"creqv", XL(19,289), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, -{"doze", XL(19,402), 0xffffffff, POWER6, PPCNONE, {0}}, +{"urfid", XL(19,306), 0xffffffff, POWER9, PPCNONE, {0}}, +{"stop", XL(19,370), 0xffffffff, POWER9, PPCNONE, {0}}, + +{"doze", XL(19,402), 0xffffffff, POWER6, POWER9, {0}}, {"crorc", XL(19,417), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, -{"nap", XL(19,434), 0xffffffff, POWER6, PPCNONE, {0}}, +{"nap", XL(19,434), 0xffffffff, POWER6, POWER9, {0}}, {"crmove", XL(19,449), XL_MASK, PPCCOM, PPCNONE, {BT, BA, BBA}}, {"cror", XL(19,449), XL_MASK, COM, PPCNONE, {BT, BA, BB}}, -{"sleep", XL(19,466), 0xffffffff, POWER6, PPCNONE, {0}}, -{"rvwinkle", XL(19,498), 0xffffffff, POWER6, PPCNONE, {0}}, +{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9, {0}}, +{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9, {0}}, {"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCNONE, {0}}, {"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCNONE, {0}}, @@ -4459,7 +4776,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"ldepx", X(31,29), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, -{"waitasec", X(31,30), XRTRARB_MASK,POWER8, PPCNONE, {0}}, +{"waitasec", X(31,30), XRTRARB_MASK,POWER8, POWER9, {0}}, +{"wait", X(31,30), XWC_MASK, POWER9, PPCNONE, {WC}}, {"lwepx", X(31,31), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RT, RA0, RB}}, @@ -4591,6 +4909,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RA0, RB}}, +{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, PPCNONE, {RT, BFA}}, + {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}}, {"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, @@ -4673,6 +4993,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, PPCNONE, {RA, RS}}, +{"cmprb", X(31,192), XCMP_MASK, POWER9, PPCNONE, {BF, L, RA, RB}}, + {"icblq.", XRC(31,198,1), X_MASK, E6500, PPCNONE, {CT, RA0, RB}}, {"stvewx", X(31,199), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}}, @@ -4711,6 +5033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stbepx", X(31,223), X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE, {RS, RA0, RB}}, +{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, PPCNONE, {BF, RA, RB}}, + {"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA0, RB}}, {"stvx", X(31,231), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VS, RA0, RB}}, @@ -4770,14 +5094,22 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"doz", XO(31,264,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"doz.", XO(31,264,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"modud", X(31,265), X_MASK, POWER9, PPCNONE, {RT, RA, RB}}, + {"add", XO(31,266,0,0), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, {"add.", XO(31,266,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"moduw", X(31,267), X_MASK, POWER9, PPCNONE, {RT, RA, RB}}, + +{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, +{"lxvl", X(31,269), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2|PPCVLE, PPCNONE, {0}}, -{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, PPC476, {RB, L}}, +{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}}, +{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}}, {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, @@ -4805,12 +5137,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lvexhx", X(31,293), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, {"lvepx", X(31,295), X_MASK, PPCVEC2|PPCVLE, PPCNONE, {VD, RA0, RB}}, +{"lxvll", X(31,301), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"mfbhrbe", X(31,302), X_MASK, POWER8, PPCNONE, {RT, BHRBE}}, -{"tlbie", X(31,306), XRA_MASK, POWER7, TITAN, {RB, RS}}, +{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, +{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, {"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}}, {"tlbi", X(31,306), XRT_MASK, POWER, PPCNONE, {RA0, RB}}, +{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, PPCNONE, {RA, XS6}}, + +{"ldmx", X(31,309), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}}, + {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, {"lhzux", X(31,311), X_MASK, COM|PPCVLE, PPCNONE, {RT, RAL, RB}}, @@ -4871,6 +5210,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {RT, PMR}}, {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, PPCNONE, {RT, TMR}}, +{"slbsync", X(31,338), 0xffffffff, POWER9, PPCNONE, {0}}, + {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, PPCNONE, {RT}}, {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RT}}, {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, @@ -5087,6 +5428,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divs", XO(31,363,0,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"divs.", XO(31,363,0,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}}, @@ -5114,10 +5457,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"stxvx", X(31,396), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, +{"stxvl", X(31,397), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, + {"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, {"slbmte", X(31,402), XRA_MASK, PPC64, PPCNONE, {RS, RB}}, +{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, PPCNONE, {XT6, RA}}, + {"pbt.", XRC(31,404,1), X_MASK, POWER8, PPCNONE, {RS, RA0, RB}}, {"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, PPCNONE, {RS, RA, RB}}, @@ -5141,10 +5489,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"stxvll", X(31,429), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, + {"clrbhrb", X(31,430), 0xffffffff, POWER8, PPCNONE, {0}}, {"slbie", X(31,434), XRTRA_MASK, PPC64, PPCNONE, {RB}}, +{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, {"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}}, @@ -5214,6 +5566,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE, {PMR, RS}}, {"mttmr", X(31,494), X_MASK, PPCTMR|E6500, PPCNONE, {TMR, RS}}, +{"slbieg", X(31,466), XRA_MASK, POWER9, PPCNONE, {RS, RB}}, + {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, PPCNONE, {RS}}, {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM|PPCVLE, PPCNONE, {RS}}, @@ -5413,7 +5767,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {RA, RS, RB}}, -{"mcrxr", X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7, {BF}}, +{"mcrxr", X(31,512), XBFRARB_MASK, COM|PPCVLE, POWER7, {BF}}, {"lbdx", X(31,515), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, @@ -5456,6 +5810,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"rrib", XRC(31,537,0), X_MASK, M601, PPCNONE, {RA, RS, RB}}, {"rrib.", XRC(31,537,1), X_MASK, M601, PPCNONE, {RA, RS, RB}}, +{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, +{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, + {"srd", XRC(31,539,0), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, {"srd.", XRC(31,539,1), X_MASK, PPC64, PPCNONE, {RA, RS, RB}}, @@ -5480,10 +5837,17 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, +{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, +{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, PPCNONE, {RA, RS}}, + +{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, PPCNONE, {BF}}, + {"lwdx", X(31,579), X_MASK, E500MC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"lvtlx", X(31,581), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"lwat", X(31,582), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}}, + {"lwfcmux", APU(31,583,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"lxsdx", X(31,588), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, @@ -5496,8 +5860,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}}, {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}}, {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, PPCNONE, {0}}, -{"sync", X(31,598), XSYNCLE_MASK,E6500, PPCNONE, {LS, ESYNC}}, -{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476, {LS}}, +{"sync", X(31,598), XSYNCLE_MASK,POWER9|E6500, PPCNONE, {LS, ESYNC}}, +{"sync", X(31,598), XSYNC_MASK, PPCCOM|PPCVLE, BOOKE|PPC476|POWER9, {LS}}, {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}}, {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, {"lwsync", X(31,598), 0xffffffff, E500, PPCNONE, {0}}, @@ -5512,6 +5876,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lvswx", X(31,613), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"ldat", X(31,614), X_MASK, POWER9, PPCNONE, {RT, RA0, FC}}, + {"lqfcmux", APU(31,615,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"nego", XO(31,104,1,0), XORB_MASK, COM|PPCVLE, PPCNONE, {RT, RA}}, @@ -5584,6 +5950,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvflx", X(31,709), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, +{"stwat", X(31,710), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}}, + {"stwfcmux", APU(31,711,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"stxsdx", X(31,716), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, @@ -5620,6 +5988,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvswx", X(31,741), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, +{"stdat", X(31,742), X_MASK, POWER9, PPCNONE, {RS, RA0, FC}}, + {"stqfcmux", APU(31,743,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, PPCNONE, {RT, RA}}, @@ -5644,6 +6014,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, {"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, PPCNONE, {L}}, +{"darn", X(31,755), XLRAND_MASK, POWER9, PPCNONE, {RT, LRAND}}, + {"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}}, {"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, PPCNONE, {RA0, RB}}, @@ -5653,6 +6025,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"srliq.", XRC(31,760,1), X_MASK, M601, PPCNONE, {RA, RS, SH}}, {"lvsm", X(31,773), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, + +{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, +{"copy", X(31,774), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L}}, + {"stvepxl", X(31,775), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"lvlxl", X(31,775), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, {"ldfcmux", APU(31,775,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -5665,7 +6041,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}}, {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}}, +{"modsd", X(31,777), X_MASK, POWER9, PPCNONE, {RT, RA, RB}}, +{"modsw", X(31,779), X_MASK, POWER9, PPCNONE, {RT, RA, RB}}, + {"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, +{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, {"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, @@ -5692,6 +6072,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stvepx", X(31,807), X_MASK, PPCVEC2, PPCNONE, {VS, RA0, RB}}, {"lvrxl", X(31,807), X_MASK, CELL, PPCNONE, {VD, RA0, RB}}, +{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, +{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, RB}}, {"rac", X(31,818), X_MASK, M601, PPCNONE, {RT, RA, RB}}, @@ -5714,17 +6097,20 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lvtlxl", X(31,837), X_MASK, PPCVEC2, PPCNONE, {VD, RA0, RB}}, +{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, PPCNONE, {0}}, + {"divo", XO(31,331,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"divo.", XO(31,331,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"lxvd2x", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, -{"lxvx", X(31,844), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA0, RB}}, +{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, {"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, PPCNONE, {RA0, RB}}, -{"slbmfev", X(31,851), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, +{"slbmfev", X(31,851), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}}, +{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, {"lbzcix", X(31,853), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, @@ -5743,12 +6129,25 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divso", XO(31,363,1,0), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, {"divso.", XO(31,363,1,1), XO_MASK, M601, PPCNONE, {RT, RA, RB}}, +{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}}, + {"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, PPCNONE, {TO, RA, HTM_SI}}, +{"rmieg", X(31,882), XRTRA_MASK, POWER9, PPCNONE, {RB}}, + {"ldcix", X(31,885), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}}, +{"msgsync", X(31,886), 0xffffffff, POWER9, PPCNONE, {0}}, + {"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, PPCNONE, {FRT, RA0, RB}}, +{"extswsli", XS(31,445,0), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}}, +{"extswsli.", XS(31,445,1), XS_MASK, POWER9, PPCNONE, {RA, RS, SH6}}, + +{"paste", XRC(31,902,0), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L0}}, +{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, PPCNONE, {RA0, RB}}, +{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, PPCNONE, {RA0, RB, L1}}, + {"stvlxl", X(31,903), X_MASK, CELL, PPCNONE, {VS, RA0, RB}}, {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}}, @@ -5758,13 +6157,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"stxvw4x", X(31,908), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, +{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, {"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, {"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, {"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}}, -{"slbmfee", X(31,915), XRA_MASK, PPC64, PPCNONE, {RT, RB}}, +{"slbmfee", X(31,915), XRLA_MASK, POWER9, PPCNONE, {RT, RB, A_L}}, +{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, {"stwcix", X(31,917), X_MASK, POWER6, PPCNONE, {RS, RA0, RB}}, @@ -5799,6 +6200,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, PPCNONE, {RT, RA, RB}}, +{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, +{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, + {"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, PPCNONE, {RA}}, {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}}, @@ -5830,7 +6234,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwuo.", XO(31,459,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"stxvd2x", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, -{"stxvx", X(31,972), XX1_MASK, PPCVSX, PPCNONE, {XS6, RA0, RB}}, +{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, {"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, PPCNONE, {RT, RA}}, @@ -5863,6 +6267,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwo", XO(31,491,1,0), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, {"divwo.", XO(31,491,1,1), XO_MASK, PPC|PPCVLE, PPCNONE, {RT, RA, RB}}, +{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, PPCNONE, {XS6, RA0, RB}}, + {"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, PPCNONE, {0}}, {"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, @@ -5947,6 +6353,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"psq_l", OP(56), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, {"lfq", OP(56), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, +{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}}, +{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCNONE, {VD, DS, RA0}}, {"lfdp", OP(57), OP_MASK, POWER6, POWER7, {FRTp, DS, RA0}}, {"psq_lu", OP(57), OP_MASK, PPCPS, PPCNONE, {FRT,PSD,RA,PSW,PSQ}}, {"lfqu", OP(57), OP_MASK, POWER2, PPCNONE, {FRT, D, RA0}}, @@ -6046,6 +6454,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcmpu", X(59,642), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, {"dtstsf", X(59,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRB}}, +{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRB}}, {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCNONE, {FRT, FRB}}, @@ -6068,6 +6477,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, SHW}}, +{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, XC6}}, {"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, @@ -6076,163 +6488,203 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, {"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6, DM}}, -{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, {"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, -{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xscmpnedp", XX3(60,27), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCNONE, {BF, XA6, XB6}}, +{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, {"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, +{"xxextractuw", XX2(60,165), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}}, {"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3,PPCNONE, {XT6, IMM8}}, +{"xxinsertw", XX2(60,181), XX2UIM4_MASK,PPCVSX3, PPCNONE, {XT6, XB6, UIMM4}}, +{"xvcmpnesp", XX3RC(60,91,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpnesp.", XX3RC(60,91,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, {"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, -{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, +{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcmpnedp", XX3RC(60,123,0), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvcmpnedp.", XX3RC(60,123,1), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCNONE, {BF, XA6, XB6}}, +{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, -{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, {"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, +{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}}, +{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, {"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, -{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, {"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCNONE, {XT6, XB6, UIM}}, +{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, {"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, {"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, -{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}}, +{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCNONE, {RT, XB6}}, +{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, {"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCNONE, {BF, XB6, DCMX}}, {"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCNONE, {XT6, XA6, XB6}}, +{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, {"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCNONE, {BF, XB6}}, -{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, -{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, -{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCNONE, {XT6, XB6}}, -{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, -{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}}, +{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA, RB}}, +{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCNONE, {XT6, XB6}}, +{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6S}}, +{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, +{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK,PPCVSX3, PPCNONE, {XT6, XB6, DCMXS}}, +{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCNONE, {XT6, XA6, XB6}}, +{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCNONE, {XT6, XA6, XB6}}, {"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCNONE, {XT6, XB6}}, {"psq_st", OP(60), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, {"stfq", OP(60), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, +{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCNONE, {XTQ6, DQ, RA0}}, +{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCNONE, {XSQ6, DQ, RA0}}, +{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}}, +{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCNONE, {VS, DS, RA0}}, {"stfdp", OP(61), OP_MASK, POWER6, POWER7, {FRSp, DS, RA0}}, {"psq_stu", OP(61), OP_MASK, PPCPS, PPCNONE, {FRS,PSD,RA,PSW,PSQ}}, {"stfqu", OP(61), OP_MASK, POWER2, PPCNONE, {FRS, D, RA}}, @@ -6241,7 +6693,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stdu", DSO(62,1), DS_MASK, PPC64, PPCNONE, {RS, DS, RAS}}, {"stq", DSO(62,2), DS_MASK, POWER4, PPC476, {RSQ, DS, RA0}}, -{"fcmpu", X(63,0), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, +{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}}, {"daddq", XRC(63,2,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, {"daddq.", XRC(63,2,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, @@ -6249,6 +6701,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dquaq", ZRC(63,3,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, {"dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp, RMC}}, +{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + +{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}}, +{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}}, + {"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, {"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FRT, FRA, FRB}}, @@ -6321,7 +6779,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS, {FRT, FRA, FRC, FRB}}, {"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCNONE, {FRT, FRA, FRC, FRB}}, -{"fcmpo", X(63,32), X_MASK|(3<<21), COM, PPCEFS, {BF, FRA, FRB}}, +{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS, {BF, FRA, FRB}}, {"dmulq", XRC(63,34,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, {"dmulq.", XRC(63,34,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, @@ -6329,6 +6787,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"drrndq", ZRC(63,35,0), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, {"drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp, RMC}}, +{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + +{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCNONE, {R, VD, VB, RMC}}, + {"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCNONE, {BT}}, {"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCNONE, {BT}}, @@ -6355,10 +6818,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"drintxq", ZRC(63,99,0), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, {"drintxq.", ZRC(63,99,1), Z2_MASK, POWER6, PPCNONE, {R, FRTp, FRBp, RMC}}, -{"ftdiv", X(63,128), X_MASK|(3<<21), POWER7, PPCNONE, {BF, FRA, FRB}}, +{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + +{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCNONE, {BF, FRA, FRB}}, {"dcmpoq", X(63,130), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, +{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}}, + {"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, {"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476, {BFF, U}}, {"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCNONE, {BFF, U, W}}, @@ -6372,9 +6839,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, {"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCNONE, {FRT, FRB}}, -{"ftsqrt", X(63,160), X_MASK|(3<<21|FRA_MASK), POWER7, PPCNONE, {BF, FRB}}, +{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCNONE, {BF, FRB}}, {"dtstexq", X(63,162), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, + +{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}}, + {"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DCM}}, {"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCNONE, {BF, FRAp, DGM}}, @@ -6396,27 +6866,53 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, {"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCNONE, {FRT, FRBp}}, +{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, + +{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, + +{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, + +{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCNONE, {FRT, FRB}}, {"dsubq", XRC(63,514,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, {"dsubq.", XRC(63,514,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, +{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"ddivq", XRC(63,546,0), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, {"ddivq.", XRC(63,546,1), X_MASK, POWER6, PPCNONE, {FRTp, FRAp, FRBp}}, +{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, +{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS, {FRT}}, {"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS, {FRT}}, {"dcmpuq", X(63,642), X_MASK, POWER6, PPCNONE, {BF, FRAp, FRBp}}, +{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCNONE, {BF, VA, VB}}, + {"dtstsfq", X(63,674), X_MASK, POWER6, PPCNONE, {BF, FRA, FRBp}}, +{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCNONE, {BF, UIM6, FRBp}}, + +{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCNONE, {BF, VB, DCMX}}, {"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCNONE, {FLM, FRB, XFL_L, W}}, {"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS, {FLM, FRB}}, @@ -6429,6 +6925,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dcffixq", XRC(63,802,0), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, {"dcffixq.", XRC(63,802,1), X_MASK, POWER6, PPCNONE, {FRTp, FRB}}, +{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, + {"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, {"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCNONE, {FRT, FRB}}, {"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, @@ -6442,6 +6946,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"denbcdq", XRC(63,834,0), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}}, {"denbcdq.", XRC(63,834,1), X_MASK, POWER6, PPCNONE, {S, FRTp, FRBp}}, +{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, +{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCNONE, {VD, VB}}, + {"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCNONE, {FRT, FRA, FRB}}, {"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCNONE, {FRT, FRB}}, @@ -6452,6 +6966,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"diexq", XRC(63,866,0), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, {"diexq.", XRC(63,866,1), X_MASK, POWER6, PPCNONE, {FRTp, FRA, FRBp}}, +{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCNONE, {VD, VA, VB}}, + {"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, {"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCNONE, {FRT, FRB}}, |