diff options
Diffstat (limited to 'opcodes/mips-opc.c')
| -rw-r--r-- | opcodes/mips-opc.c | 49 |
1 files changed, 9 insertions, 40 deletions
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index e33b561..9a80de6 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -300,7 +300,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5_33|IL2F }, {"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_D|RD_S|FP_D, 0, IL2E }, {"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC }, -{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, 0, MC }, {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC }, {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 }, {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 }, @@ -340,7 +339,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, 0, MX }, {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 }, {"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, SM|RD_b|NODS, 0, 0, MC }, -{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, 0, MC }, {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC }, {"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, /* b is at the top of the table. */ @@ -869,9 +867,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, IOCT2 }, {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 }, /* The macro has to be first to handle o32 correctly. */ -{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 }, {"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, {"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, {"ldaddd", "t,b", 0x70000012, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR }, @@ -880,7 +877,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2, 0, SF }, /* ldc1 */ -{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, @@ -1397,10 +1393,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, SB1, MX }, {"rzu.ob", "D,Q", 0x48000020, 0xfc20f83f, WR_D|RD_S|RD_T, 0, N54 }, {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, 0, MX }, -{"saa", "t,o(b)", 0, (int) M_SAA_OB, INSN_MACRO, 0, IOCTP }, {"saa", "t,A(b)", 0, (int) M_SAA_AB, INSN_MACRO, 0, IOCTP }, {"saa", "t,(b)", 0x70000018, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP }, -{"saad", "t,o(b)", 0, (int) M_SAAD_OB, INSN_MACRO, 0, IOCTP }, {"saad", "t,A(b)", 0, (int) M_SAAD_AB, INSN_MACRO, 0, IOCTP }, {"saad", "t,(b)", 0x70000019, 0xfc00ffff, SM|RD_t|RD_b, 0, IOCTP }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 }, @@ -1410,9 +1404,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3, 0, EE }, {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, /* The macro has to be first to handle o32 correctly. */ -{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 }, -{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 }, +{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 }, {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 }, {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 }, @@ -1427,7 +1420,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2, 0, SF }, -{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, INSN2_M_FP_D, I1 }, {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1 }, {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 }, {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 }, @@ -1636,20 +1628,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE }, {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2, 0, EE }, {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, -{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 }, -{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 }, -{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 }, -{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 }, -{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 }, -{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 }, -{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 }, -{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 }, -{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 }, -{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 }, -{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 }, +{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1 }, +{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3 }, +{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1 }, +{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1 }, {"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, {"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, IOCT }, @@ -2258,52 +2243,36 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, IL2F|IL3A }, /* MIPS Enhanced VA Scheme */ {"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lbue", "t,o(b)", 0, (int) M_LBUE_OB, INSN_MACRO, 0, 0, EVA }, {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA }, {"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lhue", "t,o(b)", 0, (int) M_LHUE_OB, INSN_MACRO, 0, 0, EVA }, {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA }, {"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lbe", "t,o(b)", 0, (int) M_LBE_OB, INSN_MACRO, 0, 0, EVA }, {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA }, {"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lhe", "t,o(b)", 0, (int) M_LHE_OB, INSN_MACRO, 0, 0, EVA }, {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA }, {"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lle", "t,o(b)", 0, (int) M_LLE_OB, INSN_MACRO, 0, 0, EVA }, {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA }, {"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lwe", "t,o(b)", 0, (int) M_LWE_OB, INSN_MACRO, 0, 0, EVA }, {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA }, {"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lwle", "t,o(b)", 0, (int) M_LWLE_OB, INSN_MACRO, 0, 0, EVA }, {"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA }, {"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, LDD|RD_b|WR_t, 0, 0, EVA }, -{"lwre", "t,o(b)", 0, (int) M_LWRE_OB, INSN_MACRO, 0, 0, EVA }, {"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA }, {"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, -{"sbe", "t,o(b)", 0, (int) M_SBE_OB, INSN_MACRO, 0, 0, EVA }, {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA }, {"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, SM|RD_t|WR_t|RD_b, 0, 0, EVA }, -{"sce", "t,o(b)", 0, (int) M_SCE_OB, INSN_MACRO, 0, 0, EVA }, {"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA }, {"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, -{"she", "t,o(b)", 0, (int) M_SHE_OB, INSN_MACRO, 0, 0, EVA }, {"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA }, {"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, -{"swe", "t,o(b)", 0, (int) M_SWE_OB, INSN_MACRO, 0, 0, EVA }, {"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA }, {"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, -{"swle", "t,o(b)", 0, (int) M_SWLE_OB, INSN_MACRO, 0, 0, EVA }, {"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA }, {"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, SM|RD_t|RD_b, 0, 0, EVA }, -{"swre", "t,o(b)", 0, (int) M_SWRE_OB, INSN_MACRO, 0, 0, EVA }, {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA }, {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_b, 0, 0, EVA }, -{"cachee", "k,o(b)", 0, (int) M_CACHEE_OB,INSN_MACRO, 0, 0, EVA }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA }, {"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_b, 0, 0, EVA }, -{"prefe", "k,o(b)", 0, (int) M_PREFE_OB, INSN_MACRO, 0, 0, EVA }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA }, /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the |