diff options
Diffstat (limited to 'opcodes/m32r-opc.c')
| -rw-r--r-- | opcodes/m32r-opc.c | 768 |
1 files changed, 331 insertions, 437 deletions
diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index 394d683..e9c1f74 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -3,7 +3,7 @@ THIS FILE IS USED TO GENERATE m32r-opc.c. -Copyright (C) 1998 Free Software Foundation, Inc. +Copyright (C) 1998, 1999 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -558,8 +558,8 @@ static const CGEN_OPERAND_INSTANCE fmt_add_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_add3_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; @@ -588,25 +588,25 @@ static const CGEN_OPERAND_INSTANCE fmt_addi_ops[] = { static const CGEN_OPERAND_INSTANCE fmt_addv_ops[] = { { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_addv3_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_addx_ops[] = { + { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; @@ -625,31 +625,31 @@ static const CGEN_OPERAND_INSTANCE fmt_bc24_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_beq_ops[] = { + { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, - { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_beqz_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "disp16", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP16), 0, COND_REF }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_bl8_ops[] = { - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, 0 }, + { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = { - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, 0 }, + { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { 0 } @@ -658,8 +658,8 @@ static const CGEN_OPERAND_INSTANCE fmt_bl24_ops[] = { /* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = { { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { INPUT, "disp8", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP8), 0, COND_REF }, + { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { 0 } @@ -669,8 +669,8 @@ static const CGEN_OPERAND_INSTANCE fmt_bcl8_ops[] = { /* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_bcl24_ops[] = { { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { INPUT, "disp24", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (DISP24), 0, COND_REF }, + { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, COND_REF }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF }, { 0 } @@ -697,13 +697,22 @@ static const CGEN_OPERAND_INSTANCE fmt_cmp_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, { 0 } }; /* start-sanitize-m32rx */ +static const CGEN_OPERAND_INSTANCE fmt_cmpeq_ops[] = { + { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, + { 0 } +}; + +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = { { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, @@ -712,12 +721,21 @@ static const CGEN_OPERAND_INSTANCE fmt_cmpz_ops[] = { /* end-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_div_ops[] = { + { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, + { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, + { 0 } +}; + +/* start-sanitize-m32rx */ +static const CGEN_OPERAND_INSTANCE fmt_divh_ops[] = { { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, COND_REF }, { 0 } }; +/* end-sanitize-m32rx */ /* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_jc_ops[] = { { INPUT, "condbit", & HW_ENT (HW_H_COND), CGEN_MODE_BI, 0, 0, 0 }, @@ -742,53 +760,53 @@ static const CGEN_OPERAND_INSTANCE fmt_jmp_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_ld_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ld_d_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ldb_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ldb_d_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, + { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ldh_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ldh_d_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, - { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "h_memory_add__VM_sr_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, + { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_ld_plus_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { OUTPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { 0 } @@ -813,10 +831,10 @@ static const CGEN_OPERAND_INSTANCE fmt_ldi16_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_lock_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { INPUT, "h_memory_sr", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, - { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, + { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, { 0 } }; @@ -911,21 +929,21 @@ static const CGEN_OPERAND_INSTANCE fmt_rac_ops[] = { /* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_rac_dsi_ops[] = { { INPUT, "accs", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0, 0 }, - { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0, 0 }, + { INPUT, "imm1", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (IMM1), 0, 0 }, { OUTPUT, "accd", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0, 0 }, { 0 } }; /* end-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_rte_ops[] = { - { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, - { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, { INPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, + { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, + { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, - { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { 0 } }; @@ -936,82 +954,82 @@ static const CGEN_OPERAND_INSTANCE fmt_seth_ops[] = { }; static const CGEN_OPERAND_INSTANCE fmt_sll3_ops[] = { - { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { INPUT, "simm16", & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0, 0 }, + { INPUT, "sr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_slli_ops[] = { { INPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, - { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0, 0 }, + { INPUT, "uimm5", & HW_ENT (HW_H_UINT), CGEN_MODE_INT, & OP_ENT (UIMM5), 0, 0 }, { OUTPUT, "dr", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_st_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_st_d_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_stb_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_stb_d_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_QI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_sth_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_sth_d_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "slo16", & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_HI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_add__VM_src2_slo16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_st_plus_ops[] = { - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { OUTPUT, "h_memory_new_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 }, { OUTPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, { 0 } }; static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = { - { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, - { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, { INPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, + { INPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, { INPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, - { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (UIMM4), 0, 0 }, - { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, - { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, + { INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 }, + { INPUT, "uimm4", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0, 0 }, { OUTPUT, "h_bbpsw_0", & HW_ENT (HW_H_BBPSW), CGEN_MODE_UQI, 0, 0, 0 }, { OUTPUT, "h_bpsw_0", & HW_ENT (HW_H_BPSW), CGEN_MODE_UQI, 0, 0, 0 }, + { OUTPUT, "h_cr_14", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 14, 0 }, + { OUTPUT, "h_cr_6", & HW_ENT (HW_H_CR), CGEN_MODE_USI, 0, 6, 0 }, { OUTPUT, "h_psw_0", & HW_ENT (HW_H_PSW), CGEN_MODE_UQI, 0, 0, 0 }, { OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 }, { 0 } @@ -1019,10 +1037,10 @@ static const CGEN_OPERAND_INSTANCE fmt_trap_ops[] = { static const CGEN_OPERAND_INSTANCE fmt_unlock_ops[] = { { INPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, - { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF }, { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, COND_REF }, - { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (SRC2), 0, COND_REF }, { OUTPUT, "h_lock_0", & HW_ENT (HW_H_LOCK), CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "h_memory_src2", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, COND_REF }, { 0 } }; @@ -1045,8 +1063,8 @@ static const CGEN_OPERAND_INSTANCE fmt_sat_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_sadd_ops[] = { - { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, { INPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "h_accums_1", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1, 0 }, { OUTPUT, "h_accums_0", & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0, 0 }, { 0 } }; @@ -1063,6 +1081,16 @@ static const CGEN_OPERAND_INSTANCE fmt_macwu1_ops[] = { /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ +static const CGEN_OPERAND_INSTANCE fmt_msblo_ops[] = { + { INPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, + { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, + { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, + { OUTPUT, "accum", & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0, 0 }, + { 0 } +}; + +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ static const CGEN_OPERAND_INSTANCE fmt_mulwu1_ops[] = { { INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 }, { INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 }, @@ -1086,312 +1114,178 @@ static const CGEN_OPERAND_INSTANCE fmt_sc_ops[] = { #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] -static const CGEN_IFMT fmt_empty = { +static const CGEN_IFMT ifmt_empty = { 0, 0, 0x0, { 0 } }; -static const CGEN_IFMT fmt_add = { +static const CGEN_IFMT ifmt_add = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_add3 = { +static const CGEN_IFMT ifmt_add3 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_and3 = { +static const CGEN_IFMT ifmt_and3 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } }; -static const CGEN_IFMT fmt_or3 = { +static const CGEN_IFMT ifmt_or3 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } }; -static const CGEN_IFMT fmt_addi = { +static const CGEN_IFMT ifmt_addi = { 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } }; -static const CGEN_IFMT fmt_addv = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_addv3 = { +static const CGEN_IFMT ifmt_addv3 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_addx = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_bc8 = { +static const CGEN_IFMT ifmt_bc8 = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; -static const CGEN_IFMT fmt_bc24 = { +static const CGEN_IFMT ifmt_bc24 = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; -static const CGEN_IFMT fmt_beq = { +static const CGEN_IFMT ifmt_beq = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } }; -static const CGEN_IFMT fmt_beqz = { +static const CGEN_IFMT ifmt_beqz = { 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_DISP16), 0 } }; -static const CGEN_IFMT fmt_bl8 = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } -}; - -static const CGEN_IFMT fmt_bl24 = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } -}; - /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bcl8 = { +static const CGEN_IFMT ifmt_bcl8 = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bcl24 = { +static const CGEN_IFMT ifmt_bcl24 = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_bra8 = { - 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } +static const CGEN_IFMT ifmt_cmp = { + 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_bra24 = { - 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } +static const CGEN_IFMT ifmt_cmpi = { + 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_cmp = { +/* start-sanitize-m32rx */ +static const CGEN_IFMT ifmt_cmpeq = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_cmpi = { - 32, 32, 0xfff00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - +/* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_cmpz = { +static const CGEN_IFMT ifmt_cmpz = { 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_div = { +static const CGEN_IFMT ifmt_div = { 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_jc = { - 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } +static const CGEN_IFMT ifmt_divh = { + 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_jl = { +/* start-sanitize-m32rx */ +static const CGEN_IFMT ifmt_jc = { 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_jmp = { +/* end-sanitize-m32rx */ +static const CGEN_IFMT ifmt_jl = { 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ld = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_ld_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_ldb = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_ldb_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_ldh = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_ldh_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_ld_plus = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_ld24 = { +static const CGEN_IFMT ifmt_ld24 = { 32, 32, 0xf0000000, { F (F_OP1), F (F_R1), F (F_UIMM24), 0 } }; -static const CGEN_IFMT fmt_ldi8 = { - 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } -}; - -static const CGEN_IFMT fmt_ldi16 = { +static const CGEN_IFMT ifmt_ldi16 = { 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_lock = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_machi = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_machi_a = { +static const CGEN_IFMT ifmt_machi_a = { 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_mulhi = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_mulhi_a = { - 16, 16, 0xf070, { F (F_OP1), F (F_R1), F (F_ACC), F (F_OP23), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_mv = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_mvfachi = { +static const CGEN_IFMT ifmt_mvfachi = { 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_mvfachi_a = { +static const CGEN_IFMT ifmt_mvfachi_a = { 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_mvfc = { +static const CGEN_IFMT ifmt_mvfc = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_mvtachi = { +static const CGEN_IFMT ifmt_mvtachi = { 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_mvtachi_a = { +static const CGEN_IFMT ifmt_mvtachi_a = { 16, 16, 0xf0f3, { F (F_OP1), F (F_R1), F (F_OP2), F (F_ACCS), F (F_OP3), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_mvtc = { +static const CGEN_IFMT ifmt_mvtc = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_nop = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_rac = { +static const CGEN_IFMT ifmt_nop = { 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_rac_dsi = { +static const CGEN_IFMT ifmt_rac_dsi = { 16, 16, 0xf3f2, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_rte = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_seth = { +static const CGEN_IFMT ifmt_seth = { 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_HI16), 0 } }; -static const CGEN_IFMT fmt_sll3 = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_slli = { +static const CGEN_IFMT ifmt_slli = { 16, 16, 0xf0e0, { F (F_OP1), F (F_R1), F (F_SHIFT_OP2), F (F_UIMM5), 0 } }; -static const CGEN_IFMT fmt_st = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_st_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_stb = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_stb_d = { - 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } -}; - -static const CGEN_IFMT fmt_sth = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_sth_d = { +static const CGEN_IFMT ifmt_st_d = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_st_plus = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -static const CGEN_IFMT fmt_trap = { +static const CGEN_IFMT ifmt_trap = { 16, 16, 0xfff0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_UIMM4), 0 } }; -static const CGEN_IFMT fmt_unlock = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_satb = { +static const CGEN_IFMT ifmt_satb = { 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_sat = { - 32, 32, 0xf0f0ffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_UIMM16), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_sadd = { - 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_macwu1 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_mulwu1 = { - 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } -}; - -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_sc = { +static const CGEN_IFMT ifmt_sadd = { 16, 16, 0xffff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; @@ -1417,7 +1311,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADD, "add", "add", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0xa0 }, + & ifmt_add, { 0xa0 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1426,7 +1320,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADD3, "add3", "add3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, - & fmt_add3, { 0x80a00000 }, + & ifmt_add3, { 0x80a00000 }, (PTR) & fmt_add3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1435,7 +1329,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_AND, "and", "and", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0xc0 }, + & ifmt_add, { 0xc0 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1444,7 +1338,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_AND3, "and3", "and3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, - & fmt_and3, { 0x80c00000 }, + & ifmt_and3, { 0x80c00000 }, (PTR) & fmt_and3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1453,7 +1347,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_OR, "or", "or", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0xe0 }, + & ifmt_add, { 0xe0 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1462,7 +1356,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_OR3, "or3", "or3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } }, - & fmt_or3, { 0x80e00000 }, + & ifmt_or3, { 0x80e00000 }, (PTR) & fmt_or3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1471,7 +1365,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_XOR, "xor", "xor", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0xd0 }, + & ifmt_add, { 0xd0 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1480,7 +1374,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_XOR3, "xor3", "xor3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, - & fmt_and3, { 0x80d00000 }, + & ifmt_and3, { 0x80d00000 }, (PTR) & fmt_and3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1489,7 +1383,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADDI, "addi", "addi", { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & fmt_addi, { 0x4000 }, + & ifmt_addi, { 0x4000 }, (PTR) & fmt_addi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1498,7 +1392,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADDV, "addv", "addv", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_addv, { 0x80 }, + & ifmt_add, { 0x80 }, (PTR) & fmt_addv_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1507,7 +1401,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADDV3, "addv3", "addv3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & fmt_addv3, { 0x80800000 }, + & ifmt_addv3, { 0x80800000 }, (PTR) & fmt_addv3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1516,7 +1410,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ADDX, "addx", "addx", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_addx, { 0x90 }, + & ifmt_add, { 0x90 }, (PTR) & fmt_addx_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1525,7 +1419,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BC8, "bc8", "bc.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bc8, { 0x7c00 }, + & ifmt_bc8, { 0x7c00 }, (PTR) & fmt_bc8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1534,7 +1428,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BC24, "bc24", "bc.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bc24, { 0xfc000000 }, + & ifmt_bc24, { 0xfc000000 }, (PTR) & fmt_bc24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1543,7 +1437,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BEQ, "beq", "beq", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beq, { 0xb0000000 }, + & ifmt_beq, { 0xb0000000 }, (PTR) & fmt_beq_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1552,7 +1446,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BEQZ, "beqz", "beqz", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0800000 }, + & ifmt_beqz, { 0xb0800000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1561,7 +1455,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BGEZ, "bgez", "bgez", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0b00000 }, + & ifmt_beqz, { 0xb0b00000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1570,7 +1464,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BGTZ, "bgtz", "bgtz", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0d00000 }, + & ifmt_beqz, { 0xb0d00000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1579,7 +1473,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BLEZ, "blez", "blez", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0c00000 }, + & ifmt_beqz, { 0xb0c00000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1588,7 +1482,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BLTZ, "bltz", "bltz", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0a00000 }, + & ifmt_beqz, { 0xb0a00000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1597,7 +1491,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNEZ, "bnez", "bnez", { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beqz, { 0xb0900000 }, + & ifmt_beqz, { 0xb0900000 }, (PTR) & fmt_beqz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1606,7 +1500,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BL8, "bl8", "bl.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bl8, { 0x7e00 }, + & ifmt_bc8, { 0x7e00 }, (PTR) & fmt_bl8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1615,7 +1509,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BL24, "bl24", "bl.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bl24, { 0xfe000000 }, + & ifmt_bc24, { 0xfe000000 }, (PTR) & fmt_bl24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1625,7 +1519,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BCL8, "bcl8", "bcl.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bcl8, { 0x7800 }, + & ifmt_bcl8, { 0x7800 }, (PTR) & fmt_bcl8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -1636,7 +1530,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BCL24, "bcl24", "bcl.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bcl24, { 0xf8000000 }, + & ifmt_bcl24, { 0xf8000000 }, (PTR) & fmt_bcl24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -1646,7 +1540,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNC8, "bnc8", "bnc.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bc8, { 0x7d00 }, + & ifmt_bc8, { 0x7d00 }, (PTR) & fmt_bc8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1655,7 +1549,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNC24, "bnc24", "bnc.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bc24, { 0xfd000000 }, + & ifmt_bc24, { 0xfd000000 }, (PTR) & fmt_bc24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1664,7 +1558,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNE, "bne", "bne", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } }, - & fmt_beq, { 0xb0100000 }, + & ifmt_beq, { 0xb0100000 }, (PTR) & fmt_beq_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1673,7 +1567,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BRA8, "bra8", "bra.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bra8, { 0x7f00 }, + & ifmt_bc8, { 0x7f00 }, (PTR) & fmt_bra8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1682,7 +1576,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BRA24, "bra24", "bra.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bra24, { 0xff000000 }, + & ifmt_bc24, { 0xff000000 }, (PTR) & fmt_bra24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1692,7 +1586,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNCL8, "bncl8", "bncl.s", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bcl8, { 0x7900 }, + & ifmt_bcl8, { 0x7900 }, (PTR) & fmt_bcl8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -1703,7 +1597,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_BNCL24, "bncl24", "bncl.l", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bcl24, { 0xf9000000 }, + & ifmt_bcl24, { 0xf9000000 }, (PTR) & fmt_bcl24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -1713,7 +1607,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMP, "cmp", "cmp", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_cmp, { 0x40 }, + & ifmt_cmp, { 0x40 }, (PTR) & fmt_cmp_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1722,7 +1616,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMPI, "cmpi", "cmpi", { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, - & fmt_cmpi, { 0x80400000 }, + & ifmt_cmpi, { 0x80400000 }, (PTR) & fmt_cmpi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1731,7 +1625,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMPU, "cmpu", "cmpu", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_cmp, { 0x50 }, + & ifmt_cmp, { 0x50 }, (PTR) & fmt_cmp_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1740,7 +1634,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMPUI, "cmpui", "cmpui", { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } }, - & fmt_cmpi, { 0x80500000 }, + & ifmt_cmpi, { 0x80500000 }, (PTR) & fmt_cmpi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1750,8 +1644,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMPEQ, "cmpeq", "cmpeq", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_cmp, { 0x60 }, - (PTR) & fmt_cmp_ops[0], + & ifmt_cmpeq, { 0x60 }, + (PTR) & fmt_cmpeq_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } }, /* end-sanitize-m32rx */ @@ -1761,7 +1655,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_CMPZ, "cmpz", "cmpz", { { MNEM, ' ', OP (SRC2), 0 } }, - & fmt_cmpz, { 0x70 }, + & ifmt_cmpz, { 0x70 }, (PTR) & fmt_cmpz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } }, @@ -1771,7 +1665,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_DIV, "div", "div", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_div, { 0x90000000 }, + & ifmt_div, { 0x90000000 }, (PTR) & fmt_div_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1780,7 +1674,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_DIVU, "divu", "divu", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_div, { 0x90100000 }, + & ifmt_div, { 0x90100000 }, (PTR) & fmt_div_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1789,7 +1683,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_REM, "rem", "rem", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_div, { 0x90200000 }, + & ifmt_div, { 0x90200000 }, (PTR) & fmt_div_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1798,7 +1692,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_REMU, "remu", "remu", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_div, { 0x90300000 }, + & ifmt_div, { 0x90300000 }, (PTR) & fmt_div_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1808,8 +1702,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_DIVH, "divh", "divh", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_div, { 0x90000010 }, - (PTR) & fmt_div_ops[0], + & ifmt_divh, { 0x90000010 }, + (PTR) & fmt_divh_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } }, /* end-sanitize-m32rx */ @@ -1819,7 +1713,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_JC, "jc", "jc", { { MNEM, ' ', OP (SR), 0 } }, - & fmt_jc, { 0x1cc0 }, + & ifmt_jc, { 0x1cc0 }, (PTR) & fmt_jc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -1830,7 +1724,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_JNC, "jnc", "jnc", { { MNEM, ' ', OP (SR), 0 } }, - & fmt_jc, { 0x1dc0 }, + & ifmt_jc, { 0x1dc0 }, (PTR) & fmt_jc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -1840,7 +1734,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_JL, "jl", "jl", { { MNEM, ' ', OP (SR), 0 } }, - & fmt_jl, { 0x1ec0 }, + & ifmt_jl, { 0x1ec0 }, (PTR) & fmt_jl_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1849,7 +1743,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_JMP, "jmp", "jmp", { { MNEM, ' ', OP (SR), 0 } }, - & fmt_jmp, { 0x1fc0 }, + & ifmt_jl, { 0x1fc0 }, (PTR) & fmt_jmp_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -1858,7 +1752,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LD, "ld", "ld", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_ld, { 0x20c0 }, + & ifmt_add, { 0x20c0 }, (PTR) & fmt_ld_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1867,7 +1761,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LD_D, "ld-d", "ld", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & fmt_ld_d, { 0xa0c00000 }, + & ifmt_add3, { 0xa0c00000 }, (PTR) & fmt_ld_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1876,7 +1770,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDB, "ldb", "ldb", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_ldb, { 0x2080 }, + & ifmt_add, { 0x2080 }, (PTR) & fmt_ldb_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1885,7 +1779,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDB_D, "ldb-d", "ldb", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & fmt_ldb_d, { 0xa0800000 }, + & ifmt_add3, { 0xa0800000 }, (PTR) & fmt_ldb_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1894,7 +1788,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDH, "ldh", "ldh", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_ldh, { 0x20a0 }, + & ifmt_add, { 0x20a0 }, (PTR) & fmt_ldh_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1903,7 +1797,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDH_D, "ldh-d", "ldh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & fmt_ldh_d, { 0xa0a00000 }, + & ifmt_add3, { 0xa0a00000 }, (PTR) & fmt_ldh_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1912,7 +1806,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDUB, "ldub", "ldub", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_ldb, { 0x2090 }, + & ifmt_add, { 0x2090 }, (PTR) & fmt_ldb_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1921,7 +1815,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDUB_D, "ldub-d", "ldub", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & fmt_ldb_d, { 0xa0900000 }, + & ifmt_add3, { 0xa0900000 }, (PTR) & fmt_ldb_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1930,7 +1824,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDUH, "lduh", "lduh", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_ldh, { 0x20b0 }, + & ifmt_add, { 0x20b0 }, (PTR) & fmt_ldh_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1939,7 +1833,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDUH_D, "lduh-d", "lduh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } }, - & fmt_ldh_d, { 0xa0b00000 }, + & ifmt_add3, { 0xa0b00000 }, (PTR) & fmt_ldh_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1948,7 +1842,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LD_PLUS, "ld-plus", "ld", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } }, - & fmt_ld_plus, { 0x20e0 }, + & ifmt_add, { 0x20e0 }, (PTR) & fmt_ld_plus_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1957,7 +1851,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LD24, "ld24", "ld24", { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } }, - & fmt_ld24, { 0xe0000000 }, + & ifmt_ld24, { 0xe0000000 }, (PTR) & fmt_ld24_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1966,7 +1860,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDI8, "ldi8", "ldi8", { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & fmt_ldi8, { 0x6000 }, + & ifmt_addi, { 0x6000 }, (PTR) & fmt_ldi8_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -1975,7 +1869,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LDI16, "ldi16", "ldi16", { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, - & fmt_ldi16, { 0x90f00000 }, + & ifmt_ldi16, { 0x90f00000 }, (PTR) & fmt_ldi16_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -1984,7 +1878,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_LOCK, "lock", "lock", { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } }, - & fmt_lock, { 0x20d0 }, + & ifmt_add, { 0x20d0 }, (PTR) & fmt_lock_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -1993,7 +1887,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACHI, "machi", "machi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_machi, { 0x3040 }, + & ifmt_cmp, { 0x3040 }, (PTR) & fmt_machi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2003,7 +1897,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACHI_A, "machi-a", "machi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_machi_a, { 0x3040 }, + & ifmt_machi_a, { 0x3040 }, (PTR) & fmt_machi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2013,7 +1907,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACLO, "maclo", "maclo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_machi, { 0x3050 }, + & ifmt_cmp, { 0x3050 }, (PTR) & fmt_machi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2023,7 +1917,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACLO_A, "maclo-a", "maclo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_machi_a, { 0x3050 }, + & ifmt_machi_a, { 0x3050 }, (PTR) & fmt_machi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2033,7 +1927,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACWHI, "macwhi", "macwhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_machi, { 0x3060 }, + & ifmt_cmp, { 0x3060 }, (PTR) & fmt_machi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2043,7 +1937,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_machi_a, { 0x3060 }, + & ifmt_machi_a, { 0x3060 }, (PTR) & fmt_machi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } }, @@ -2053,7 +1947,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACWLO, "macwlo", "macwlo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_machi, { 0x3070 }, + & ifmt_cmp, { 0x3070 }, (PTR) & fmt_machi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2063,7 +1957,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_machi_a, { 0x3070 }, + & ifmt_machi_a, { 0x3070 }, (PTR) & fmt_machi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } }, @@ -2073,7 +1967,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MUL, "mul", "mul", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0x1060 }, + & ifmt_add, { 0x1060 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_S } } }, @@ -2082,7 +1976,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULHI, "mulhi", "mulhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_mulhi, { 0x3000 }, + & ifmt_cmp, { 0x3000 }, (PTR) & fmt_mulhi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2092,7 +1986,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULHI_A, "mulhi-a", "mulhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_mulhi_a, { 0x3000 }, + & ifmt_machi_a, { 0x3000 }, (PTR) & fmt_mulhi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2102,7 +1996,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULLO, "mullo", "mullo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_mulhi, { 0x3010 }, + & ifmt_cmp, { 0x3010 }, (PTR) & fmt_mulhi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2112,7 +2006,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULLO_A, "mullo-a", "mullo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_mulhi_a, { 0x3010 }, + & ifmt_machi_a, { 0x3010 }, (PTR) & fmt_mulhi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2122,7 +2016,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULWHI, "mulwhi", "mulwhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_mulhi, { 0x3020 }, + & ifmt_cmp, { 0x3020 }, (PTR) & fmt_mulhi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2132,7 +2026,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_mulhi_a, { 0x3020 }, + & ifmt_machi_a, { 0x3020 }, (PTR) & fmt_mulhi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } }, @@ -2142,7 +2036,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULWLO, "mulwlo", "mulwlo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_mulhi, { 0x3030 }, + & ifmt_cmp, { 0x3030 }, (PTR) & fmt_mulhi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2152,7 +2046,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, - & fmt_mulhi_a, { 0x3030 }, + & ifmt_machi_a, { 0x3030 }, (PTR) & fmt_mulhi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } } }, @@ -2162,7 +2056,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MV, "mv", "mv", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_mv, { 0x1080 }, + & ifmt_add, { 0x1080 }, (PTR) & fmt_mv_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2171,7 +2065,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACHI, "mvfachi", "mvfachi", { { MNEM, ' ', OP (DR), 0 } }, - & fmt_mvfachi, { 0x50f0 }, + & ifmt_mvfachi, { 0x50f0 }, (PTR) & fmt_mvfachi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2181,7 +2075,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & fmt_mvfachi_a, { 0x50f0 }, + & ifmt_mvfachi_a, { 0x50f0 }, (PTR) & fmt_mvfachi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2191,7 +2085,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", { { MNEM, ' ', OP (DR), 0 } }, - & fmt_mvfachi, { 0x50f1 }, + & ifmt_mvfachi, { 0x50f1 }, (PTR) & fmt_mvfachi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2201,7 +2095,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & fmt_mvfachi_a, { 0x50f1 }, + & ifmt_mvfachi_a, { 0x50f1 }, (PTR) & fmt_mvfachi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2211,7 +2105,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", { { MNEM, ' ', OP (DR), 0 } }, - & fmt_mvfachi, { 0x50f2 }, + & ifmt_mvfachi, { 0x50f2 }, (PTR) & fmt_mvfachi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2221,7 +2115,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } }, - & fmt_mvfachi_a, { 0x50f2 }, + & ifmt_mvfachi_a, { 0x50f2 }, (PTR) & fmt_mvfachi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2231,7 +2125,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVFC, "mvfc", "mvfc", { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } }, - & fmt_mvfc, { 0x1090 }, + & ifmt_mvfc, { 0x1090 }, (PTR) & fmt_mvfc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2240,7 +2134,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVTACHI, "mvtachi", "mvtachi", { { MNEM, ' ', OP (SRC1), 0 } }, - & fmt_mvtachi, { 0x5070 }, + & ifmt_mvtachi, { 0x5070 }, (PTR) & fmt_mvtachi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2250,7 +2144,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, - & fmt_mvtachi_a, { 0x5070 }, + & ifmt_mvtachi_a, { 0x5070 }, (PTR) & fmt_mvtachi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2260,7 +2154,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", { { MNEM, ' ', OP (SRC1), 0 } }, - & fmt_mvtachi, { 0x5071 }, + & ifmt_mvtachi, { 0x5071 }, (PTR) & fmt_mvtachi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2270,7 +2164,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } }, - & fmt_mvtachi_a, { 0x5071 }, + & ifmt_mvtachi_a, { 0x5071 }, (PTR) & fmt_mvtachi_a_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2280,7 +2174,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MVTC, "mvtc", "mvtc", { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } }, - & fmt_mvtc, { 0x10a0 }, + & ifmt_mvtc, { 0x10a0 }, (PTR) & fmt_mvtc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2289,7 +2183,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_NEG, "neg", "neg", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_mv, { 0x30 }, + & ifmt_add, { 0x30 }, (PTR) & fmt_mv_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2298,7 +2192,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_NOP, "nop", "nop", { { MNEM, 0 } }, - & fmt_nop, { 0x7000 }, + & ifmt_nop, { 0x7000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2307,7 +2201,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_NOT, "not", "not", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_mv, { 0xb0 }, + & ifmt_add, { 0xb0 }, (PTR) & fmt_mv_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2316,7 +2210,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_RAC, "rac", "rac", { { MNEM, 0 } }, - & fmt_rac, { 0x5090 }, + & ifmt_nop, { 0x5090 }, (PTR) & fmt_rac_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2326,7 +2220,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_RAC_DSI, "rac-dsi", "rac", { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, - & fmt_rac_dsi, { 0x5090 }, + & ifmt_rac_dsi, { 0x5090 }, (PTR) & fmt_rac_dsi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2336,7 +2230,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_RACH, "rach", "rach", { { MNEM, 0 } }, - & fmt_rac, { 0x5080 }, + & ifmt_nop, { 0x5080 }, (PTR) & fmt_rac_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } } }, @@ -2346,7 +2240,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_RACH_DSI, "rach-dsi", "rach", { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } }, - & fmt_rac_dsi, { 0x5080 }, + & ifmt_rac_dsi, { 0x5080 }, (PTR) & fmt_rac_dsi_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2356,7 +2250,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_RTE, "rte", "rte", { { MNEM, 0 } }, - & fmt_rte, { 0x10d6 }, + & ifmt_nop, { 0x10d6 }, (PTR) & fmt_rte_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -2365,7 +2259,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SETH, "seth", "seth", { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } }, - & fmt_seth, { 0xd0c00000 }, + & ifmt_seth, { 0xd0c00000 }, (PTR) & fmt_seth_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2374,7 +2268,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SLL, "sll", "sll", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0x1040 }, + & ifmt_add, { 0x1040 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2383,7 +2277,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SLL3, "sll3", "sll3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & fmt_sll3, { 0x90c00000 }, + & ifmt_addv3, { 0x90c00000 }, (PTR) & fmt_sll3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2392,7 +2286,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SLLI, "slli", "slli", { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & fmt_slli, { 0x5040 }, + & ifmt_slli, { 0x5040 }, (PTR) & fmt_slli_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2401,7 +2295,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRA, "sra", "sra", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0x1020 }, + & ifmt_add, { 0x1020 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2410,7 +2304,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRA3, "sra3", "sra3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & fmt_sll3, { 0x90a00000 }, + & ifmt_addv3, { 0x90a00000 }, (PTR) & fmt_sll3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2419,7 +2313,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRAI, "srai", "srai", { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & fmt_slli, { 0x5020 }, + & ifmt_slli, { 0x5020 }, (PTR) & fmt_slli_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2428,7 +2322,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRL, "srl", "srl", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0x1000 }, + & ifmt_add, { 0x1000 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2437,7 +2331,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRL3, "srl3", "srl3", { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }, - & fmt_sll3, { 0x90800000 }, + & ifmt_addv3, { 0x90800000 }, (PTR) & fmt_sll3_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2446,7 +2340,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SRLI, "srli", "srli", { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } }, - & fmt_slli, { 0x5000 }, + & ifmt_slli, { 0x5000 }, (PTR) & fmt_slli_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2455,7 +2349,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ST, "st", "st", { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & fmt_st, { 0x2040 }, + & ifmt_cmp, { 0x2040 }, (PTR) & fmt_st_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2464,7 +2358,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ST_D, "st-d", "st", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & fmt_st_d, { 0xa0400000 }, + & ifmt_st_d, { 0xa0400000 }, (PTR) & fmt_st_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2473,7 +2367,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_STB, "stb", "stb", { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & fmt_stb, { 0x2000 }, + & ifmt_cmp, { 0x2000 }, (PTR) & fmt_stb_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2482,7 +2376,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_STB_D, "stb-d", "stb", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & fmt_stb_d, { 0xa0000000 }, + & ifmt_st_d, { 0xa0000000 }, (PTR) & fmt_stb_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2491,7 +2385,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_STH, "sth", "sth", { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & fmt_sth, { 0x2020 }, + & ifmt_cmp, { 0x2020 }, (PTR) & fmt_sth_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2500,7 +2394,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_STH_D, "sth-d", "sth", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } }, - & fmt_sth_d, { 0xa0200000 }, + & ifmt_st_d, { 0xa0200000 }, (PTR) & fmt_sth_d_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2509,7 +2403,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ST_PLUS, "st-plus", "st", { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } }, - & fmt_st_plus, { 0x2060 }, + & ifmt_cmp, { 0x2060 }, (PTR) & fmt_st_plus_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2518,7 +2412,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_ST_MINUS, "st-minus", "st", { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } }, - & fmt_st_plus, { 0x2070 }, + & ifmt_cmp, { 0x2070 }, (PTR) & fmt_st_plus_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2527,7 +2421,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SUB, "sub", "sub", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_add, { 0x20 }, + & ifmt_add, { 0x20 }, (PTR) & fmt_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2536,7 +2430,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SUBV, "subv", "subv", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_addv, { 0x0 }, + & ifmt_add, { 0x0 }, (PTR) & fmt_addv_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2545,7 +2439,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SUBX, "subx", "subx", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_addx, { 0x10 }, + & ifmt_add, { 0x10 }, (PTR) & fmt_addx_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_OS } } }, @@ -2554,7 +2448,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_TRAP, "trap", "trap", { { MNEM, ' ', OP (UIMM4), 0 } }, - & fmt_trap, { 0x10f0 }, + & ifmt_trap, { 0x10f0 }, (PTR) & fmt_trap_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } } }, @@ -2563,7 +2457,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_UNLOCK, "unlock", "unlock", { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } }, - & fmt_unlock, { 0x2050 }, + & ifmt_cmp, { 0x2050 }, (PTR) & fmt_unlock_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE), PIPE_O } } }, @@ -2573,7 +2467,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SATB, "satb", "satb", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_satb, { 0x80600300 }, + & ifmt_satb, { 0x80600300 }, (PTR) & fmt_satb_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -2584,7 +2478,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SATH, "sath", "sath", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_satb, { 0x80600200 }, + & ifmt_satb, { 0x80600200 }, (PTR) & fmt_satb_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -2595,7 +2489,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SAT, "sat", "sat", { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, - & fmt_sat, { 0x80600000 }, + & ifmt_satb, { 0x80600000 }, (PTR) & fmt_sat_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -2606,7 +2500,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", { { MNEM, ' ', OP (SRC2), 0 } }, - & fmt_cmpz, { 0x370 }, + & ifmt_cmpz, { 0x370 }, (PTR) & fmt_cmpz_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } } }, @@ -2617,7 +2511,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SADD, "sadd", "sadd", { { MNEM, 0 } }, - & fmt_sadd, { 0x50e4 }, + & ifmt_sadd, { 0x50e4 }, (PTR) & fmt_sadd_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2628,7 +2522,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACWU1, "macwu1", "macwu1", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_macwu1, { 0x50b0 }, + & ifmt_cmpeq, { 0x50b0 }, (PTR) & fmt_macwu1_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2639,8 +2533,8 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MSBLO, "msblo", "msblo", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_machi, { 0x50d0 }, - (PTR) & fmt_machi_ops[0], + & ifmt_cmpeq, { 0x50d0 }, + (PTR) & fmt_msblo_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, /* end-sanitize-m32rx */ @@ -2650,7 +2544,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MULWU1, "mulwu1", "mulwu1", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_mulwu1, { 0x50a0 }, + & ifmt_cmpeq, { 0x50a0 }, (PTR) & fmt_mulwu1_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2661,7 +2555,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_MACLH1, "maclh1", "maclh1", { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } }, - & fmt_macwu1, { 0x50c0 }, + & ifmt_cmpeq, { 0x50c0 }, (PTR) & fmt_macwu1_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } } }, @@ -2672,7 +2566,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SC, "sc", "sc", { { MNEM, 0 } }, - & fmt_sc, { 0x7401 }, + & ifmt_sadd, { 0x7401 }, (PTR) & fmt_sc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -2683,7 +2577,7 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = { 1, 1, 1, 1 }, M32R_INSN_SNC, "snc", "snc", { { MNEM, 0 } }, - & fmt_sc, { 0x7501 }, + & ifmt_sadd, { 0x7501 }, (PTR) & fmt_sc_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } } }, @@ -2706,163 +2600,163 @@ static const CGEN_INSN_TABLE insn_table = #define F(f) & m32r_cgen_ifld_table[CONCAT2 (M32R_,f)] -static const CGEN_IFMT fmt_bc8r = { +static const CGEN_IFMT ifmt_bc8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; -static const CGEN_IFMT fmt_bc24r = { +static const CGEN_IFMT ifmt_bc24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; -static const CGEN_IFMT fmt_bl8r = { +static const CGEN_IFMT ifmt_bl8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; -static const CGEN_IFMT fmt_bl24r = { +static const CGEN_IFMT ifmt_bl24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bcl8r = { +static const CGEN_IFMT ifmt_bcl8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bcl24r = { +static const CGEN_IFMT ifmt_bcl24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_bnc8r = { +static const CGEN_IFMT ifmt_bnc8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; -static const CGEN_IFMT fmt_bnc24r = { +static const CGEN_IFMT ifmt_bnc24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; -static const CGEN_IFMT fmt_bra8r = { +static const CGEN_IFMT ifmt_bra8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; -static const CGEN_IFMT fmt_bra24r = { +static const CGEN_IFMT ifmt_bra24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bncl8r = { +static const CGEN_IFMT ifmt_bncl8r = { 16, 16, 0xff00, { F (F_OP1), F (F_R1), F (F_DISP8), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_bncl24r = { +static const CGEN_IFMT ifmt_bncl24r = { 32, 32, 0xff000000, { F (F_OP1), F (F_R1), F (F_DISP24), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_ld_2 = { +static const CGEN_IFMT ifmt_ld_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ld_d2 = { +static const CGEN_IFMT ifmt_ld_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_ldb_2 = { +static const CGEN_IFMT ifmt_ldb_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ldb_d2 = { +static const CGEN_IFMT ifmt_ldb_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_ldh_2 = { +static const CGEN_IFMT ifmt_ldh_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ldh_d2 = { +static const CGEN_IFMT ifmt_ldh_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_ldub_2 = { +static const CGEN_IFMT ifmt_ldub_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ldub_d2 = { +static const CGEN_IFMT ifmt_ldub_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_lduh_2 = { +static const CGEN_IFMT ifmt_lduh_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_lduh_d2 = { +static const CGEN_IFMT ifmt_lduh_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_pop = { +static const CGEN_IFMT ifmt_pop = { 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_ldi8a = { +static const CGEN_IFMT ifmt_ldi8a = { 16, 16, 0xf000, { F (F_OP1), F (F_R1), F (F_SIMM8), 0 } }; -static const CGEN_IFMT fmt_ldi16a = { +static const CGEN_IFMT ifmt_ldi16a = { 32, 32, 0xf0ff0000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_rac_d = { +static const CGEN_IFMT ifmt_rac_d = { 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_rac_ds = { +static const CGEN_IFMT ifmt_rac_ds = { 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_rach_d = { +static const CGEN_IFMT ifmt_rach_d = { 16, 16, 0xf3ff, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } }; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ -static const CGEN_IFMT fmt_rach_ds = { +static const CGEN_IFMT ifmt_rach_ds = { 16, 16, 0xf3f3, { F (F_OP1), F (F_ACCD), F (F_BITS67), F (F_OP2), F (F_ACCS), F (F_BIT14), F (F_IMM1), 0 } }; /* end-sanitize-m32rx */ -static const CGEN_IFMT fmt_st_2 = { +static const CGEN_IFMT ifmt_st_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_st_d2 = { +static const CGEN_IFMT ifmt_st_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_stb_2 = { +static const CGEN_IFMT ifmt_stb_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_stb_d2 = { +static const CGEN_IFMT ifmt_stb_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_sth_2 = { +static const CGEN_IFMT ifmt_sth_2 = { 16, 16, 0xf0f0, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; -static const CGEN_IFMT fmt_sth_d2 = { +static const CGEN_IFMT ifmt_sth_d2 = { 32, 32, 0xf0f00000, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), F (F_SIMM16), 0 } }; -static const CGEN_IFMT fmt_push = { +static const CGEN_IFMT ifmt_push = { 16, 16, 0xf0ff, { F (F_OP1), F (F_R1), F (F_OP2), F (F_R2), 0 } }; @@ -2883,7 +2777,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bc8r", "bc", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bc8r, { 0x7c00 }, + & ifmt_bc8r, { 0x7c00 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -2892,7 +2786,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bc24r", "bc", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bc24r, { 0xfc000000 }, + & ifmt_bc24r, { 0xfc000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2901,7 +2795,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bl8r", "bl", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bl8r, { 0x7e00 }, + & ifmt_bl8r, { 0x7e00 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -2910,7 +2804,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bl24r", "bl", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bl24r, { 0xfe000000 }, + & ifmt_bl24r, { 0xfe000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2920,7 +2814,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bcl8r", "bcl", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bcl8r, { 0x7800 }, + & ifmt_bcl8r, { 0x7800 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } }, @@ -2931,7 +2825,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bcl24r", "bcl", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bcl24r, { 0xf8000000 }, + & ifmt_bcl24r, { 0xf8000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -2941,7 +2835,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bnc8r", "bnc", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bnc8r, { 0x7d00 }, + & ifmt_bnc8r, { 0x7d00 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -2950,7 +2844,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bnc24r", "bnc", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bnc24r, { 0xfd000000 }, + & ifmt_bnc24r, { 0xfd000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2959,7 +2853,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bra8r", "bra", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bra8r, { 0x7f00 }, + & ifmt_bra8r, { 0x7f00 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -2968,7 +2862,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bra24r", "bra", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bra24r, { 0xff000000 }, + & ifmt_bra24r, { 0xff000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -2978,7 +2872,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bncl8r", "bncl", { { MNEM, ' ', OP (DISP8), 0 } }, - & fmt_bncl8r, { 0x7900 }, + & ifmt_bncl8r, { 0x7900 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_O } } }, @@ -2989,7 +2883,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "bncl24r", "bncl", { { MNEM, ' ', OP (DISP24), 0 } }, - & fmt_bncl24r, { 0xf9000000 }, + & ifmt_bncl24r, { 0xf9000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX), PIPE_NONE } } }, @@ -2999,7 +2893,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ld-2", "ld", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & fmt_ld_2, { 0x20c0 }, + & ifmt_ld_2, { 0x20c0 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3008,7 +2902,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ld-d2", "ld", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & fmt_ld_d2, { 0xa0c00000 }, + & ifmt_ld_d2, { 0xa0c00000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3017,7 +2911,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldb-2", "ldb", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & fmt_ldb_2, { 0x2080 }, + & ifmt_ldb_2, { 0x2080 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3026,7 +2920,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldb-d2", "ldb", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & fmt_ldb_d2, { 0xa0800000 }, + & ifmt_ldb_d2, { 0xa0800000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3035,7 +2929,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldh-2", "ldh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & fmt_ldh_2, { 0x20a0 }, + & ifmt_ldh_2, { 0x20a0 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3044,7 +2938,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldh-d2", "ldh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & fmt_ldh_d2, { 0xa0a00000 }, + & ifmt_ldh_d2, { 0xa0a00000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3053,7 +2947,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldub-2", "ldub", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & fmt_ldub_2, { 0x2090 }, + & ifmt_ldub_2, { 0x2090 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3062,7 +2956,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldub-d2", "ldub", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & fmt_ldub_d2, { 0xa0900000 }, + & ifmt_ldub_d2, { 0xa0900000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3071,7 +2965,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "lduh-2", "lduh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } }, - & fmt_lduh_2, { 0x20b0 }, + & ifmt_lduh_2, { 0x20b0 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3080,7 +2974,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "lduh-d2", "lduh", { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } }, - & fmt_lduh_d2, { 0xa0b00000 }, + & ifmt_lduh_d2, { 0xa0b00000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3089,7 +2983,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "pop", "pop", { { MNEM, ' ', OP (DR), 0 } }, - & fmt_pop, { 0x20ef }, + & ifmt_pop, { 0x20ef }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3098,7 +2992,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldi8a", "ldi", { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } }, - & fmt_ldi8a, { 0x6000 }, + & ifmt_ldi8a, { 0x6000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } } }, @@ -3107,7 +3001,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "ldi16a", "ldi", { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } }, - & fmt_ldi16a, { 0x90f00000 }, + & ifmt_ldi16a, { 0x90f00000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3117,7 +3011,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "rac-d", "rac", { { MNEM, ' ', OP (ACCD), 0 } }, - & fmt_rac_d, { 0x5090 }, + & ifmt_rac_d, { 0x5090 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } }, @@ -3128,7 +3022,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "rac-ds", "rac", { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, - & fmt_rac_ds, { 0x5090 }, + & ifmt_rac_ds, { 0x5090 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } }, @@ -3139,7 +3033,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "rach-d", "rach", { { MNEM, ' ', OP (ACCD), 0 } }, - & fmt_rach_d, { 0x5080 }, + & ifmt_rach_d, { 0x5080 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } }, @@ -3150,7 +3044,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "rach-ds", "rach", { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } }, - & fmt_rach_ds, { 0x5080 }, + & ifmt_rach_ds, { 0x5080 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32RX), PIPE_S } } }, @@ -3160,7 +3054,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "st-2", "st", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & fmt_st_2, { 0x2040 }, + & ifmt_st_2, { 0x2040 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3169,7 +3063,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "st-d2", "st", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & fmt_st_d2, { 0xa0400000 }, + & ifmt_st_d2, { 0xa0400000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3178,7 +3072,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "stb-2", "stb", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & fmt_stb_2, { 0x2000 }, + & ifmt_stb_2, { 0x2000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3187,7 +3081,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "stb-d2", "stb", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & fmt_stb_d2, { 0xa0000000 }, + & ifmt_stb_d2, { 0xa0000000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3196,7 +3090,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "sth-2", "sth", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } }, - & fmt_sth_2, { 0x2020 }, + & ifmt_sth_2, { 0x2020 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } } }, @@ -3205,7 +3099,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "sth-d2", "sth", { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } }, - & fmt_sth_d2, { 0xa0200000 }, + & ifmt_sth_d2, { 0xa0200000 }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, @@ -3214,7 +3108,7 @@ static const CGEN_INSN macro_insn_table_entries[] = { 1, 1, 1, 1 }, -1, "push", "push", { { MNEM, ' ', OP (SRC1), 0 } }, - & fmt_push, { 0x207f }, + & ifmt_push, { 0x207f }, (PTR) 0, { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } } }, |