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Diffstat (limited to 'opcodes/m32r-desc.c')
-rw-r--r--opcodes/m32r-desc.c557
1 files changed, 277 insertions, 280 deletions
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 3b8cb56..c9cd3bb 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -148,25 +148,25 @@ static const CGEN_MACH m32r_cgen_mach_table[] = {
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
{
- { "fp", 13, {0, {0}}, 0, 0 },
- { "lr", 14, {0, {0}}, 0, 0 },
- { "sp", 15, {0, {0}}, 0, 0 },
- { "r0", 0, {0, {0}}, 0, 0 },
- { "r1", 1, {0, {0}}, 0, 0 },
- { "r2", 2, {0, {0}}, 0, 0 },
- { "r3", 3, {0, {0}}, 0, 0 },
- { "r4", 4, {0, {0}}, 0, 0 },
- { "r5", 5, {0, {0}}, 0, 0 },
- { "r6", 6, {0, {0}}, 0, 0 },
- { "r7", 7, {0, {0}}, 0, 0 },
- { "r8", 8, {0, {0}}, 0, 0 },
- { "r9", 9, {0, {0}}, 0, 0 },
- { "r10", 10, {0, {0}}, 0, 0 },
- { "r11", 11, {0, {0}}, 0, 0 },
- { "r12", 12, {0, {0}}, 0, 0 },
- { "r13", 13, {0, {0}}, 0, 0 },
- { "r14", 14, {0, {0}}, 0, 0 },
- { "r15", 15, {0, {0}}, 0, 0 }
+ { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
+ { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD m32r_cgen_opval_gr_names =
@@ -178,30 +178,30 @@ CGEN_KEYWORD m32r_cgen_opval_gr_names =
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
{
- { "psw", 0, {0, {0}}, 0, 0 },
- { "cbr", 1, {0, {0}}, 0, 0 },
- { "spi", 2, {0, {0}}, 0, 0 },
- { "spu", 3, {0, {0}}, 0, 0 },
- { "bpc", 6, {0, {0}}, 0, 0 },
- { "bbpsw", 8, {0, {0}}, 0, 0 },
- { "bbpc", 14, {0, {0}}, 0, 0 },
- { "evb", 5, {0, {0}}, 0, 0 },
- { "cr0", 0, {0, {0}}, 0, 0 },
- { "cr1", 1, {0, {0}}, 0, 0 },
- { "cr2", 2, {0, {0}}, 0, 0 },
- { "cr3", 3, {0, {0}}, 0, 0 },
- { "cr4", 4, {0, {0}}, 0, 0 },
- { "cr5", 5, {0, {0}}, 0, 0 },
- { "cr6", 6, {0, {0}}, 0, 0 },
- { "cr7", 7, {0, {0}}, 0, 0 },
- { "cr8", 8, {0, {0}}, 0, 0 },
- { "cr9", 9, {0, {0}}, 0, 0 },
- { "cr10", 10, {0, {0}}, 0, 0 },
- { "cr11", 11, {0, {0}}, 0, 0 },
- { "cr12", 12, {0, {0}}, 0, 0 },
- { "cr13", 13, {0, {0}}, 0, 0 },
- { "cr14", 14, {0, {0}}, 0, 0 },
- { "cr15", 15, {0, {0}}, 0, 0 }
+ { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
+ { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD m32r_cgen_opval_cr_names =
@@ -213,8 +213,8 @@ CGEN_KEYWORD m32r_cgen_opval_cr_names =
static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
{
- { "a0", 0, {0, {0}}, 0, 0 },
- { "a1", 1, {0, {0}}, 0, 0 }
+ { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD m32r_cgen_opval_h_accums =
@@ -235,25 +235,25 @@ CGEN_KEYWORD m32r_cgen_opval_h_accums =
const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
{
- { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
- { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
- { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
- { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
- { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
- { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
+ { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -269,36 +269,36 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
const CGEN_IFLD m32r_cgen_ifld_table[] =
{
- { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
- { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
- { 0, 0, 0, 0, 0, 0, {0, {0}} }
+ { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -330,119 +330,119 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
- { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm3: 3 bit unsigned number */
{ "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm8: 8 bit unsigned immediate */
{ "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
- { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
+ { 0|A(HASH_PREFIX), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
- { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+ { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
- { 0, { (1<<MACH_BASE) } } },
+ { 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
- { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
- { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
- { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
{ 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
- { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, { (const PTR) 0 } },
- { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
{ 0, { (const PTR) 0 } },
- { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
- { 0, { 0 } } }
+ { 0, { { { (1<<MACH_BASE), 0 } } } } }
};
#undef A
@@ -462,746 +462,746 @@ static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
/* Special null first entry.
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, {0, {0}} },
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
/* add $dr,$sr */
{
M32R_INSN_ADD, "add", "add", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* add3 $dr,$sr,$hash$slo16 */
{
M32R_INSN_ADD3, "add3", "add3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* and $dr,$sr */
{
M32R_INSN_AND, "and", "and", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* and3 $dr,$sr,$uimm16 */
{
M32R_INSN_AND3, "and3", "and3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* or $dr,$sr */
{
M32R_INSN_OR, "or", "or", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* or3 $dr,$sr,$hash$ulo16 */
{
M32R_INSN_OR3, "or3", "or3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* xor $dr,$sr */
{
M32R_INSN_XOR, "xor", "xor", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* xor3 $dr,$sr,$uimm16 */
{
M32R_INSN_XOR3, "xor3", "xor3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* addi $dr,$simm8 */
{
M32R_INSN_ADDI, "addi", "addi", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* addv $dr,$sr */
{
M32R_INSN_ADDV, "addv", "addv", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* addv3 $dr,$sr,$simm16 */
{
M32R_INSN_ADDV3, "addv3", "addv3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* addx $dr,$sr */
{
M32R_INSN_ADDX, "addx", "addx", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* bc.s $disp8 */
{
M32R_INSN_BC8, "bc8", "bc.s", 16,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bc.l $disp24 */
{
M32R_INSN_BC24, "bc24", "bc.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* beq $src1,$src2,$disp16 */
{
M32R_INSN_BEQ, "beq", "beq", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* beqz $src2,$disp16 */
{
M32R_INSN_BEQZ, "beqz", "beqz", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bgez $src2,$disp16 */
{
M32R_INSN_BGEZ, "bgez", "bgez", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bgtz $src2,$disp16 */
{
M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* blez $src2,$disp16 */
{
M32R_INSN_BLEZ, "blez", "blez", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bltz $src2,$disp16 */
{
M32R_INSN_BLTZ, "bltz", "bltz", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bnez $src2,$disp16 */
{
M32R_INSN_BNEZ, "bnez", "bnez", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bl.s $disp8 */
{
M32R_INSN_BL8, "bl8", "bl.s", 16,
- { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bl.l $disp24 */
{
M32R_INSN_BL24, "bl24", "bl.l", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bcl.s $disp8 */
{
M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* bcl.l $disp24 */
{
M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bnc.s $disp8 */
{
M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bnc.l $disp24 */
{
M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bne $src1,$src2,$disp16 */
{
M32R_INSN_BNE, "bne", "bne", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bra.s $disp8 */
{
M32R_INSN_BRA8, "bra8", "bra.s", 16,
- { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bra.l $disp24 */
{
M32R_INSN_BRA24, "bra24", "bra.l", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bncl.s $disp8 */
{
M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
- { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* bncl.l $disp24 */
{
M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
- { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* cmp $src1,$src2 */
{
M32R_INSN_CMP, "cmp", "cmp", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* cmpi $src2,$simm16 */
{
M32R_INSN_CMPI, "cmpi", "cmpi", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* cmpu $src1,$src2 */
{
M32R_INSN_CMPU, "cmpu", "cmpu", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* cmpui $src2,$simm16 */
{
M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* cmpeq $src1,$src2 */
{
M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
},
/* cmpz $src2 */
{
M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
},
/* div $dr,$sr */
{
M32R_INSN_DIV, "div", "div", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* divu $dr,$sr */
{
M32R_INSN_DIVU, "divu", "divu", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* rem $dr,$sr */
{
M32R_INSN_REM, "rem", "rem", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* remu $dr,$sr */
{
M32R_INSN_REMU, "remu", "remu", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* remh $dr,$sr */
{
M32R_INSN_REMH, "remh", "remh", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* remuh $dr,$sr */
{
M32R_INSN_REMUH, "remuh", "remuh", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* remb $dr,$sr */
{
M32R_INSN_REMB, "remb", "remb", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* remub $dr,$sr */
{
M32R_INSN_REMUB, "remub", "remub", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* divuh $dr,$sr */
{
M32R_INSN_DIVUH, "divuh", "divuh", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* divb $dr,$sr */
{
M32R_INSN_DIVB, "divb", "divb", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* divub $dr,$sr */
{
M32R_INSN_DIVUB, "divub", "divub", 32,
- { 0, { (1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* divh $dr,$sr */
{
M32R_INSN_DIVH, "divh", "divh", 32,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* jc $sr */
{
M32R_INSN_JC, "jc", "jc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* jnc $sr */
{
M32R_INSN_JNC, "jnc", "jnc", 16,
- { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* jl $sr */
{
M32R_INSN_JL, "jl", "jl", 16,
- { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* jmp $sr */
{
M32R_INSN_JMP, "jmp", "jmp", 16,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ld $dr,@$sr */
{
M32R_INSN_LD, "ld", "ld", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ld $dr,@($slo16,$sr) */
{
M32R_INSN_LD_D, "ld-d", "ld", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldb $dr,@$sr */
{
M32R_INSN_LDB, "ldb", "ldb", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldb $dr,@($slo16,$sr) */
{
M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldh $dr,@$sr */
{
M32R_INSN_LDH, "ldh", "ldh", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldh $dr,@($slo16,$sr) */
{
M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldub $dr,@$sr */
{
M32R_INSN_LDUB, "ldub", "ldub", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ldub $dr,@($slo16,$sr) */
{
M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* lduh $dr,@$sr */
{
M32R_INSN_LDUH, "lduh", "lduh", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* lduh $dr,@($slo16,$sr) */
{
M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ld $dr,@$sr+ */
{
M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* ld24 $dr,$uimm24 */
{
M32R_INSN_LD24, "ld24", "ld24", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* ldi8 $dr,$simm8 */
{
M32R_INSN_LDI8, "ldi8", "ldi8", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* ldi16 $dr,$hash$slo16 */
{
M32R_INSN_LDI16, "ldi16", "ldi16", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* lock $dr,@$sr */
{
M32R_INSN_LOCK, "lock", "lock", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* machi $src1,$src2 */
{
M32R_INSN_MACHI, "machi", "machi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* machi $src1,$src2,$acc */
{
M32R_INSN_MACHI_A, "machi-a", "machi", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* maclo $src1,$src2 */
{
M32R_INSN_MACLO, "maclo", "maclo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* maclo $src1,$src2,$acc */
{
M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* macwhi $src1,$src2 */
{
M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* macwhi $src1,$src2,$acc */
{
M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* macwlo $src1,$src2 */
{
M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* macwlo $src1,$src2,$acc */
{
M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mul $dr,$sr */
{
M32R_INSN_MUL, "mul", "mul", 16,
- { 0, { (1<<MACH_BASE), PIPE_S } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulhi $src1,$src2 */
{
M32R_INSN_MULHI, "mulhi", "mulhi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulhi $src1,$src2,$acc */
{
M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mullo $src1,$src2 */
{
M32R_INSN_MULLO, "mullo", "mullo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mullo $src1,$src2,$acc */
{
M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulwhi $src1,$src2 */
{
M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulwhi $src1,$src2,$acc */
{
M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulwlo $src1,$src2 */
{
M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulwlo $src1,$src2,$acc */
{
M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mv $dr,$sr */
{
M32R_INSN_MV, "mv", "mv", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* mvfachi $dr */
{
M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfachi $dr,$accs */
{
M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfaclo $dr */
{
M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfaclo $dr,$accs */
{
M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfacmi $dr */
{
M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfacmi $dr,$accs */
{
M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvfc $dr,$scr */
{
M32R_INSN_MVFC, "mvfc", "mvfc", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* mvtachi $src1 */
{
M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvtachi $src1,$accs */
{
M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvtaclo $src1 */
{
M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvtaclo $src1,$accs */
{
M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mvtc $sr,$dcr */
{
M32R_INSN_MVTC, "mvtc", "mvtc", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* neg $dr,$sr */
{
M32R_INSN_NEG, "neg", "neg", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* nop */
{
M32R_INSN_NOP, "nop", "nop", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* not $dr,$sr */
{
M32R_INSN_NOT, "not", "not", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* rac */
{
M32R_INSN_RAC, "rac", "rac", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* rac $accd,$accs,$imm1 */
{
M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* rach */
{
M32R_INSN_RACH, "rach", "rach", 16,
- { 0, { (1<<MACH_M32R), PIPE_S } }
+ { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
},
/* rach $accd,$accs,$imm1 */
{
M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* rte */
{
M32R_INSN_RTE, "rte", "rte", 16,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* seth $dr,$hash$hi16 */
{
M32R_INSN_SETH, "seth", "seth", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* sll $dr,$sr */
{
M32R_INSN_SLL, "sll", "sll", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* sll3 $dr,$sr,$simm16 */
{
M32R_INSN_SLL3, "sll3", "sll3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* slli $dr,$uimm5 */
{
M32R_INSN_SLLI, "slli", "slli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* sra $dr,$sr */
{
M32R_INSN_SRA, "sra", "sra", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* sra3 $dr,$sr,$simm16 */
{
M32R_INSN_SRA3, "sra3", "sra3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* srai $dr,$uimm5 */
{
M32R_INSN_SRAI, "srai", "srai", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* srl $dr,$sr */
{
M32R_INSN_SRL, "srl", "srl", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* srl3 $dr,$sr,$simm16 */
{
M32R_INSN_SRL3, "srl3", "srl3", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* srli $dr,$uimm5 */
{
M32R_INSN_SRLI, "srli", "srli", 16,
- { 0, { (1<<MACH_BASE), PIPE_O_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
},
/* st $src1,@$src2 */
{
M32R_INSN_ST, "st", "st", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* st $src1,@($slo16,$src2) */
{
M32R_INSN_ST_D, "st-d", "st", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* stb $src1,@$src2 */
{
M32R_INSN_STB, "stb", "stb", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* stb $src1,@($slo16,$src2) */
{
M32R_INSN_STB_D, "stb-d", "stb", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* sth $src1,@$src2 */
{
M32R_INSN_STH, "sth", "sth", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* sth $src1,@($slo16,$src2) */
{
M32R_INSN_STH_D, "sth-d", "sth", 32,
- { 0, { (1<<MACH_BASE), PIPE_NONE } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* st $src1,@+$src2 */
{
M32R_INSN_ST_PLUS, "st-plus", "st", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* sth $src1,@$src2+ */
{
M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* stb $src1,@$src2+ */
{
M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* st $src1,@-$src2 */
{
M32R_INSN_ST_MINUS, "st-minus", "st", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* sub $dr,$sr */
{
M32R_INSN_SUB, "sub", "sub", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* subv $dr,$sr */
{
M32R_INSN_SUBV, "subv", "subv", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* subx $dr,$sr */
{
M32R_INSN_SUBX, "subx", "subx", 16,
- { 0, { (1<<MACH_BASE), PIPE_OS } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
},
/* trap $uimm4 */
{
M32R_INSN_TRAP, "trap", "trap", 16,
- { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* unlock $src1,@$src2 */
{
M32R_INSN_UNLOCK, "unlock", "unlock", 16,
- { 0, { (1<<MACH_BASE), PIPE_O } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* satb $dr,$sr */
{
M32R_INSN_SATB, "satb", "satb", 32,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* sath $dr,$sr */
{
M32R_INSN_SATH, "sath", "sath", 32,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* sat $dr,$sr */
{
M32R_INSN_SAT, "sat", "sat", 32,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* pcmpbz $src2 */
{
M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
- { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
+ { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
},
/* sadd */
{
M32R_INSN_SADD, "sadd", "sadd", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* macwu1 $src1,$src2 */
{
M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* msblo $src1,$src2 */
{
M32R_INSN_MSBLO, "msblo", "msblo", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* mulwu1 $src1,$src2 */
{
M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* maclh1 $src1,$src2 */
{
M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
- { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
+ { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
},
/* sc */
{
M32R_INSN_SC, "sc", "sc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* snc */
{
M32R_INSN_SNC, "snc", "snc", 16,
- { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
+ { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
},
/* clrpsw $uimm8 */
{
M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
- { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* setpsw $uimm8 */
{
M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
- { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
/* bset $uimm3,@($slo16,$sr) */
{
M32R_INSN_BSET, "bset", "bset", 32,
- { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* bclr $uimm3,@($slo16,$sr) */
{
M32R_INSN_BCLR, "bclr", "bclr", 32,
- { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
+ { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
},
/* btst $uimm3,$sr */
{
M32R_INSN_BTST, "btst", "btst", 16,
- { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
+ { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
},
};
@@ -1324,7 +1324,7 @@ static void
m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
{
int i;
- unsigned int isas = cd->isas;
+ CGEN_BITSET *isas = cd->isas;
unsigned int machs = cd->machs;
cd->int_insn_p = CGEN_INT_INSN_P;
@@ -1336,7 +1336,7 @@ m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
- if (((1 << i) & isas) != 0)
+ if (cgen_bitset_contains (isas, i))
{
const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
@@ -1421,7 +1421,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
- unsigned int isas = 0; /* 0 = "unspecified" */
+ CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
unsigned int machs = 0; /* 0 = "unspecified" */
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
@@ -1440,7 +1440,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
switch (arg_type)
{
case CGEN_CPU_OPEN_ISAS :
- isas = va_arg (ap, unsigned int);
+ isas = va_arg (ap, CGEN_BITSET *);
break;
case CGEN_CPU_OPEN_MACHS :
machs = va_arg (ap, unsigned int);
@@ -1471,9 +1471,6 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
machs = (1 << MAX_MACHS) - 1;
/* Base mach is always selected. */
machs |= 1;
- /* ISA unspecified means "all". */
- if (isas == 0)
- isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
@@ -1481,7 +1478,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
abort ();
}
- cd->isas = isas;
+ cd->isas = cgen_bitset_copy (isas);
cd->machs = machs;
cd->endian = endian;
/* FIXME: for the sparc case we can determine insn-endianness statically.
generated by cgit v1.1 at 2024-11-27 12:00:43 +0000