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Diffstat (limited to 'opcodes/m32r-desc.c')
-rw-r--r--opcodes/m32r-desc.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 32c2979..7e03602 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -312,115 +312,115 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm3: 3 bit unsigned number */
{ "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm8: 8 bit unsigned immediate */
{ "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
- { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
@@ -1468,7 +1468,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
@@ -1508,7 +1508,7 @@ m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
+ }
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
generated by cgit v1.1 at 2024-11-29 03:33:44 +0000